<Record><identifier xmlns="http://purl.org/dc/elements/1.1/">URN:NBN:SI:DOC-UWBQJB9J</identifier><date>2018</date><creator>Fajfar, Iztok</creator><creator>Olenšek, Jernej</creator><creator>Rojec, Žiga</creator><relation>documents/doc/U/URN_NBN_SI_doc-UWBQJB9J_001.pdf</relation><relation>documents/doc/U/URN_NBN_SI_doc-UWBQJB9J_001.txt</relation><format format_type="issue">1</format><format format_type="volume">48</format><format format_type="type">article</format><format format_type="extent">str. 29-40</format><identifier identifier_type="ISSN">0352-9045</identifier><identifier identifier_type="COBISSID_HOST">12065620</identifier><identifier identifier_type="URN">URN:NBN:SI:doc-UWBQJB9J</identifier><language>eng</language><publisher>Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale</publisher><source>Informacije MIDEM</source><rights>InC</rights><subject language_type_id="eng">analog circuits</subject><subject language_type_id="slv">analogna vezja</subject><subject language_type_id="eng">automated synthesis</subject><subject language_type_id="slv">avtomatska sinteza</subject><subject language_type_id="eng">computer-aided design</subject><subject language_type_id="slv">evolucijski algoritmi</subject><subject language_type_id="eng">evolutionary algorithms</subject><subject language_type_id="slv">računalniško podprto načrtovanje</subject><title>Analog circuit topology representation for automated synthesis and optimization</title><title>Zapis topologije analognega električnega vezja za namen avtomatske sinteze in optimizacije</title></Record>