A methodology for optimum delay, skew, and power performances in an FPGA clock network

URN:NBN:SI:DOC-U4EM5DT82006Sulaiman, Mohd Shahimandocuments/doc/U/URN_NBN_SI_doc-U4EM5DT8_001.pdfdocuments/doc/U/URN_NBN_SI_doc-U4EM5DT8_001.txt236articlestr. 85-900352-90456534996URN:NBN:SI:doc-U4EM5DT8engStrokovno društvo za mikroelektroniko, elektronske sestavne dele in materialeInformacije MIDEMInCCMOSFPGAintegrirana vezjanačrtovanjeA methodology for optimum delay, skew, and power performances in an FPGA clock networkMetodologija za doseganje optimalne zakasnitve, porazdelitve signala in porabe moči urinega omrežja vezij FPGA