FPGA implementation of a space vector pulse width modulation technique for a two-level inverter

URN:NBN:SI:DOC-P608PU922018Aoughellanet, SaidBelkheiri, AhmedBelkheiri, Mohammeddocuments/doc/P/URN_NBN_SI_doc-P608PU92_001.pdfdocuments/doc/P/URN_NBN_SI_doc-P608PU92_001.txt385articlestr. 77-830013-585213059075URN:NBN:SI:doc-P608PU92engStrokovna zadruga koncesijoniranih elektrotehnikovElektrotehniški vestnikInCFPGAkrmiljenjelogični elementimočnostna elektronikatrifazni inverterFPGA implementation of a space vector pulse width modulation technique for a two-level inverter