<Record><identifier xmlns="http://purl.org/dc/elements/1.1/">URN:NBN:SI:DOC-NR1FT6CA</identifier><date>2022</date><creator>Bulić, Patricio</creator><creator>Lotrič, Uroš</creator><creator>Pilipović, Ratko</creator><relation>documents/doc/N/URN_NBN_SI_doc-NR1FT6CA_001.pdf</relation><relation>documents/doc/N/URN_NBN_SI_doc-NR1FT6CA_001.txt</relation><format format_type="type">article</format><format format_type="extent">Str. 24-27</format><identifier identifier_type="COBISSID_HOST">122803203</identifier><identifier identifier_type="ISSN">2591-0442</identifier><identifier identifier_type="URN">URN:NBN:SI:doc-NR1FT6CA</identifier><language>eng</language><publisher publisher_location="Ljubljana">Fakulteta za elektrotehniko</publisher><publisher publisher_location="Ljubljana">Slovenska sekcija IEEE</publisher><source>Zbornik mednarodne Elektrotehniške in računalniške konference</source><rights>InC</rights><subject language_type_id="slv">FPGA</subject><subject language_type_id="slv">HDL</subject><subject language_type_id="slv">HLS</subject><subject language_type_id="slv">VLSI</subject><title>On the employment of approximate multipliers in high-level synthesis toolkits</title></Record>