Low leakage charge recycling power gating structure for CMOS VLSI circuits

URN:NBN:SI:DOC-F8GCH5092015Govindaraj, T.Kavitha, M.documents/doc/F/URN_NBN_SI_doc-F8GCH509_001.pdfdocuments/doc/F/URN_NBN_SI_doc-F8GCH509_001.txt145articlestr. 66-720352-9045280571136URN:NBN:SI:doc-F8GCH509engStrokovno društvo za mikroelektroniko, elektronske sestavne dele in materialeInformacije MIDEMInCbaterijeCMOSintegrirana vezjamikroelektronikaLow leakage charge recycling power gating structure for CMOS VLSI circuitsVezja CMOS VLSI z nizkim uhajalnim tokom vrat