<Record><identifier xmlns="http://purl.org/dc/elements/1.1/">URN:NBN:SI:DOC-A0NOLU8C</identifier><date>2005</date><creator>Kopač, Franci</creator><relation>documents/visokosolska_dela/visokosolska_dela/pdf/urn_nbn_si_doc-a0nolu8c.pdf</relation><relation>documents/visokosolska_dela/visokosolska_dela/txt/urn_nbn_si_doc-a0nolu8c.txt</relation><format format_type="main">71 strani</format><format format_type="type">magistrska dela</format><identifier identifier_type="COBISSID">238113024</identifier><identifier identifier_type="URN">URN:NBN:SI:doc-A0NOLU8C</identifier><language>slv</language><publisher>dLib distributer</publisher><publisher>F. Kopač</publisher><source>visokošolska dela</source><rights>InC</rights><subject language_type_id="slv">BT.656</subject><subject language_type_id="slv">FPGA</subject><subject language_type_id="slv">Magistrske naloge</subject><subject language_type_id="slv">obdelava video signala</subject><subject language_type_id="slv">rekonfigurabilni sistemi</subject><subject language_type_id="slv">VHDL</subject><subject language_type_id="slv">Video signali</subject><title>magistrsko delo</title><title>Razvojni sistem za obdelavo video signala s programirljivimi vezji</title></Record>