<Record><identifier xmlns="http://purl.org/dc/elements/1.1/">URN:NBN:SI:DOC-8CH46LV0</identifier><date>2018</date><creator>Skuber, Tadej</creator><creator>Trost, Andrej</creator><creator>Žemva, Andrej</creator><relation>documents/doc/8/URN_NBN_SI_doc-8CH46LV0_001.pdf</relation><relation>documents/doc/8/URN_NBN_SI_doc-8CH46LV0_001.txt</relation><format format_type="type">article</format><format format_type="extent">Str. 17-20</format><identifier identifier_type="COBISSID_HOST">12178260</identifier><identifier identifier_type="ISSN">2591-0442</identifier><identifier identifier_type="URN">URN:NBN:SI:doc-8CH46LV0</identifier><language>eng</language><publisher>Društvo Slovenska sekcija IEEE</publisher><source>Zbornik mednarodne Elektrotehniške in računalniške konference</source><rights>InC</rights><subject language_type_id="slv">FPGA</subject><subject language_type_id="slv">HLS</subject><subject language_type_id="slv">obdelava video signalov</subject><subject language_type_id="eng">video signal processing</subject><title>High-level synthesis and optimization of video signal processing IP</title></Record>