<Record><identifier xmlns="http://purl.org/dc/elements/1.1/">URN:NBN:SI:DOC-6NVC8Q5S</identifier><date>2000</date><creator>Brezočnik, Zmago</creator><creator>Časar, Aleš</creator><creator>Kapus, Tatjana</creator><relation>documents/doc/6/URN_NBN_SI_doc-6NVC8Q5S_001.pdf</relation><relation>documents/doc/6/URN_NBN_SI_doc-6NVC8Q5S_001.txt</relation><format format_type="issue">3</format><format format_type="volume">30</format><format format_type="type">article</format><format format_type="extent">str. 153-160</format><identifier identifier_type="ISSN">0352-9045</identifier><identifier identifier_type="COBISSID">5935638</identifier><identifier identifier_type="URN">URN:NBN:SI:doc-6NVC8Q5S</identifier><language>eng</language><publisher>Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale</publisher><source>Informacije MIDEM</source><rights>InC</rights><subject language_type_id="slv">algoritmi</subject><subject language_type_id="slv">digitalna vezja</subject><subject language_type_id="slv">odločitveni grafi</subject><subject language_type_id="slv">preverjanje</subject><subject language_type_id="slv">verifikacija</subject><title>Formal verification of digital circuits using symbolic model checking</title><title>Formalna verifikacija digitalnih vezij s simboličnim preverjanjem modelov</title></Record>