<Record><identifier xmlns="http://purl.org/dc/elements/1.1/">URN:NBN:SI:DOC-6I6HX1JH</identifier><date>2019</date><creator>Murovič, Tadej</creator><creator>Trost, Andrej</creator><relation>documents/doc/6/URN_NBN_SI_doc-6I6HX1JH_001.pdf</relation><relation>documents/doc/6/URN_NBN_SI_doc-6I6HX1JH_001.txt</relation><format format_type="issue">1/2</format><format format_type="volume">86</format><format format_type="type">article</format><format format_type="extent">str. 47-53</format><identifier identifier_type="ISSN">0013-5852</identifier><identifier identifier_type="COBISSID_HOST">12547668</identifier><identifier identifier_type="URN">URN:NBN:SI:doc-6I6HX1JH</identifier><language>eng</language><publisher>Strokovna zadruga koncesijoniranih elektrotehnikov</publisher><source>Elektrotehniški vestnik</source><rights>InC</rights><subject language_type_id="slv">binarne nevronske mreže</subject><subject language_type_id="eng">binary neural networks</subject><subject language_type_id="slv">BNN</subject><subject language_type_id="eng">edge processing</subject><subject language_type_id="slv">FPGA</subject><subject language_type_id="eng">HDL design</subject><subject language_type_id="eng">machine learning</subject><subject language_type_id="slv">masivno paralelne nevronske mreže</subject><subject language_type_id="eng">massively parallel neural networks</subject><subject language_type_id="slv">obdelava na robu</subject><subject language_type_id="slv">strojno učenje</subject><subject language_type_id="slv">strojno-opisno načrtovanje</subject><title>Massively parallel combinational binary neural networks for edge processing</title></Record>