Reducing the length of the test sequence for analog test signal generation

URN:NBN:SI:DOC-4HENBCE72015Lijia, XuLong, TingShiqi, Jiangdocuments/doc/4/URN_NBN_SI_doc-4HENBCE7_001.pdfdocuments/doc/4/URN_NBN_SI_doc-4HENBCE7_001.txt1/282articlestr. 8-140013-5852286084096URN:NBN:SI:doc-4HENBCE7engElektrotehniška zveza SlovenijeElektrotehniški vestnikInCanalogna vezjapodporni vektorjitestiranje vezijReducing the length of the test sequence for analog test signal generation