<Record><identifier xmlns="http://purl.org/dc/elements/1.1/">URN:NBN:SI:DOC-0L02J85I</identifier><date>1994</date><creator>Runovc, Franc</creator><relation>documents/znanstveni_clanki/kovine_zlitine_tehnologije/html/URN_NBN_SI_doc-0L02J85I.html</relation><relation>documents/znanstveni_clanki/kovine_zlitine_tehnologije/pdf/URN_NBN_SI_doc-0L02J85I.pdf</relation><relation>documents/znanstveni_clanki/kovine_zlitine_tehnologije/txt/URN_NBN_SI_doc-0L02J85I.txt</relation><format format_type="volume">28</format><format format_type="issue">3</format><format format_type="main">4 strani</format><format format_type="type">article</format><format format_type="extent">str. 512-515</format><identifier identifier_type="ISSN">1318-0010</identifier><identifier identifier_type="COBISSID">70182656</identifier><identifier identifier_type="URN">URN:NBN:SI:doc-0L02J85I</identifier><language>eng</language><publisher>Inštitut za kovinske materiale in tehnologije</publisher><publisher>Železarna Jesenice</publisher><publisher>Železarna Ravne</publisher><publisher>Železarna Štore</publisher><source>Kovine zlitine tehnologije</source><rights>InC</rights><subject language_type_id="eng">Metallurgical and Materials Engineering</subject><subject language_type_id="slv">metalurgija</subject><subject language_type_id="slv">mikroelektronika</subject><subject language_type_id="slv">modeliranje procesov</subject><subject language_type_id="slv">simulacija</subject><title>Computer-aided modeling and simulation of fabrication steps in semiconductor processes</title></Record>