Original scientific paper Informacije Journal of Microelectronics, Electronic Components and Materials Vol. 45, No. 4 (2015), 266 - 276 Low-pass filter for UWB system with the circuit for compensation of process induced on-chip capacitor variation Branislava Milinkovic12, Milenko Milicevic13, Dorde Simic1, Goran Stojanovic2, Radivoje Duric3 1TES Electronic Solutions GmbH, Stuttgart, Germany 2University of Novi Sad, Faculty of Technical Sciences, Department for Power, Electronic and Communication Engineering, Novi Sad, Serbia 3University of Belgrade, School of Electrical Engineering, Department of Electronics, Belgrade, Serbia Abstract: This paper describes the design and optimization of a Chebyshev 5th order low pass filter with included circuit for automatic process calibration and compensation. The filter is realized using lumped elements in 130 nm radio frequency (RF) CMOS process and is dedicated to cover lower sub-band (3.4 GHz - 4.8 GHz) of ultra-wideband (UWB) system. The proposed full on-chip calibration concept estimates MIM-Capacitor (Metal-Insulator-Metal) capacitance process-induced variation against more stable on-chip MOS capacitor reference. In order to estimate the capacitance value, a low frequency oscillator is designed, which uses both types of capacitors for generating the oscillations, one after another. The MIM capacitor value is determined in digital domain based on the ratio of two oscillation frequencies and its exact needed value is obtained using a compensation capacitor bank. Detailed mathematical optimization of the calibration method is presented. All RF, analog and digital circuits have been integrated on a test chip and fabricated in 130 nm RF CMOS process. The produced ICs have been on-wafer measured and compared to simulation results. According to obtained results, the proposed calibration concept lowers process-induced filter transfer characteristic variation from approximately 5 dB to 0.6 dB at the critical frequency. The calibration needs to be applied just once at the beginning of circuit operation. The total area of implemented calibration circuit is less than 0.1 mm2. The same method and the compensation circuit can be employed for the calibration of all on-chip circuits whose performance is affected by MIM capacitance process variation. Keywords: process variation; compensation; MIM capacitor; low-pass filter; UWB Izvleček: Članek opisuje optimizacijo Chebyshevega nizkopasovnega filtra petega reda, ki vključuje vezje za avtomatsko kalibracijo in kompenzacijo. Filter je realiziran z uporabo 130 nm CMOS procesa in je namenjen za podpas (3.4 GHz - 4.8 GHz) UWB sistema. Predlagan polno integriran koncept kalibracije ocenjuje spremembe kapacitivnosti MIM kondenzatorja v nasprotju s stabilnim referenčnim MOS kondenzatorjem. Za oceno kapacitivnosti je uporabljen nizkofrekvenčni oscilator. Opravljena je bila natančna matematična optimizacija kalibracijske metode. RF, analogna in digitalna vezja so integrirana na testnem čipu v 1300 nm RF CMOS tehnologiji. Čipi so bili merjeni na rezini. Glede na rezultate predlagana kalibracija zmanjšuje procesno prožen prenos karakteristike sprememb za 0.6 do 5 dB pri kritični frekvenci. Ista metodologija se lahko uporabi za vsa vezja, ki so obremenjena s spremembami MIM kapacitivnosti. Ključne besede: variacije procesa; kompenzacija; MIM kondenzator; nizkopasovni filter; UWB * Corresponding Author's e-mail: branislava.milinkovic@tes-dst.com Nizko pasovni filter za UWB system z vezjem za kompenzacijo procesno vzpodbujenega spreminjanja integriranega kondenzatorja 266 © MIDEM Society B. Milinkovič et al; Informacije Midem, Vol. 45, No. 4 (2015), 266 - 276 1 Introduction Constant IC manufacturing technology scaling allows the device integration in ever smaller area. As an adverse effect, the size reduction causes degradation of the intrinsic precision of the manufactured components [1]. In order to satisfy extreme design constraints on the analog/RF circuits with given component tolerances, some method of digital calibration must be applied [1]. For the mass product solutions, it is very important that the calibration circuits take as small area on the silicon as possible. Since with the technology scaling the size of digital devices is reduced, it is possible to implement complex digital calibration circuits occupying very small on-chip area. Moreover, for consumer products, external references are not applicable, since the external component size is almost comparable to the chip size [2]. In this paper, the design of a passive, LC low-pass filter is described. The DC inductance value for on-chip inductors is mostly insensitive to process variations [2], but on-chip capacitors notably change their values due to the finite manufacturing accuracy. The Table 1 presents capacitor value variations for three types of capacitors, available in the used technology. The MIM-capacitors are the most suitable for RF applications, since they are the most linear and have the highest Q-factor of all available on-chip capacitor types, so this type of the capacitor is chosen to be used in the design. In case of MIM-capacitors, the shift in capacitance occurs mostly due to the oxide thickness variation, rather than to the temperature-induced variation. Unfortunately, the shift in the capacitance value will degrade the final performance of circuits beyond allowed limitations, so an adequate calibration and compensation method must be applied. Presented calibration concept compensates MIM-capacitor variation and can be applied in any circuit which characteristics are deteriorated due to MIM cap process-induced variations. Table 1: Tolerances of the available capacitors in the used technology Capacitor type Process and temperature (-40:125°C) tolerance MIM ±15% MOM ±15% MOS ±4% The Paper [3] has demonstrated a way to estimate and compensate capacitor values using an external reference. In [2], the calibration concept with the internal on-chip reference has been proposed, which makes calibration suitable for the small form factor solutions. The price is paid by limited accuracy of the reference, but at the other hand, the approach is insensitive to parasitic and systematic errors introduced by calibration circuit. This paper combines these two calibration approaches with additional optimizations, offering unique calibration solution, applicable for mass production. The proposed solution is applied on the low-pass filter calibration. The concept is verified through measurements. The second section describes low-pass filter implementation. In the third section, the calibration concept is reviewed in detail. The experimental results are presented in the fourth section that is followed by conclusion in the fifth section. 2 Low-pass filter 2.1 Description Ultra Wideband (UWB) systems are very suitable for low cost, low power or high data rate, short range communication. By using a large bandwidth, they are immune to narrow band interference and multipath fading. These systems are preferable in the applications that demand high security level, since transmitted signal is noise-like, and hence hard to intercept. Filters are one of the key components in UWB systems. In transmitter, they control out-of-band radiation and suppress higher harmonics. In receiver, filters enable the suppression of unwanted signals and interferers. Proposed filter is designed for the lower band of UWB system according to 802.15.4a standard [4]. The filter can be applied in both, transmitter and receiver. The specifications of the proposed 5th order Chebyshev low-pass filter are listed in Table 2. The specifications are chosen based on transmitter transmission power level and linearity and estimated levels of unwanted signals and interferers in image band on the receiver side. The Chebyshev filter has the best compromise between pass-band ripple, which degrades Error Vector Modulation (EVM) and selectivity, which limits out-of-band emission and reception. Table 2: Filter specifications Item Value Description Zin 50Q Zout 50Q S11 <-10dB 267 B. Milinkovič et al; Informacije Midem, Vol. 45, No. 4 (2015), 266 - 276 S22 <-10dB IL <1 dB Goal Order 5 Chebyshev Ripple ±0.5dB Fc 4.8GHz 3dB point -15dB @6.4GHz Selectivity -30dB @8.53GHz -40dB @10.67GHz 3 Calibration The first filter implementation has been synthesized using ideal component values from [5]. Due to the low Q-factor of the on-chip passive components, optimization of component values under nominal conditions has been performed. The filter schematic and obtained S-parameter simulation results through all three process variation corners are presented in Figure 1 and Figure 2, respectively. The results are obtained on the schematic level and extracted parasitic effects after the circuit layout will introduce additional losses. RF, IN L L2 RF, OUT C^ PADn Figure 1: LPF- schematic Figure 2: Filter transfer characteristic in slow(blue), typical(green) and fast(red) corner In this section, the calibration concept using internal reference is described in details. The most suitable internal reference for on-chip capacitor calibration can be obtained using MOS capacitors. As it can be seen from the Table 1, the variation with a process and temperature is acceptable ±4%. But MOS capacitors are very nonlinear and can't be used in the circuits without appropriate polarization. For the purpose of the calibration, the reference MOS capacitor is polarized in the region where its nonlinear behavior is negligible. 3.1 Concept Each of three capacitors from Figure 1 is replaced with a bank of one base and several tuning capacitors, used for the compensation. Depending on process variation effects on the capacitance value, the corresponding compensation capacitors are included or excluded from the circuit operation using RF switches, Figure 3. Thus, the effective capacitance is adjusted to the nominal value under all process variations. Control signals for the switches are generated from the circuits that estimate capacitor process variation. Figure 3: Capacitor bank Figure 4 illustrates the concept of MIM-capacitor value estimation. The oscillator core generates oscillations on charge-pump principle using first the MIM and than the MOS capacitance. The MIM-capacitor value is calculated in digital domain by determining ratio of the oscillation frequencies which corresponds to inverse ratio of the MIM and MOS capacitor values. As it can be seen from Table 2 and Figure 2, the specifications are not fulfilled under all process variations. One way to overcome this problem is to increase the order of the filter. That leads to overdesign at the price of larger chip area. Another solution is to apply a calibration and this solution is the preferred one. Figure 4: Calibration concept The real advantage of the proposed approach is cancellation of PVT (Process, Voltage and Temperature) 268 B. Milinkovič et al; Informacije Midem, Vol. 45, No. 4 (2015), 266 - 276 variations for all components used for frequency ratio determination since the same oscillator core generates oscillations in both cases (with MIM and MOS capacitors). Values of the capacitors in the cap bank and the process values at which they are included in the circuit operation are chosen according to the calculation derived in [3]. New value of the nominal capacitor is: 1 + £ C = C nom nom k„ (1) 3.2.1 "On" state When the switch is "on", the gate voltage corresponds to VDD, while VD= VS=0. The impedance seen between drain and source terminals of the transistor is dominated by rds resistance, (4). ~ W-M-CoxL(Vdd - Vh) (4) For the minimal transistor length and the fixed polarization we can assume that switch "on" resistance is approximately Ron=Kr/W, where KR=M-C0x-(VDD-V,h)/L is constant. This approximation is good enough in the observed case. Where C is the capacitor nominal value, £ is maximal nom 1 acceptable error caused by discrete nature of compensation and k is maximal process value- k =1+3-o, max 1 max where o is normalized standard process deviation for MIM-capacitors. New, n-th compensation capacitor (2) is included in the circuit operation at the process value given by means of (3). It is assumed that C is 1. Note, that at k pronom n cess value, only C is included in the circuit operation. In order to calculate contribution of the switch "on" resistance to the filter insertion loss, we need to transform impedances (Figure 5). RP — RS - (Q1 +1), CP — Cs Q2 C Q1 +1 Q — 1 (O-Rs ■ C (5) 5 C P R p Cn = £•(1 + £) 2" 1 + 3 a (1 -£)" (2) :R s k = 1 -e 1+e+£ c, max ,=1 (3) k„ Satisfactory accuracy of up to £=2% can be reached using three compensation capacitors. Normalized values of the compensation capacitors are presented in Table 3. All capacitor values are normalized to C . nom Table 3: Normalized values of the compensation capacitors in cap bank presented in Figure 3. Capacitor name Capacitor value C'nom 0.8872 Cci 0.0368 Cc2 0.0751 Cc3 0.1534 3.2 Switch design Figure 5: A series to parallel impedance transformation For Q>10 we get: Rp ■RS • Q J CP ~ CS (6) Since we have three switches in the circuit, the total contribution of the switch "on" resistance to the node impedance can be expressed via equivalent parallel resistance, (7). Influence of the switch "on" resistance on filter performance is measured by means of Q-factor. Equivalent Q-factor of the observed node has the lowest value in the case when all three switches are "on". This case corresponds to the "fast" corner (k=k . ). Req = R ■ Q2I|R2 • Ö22 IIR • Q: (7) In that case, the equivalent Q-factor of each capacitor can be expressed by (8). Compensation capacitances are included in the circuit operation via RF switches as presented in the Figure 3. The switches are optimized so that the best compromise between insertion loss (when the switches are "on") and isolation (when the switches are "off") is obtained for the given application. Q = ■ m krnn • C, • K nom R r 2 •(— W + - W2 W3 (8) Where r corresponds to CCi/Cnom ratio for i=1,2,3 and r=C' /C . These values are listed in Table 3. u is 0 nom nom angular frequency, k is minimal process value, C min nom r0 + ri + r2 + r3 2 2 r r. ) 269 B. Milinkovič et al; Informacije Midem, Vol. 45, No. 4 (2015), 266 - 276 is nominal capacitor value, KR is switch constant expressed above and Wi is width of the i-th switch which includes the compensation capacitors CCi into the circuit operation. 3.2.2 "Off" state Figure 6 presents switch parasitic capacitors in "off" state. Cgd and Cgs are originating from overlap of the gate poly and drain/source areas and they can be approximately expressed via C ,=C =C =W-L -C' . C., and C, * r gd gs ov ov ox db sb are junction capacitances between drain/source terminal and substrate. This capacitance is usually decomposed into bottom plate capacitance, associated with the bottom of the junction, Cj and sidewall capacitance due to the perimeter of the junction, C . C and C are r 3 ' jsw j jsw capacitance per unit area and unit length, respectively, and both can be expressed as C=Cj0/(1+VR/$B)m, where VR is reverse voltage across junction. is the junction build-in potential and m is typically in the range of 0.3 and 0.4 [6]. In order to make these capacitances as low as possible, multi-finger structure is adopted and the drain is connected to the supply voltage in switch "off" state. The switch polarization, as presented in Figure 3, is done via inverter and a high value resistor. The resistor increases output inverter impedance since it appears in parallel with switch "off" impedance. -cdb + c„ c dg wgs c,,„+c„ w ■■ — ■E-C- + 2 J W W (9) Where W is transistor width, E is width of the diffusion at drain terminal, Lov is determined by the technology and represents length of an overlap area between gate poly and drain diffusion area, while C'ox is oxide capacitance per unit area. With the adopted polarization, we can approximately conclude that the drain capacitance is determined with the technology parameters and transistor width, Cdrain~KC'W. Note that in the frequency range of interest (up to 10GHz) and with a good layout we can neglect Rsub in a given technology. Also W/2>>E is assumed. Capacitor error (£p) due to the switch parasitic capacitance is largest when all switches are "off" and that occurs in slow process corner k=k . ' max r. "p i- J max 1-c, - + - ■r, KcWy k -r -C nom j "'max 2 nom + kcW2 (10) C G C. lr -r -C J max '3 ^nom gd S c ^ D B Figure 6: Switch in "off" state Rsub models the substrate resistance from the junction to the substrate ground and in the given technology it depends on size and distance of the substrate contacts, the transistor size, the number of the gate fingers, and even of nearby circuit elements [7]. With the given polarization and multi-finger structure and with neglecting Rsub the impedance seen from the drain terminal is mainly capacitive and given by means of the following formula: KCW, 3.2.3 Switch optimization Without compensation, the IL (Insertion Loss) is determined by Q-factor of the inductors. With the compensation present, the switches can significantly degrade the IL. In order to prevent it, equivalent capacitor Q-factor has to be high enough at the frequency range of interest. According to (8) equivalent capacitor Q-factor decreases with a frequency. Thus, insertion loss will be the most degraded at the highest frequency where it is important: at cutoff frequency (/=/c=4.8GHz). Based on simulation results that consider degradation of IL due to equivalent capacitor Q-factor degradation, it is found that for capacitors having Q-factor above 40 at f, the degradation will be lower than 0.5dB. From (8) we can observe that transistor width should be maximal in order to have high Q-factor. From the other side, the width should be minimal for the minimal error, (10) so, the optimal trade-off between insertion loss and capacitor error needs to be made. The calculation below gives the optimum ratio of switch width for a given Q-factor. 270 B. Milinkovič et al; Informacije Midem, Vol. 45, No. 4 (2015), 266 - 276 The goal is to minimize £p for a given Q. For the derivation we are going to use Jesen's inequality- Xj, , X3 . tj * f (Xi) +12 * f (X ) +t3 * f (X3) ^ f (tj * Xj +12 * X +t3 * X3) Where / is a convex function, x1, x2 and x3 in its domain, t1, t2 and t3 positive weights for which applies-f1+f2+f3=1. Equality applies if and only if x,= x2= x3 or / is linear. For /(x)=1/x, we can write: ( 1 + ^max ' r\ ' Cnc kcwx t'f + —•/ ' k r-C N ^ I "'max 3 umi< kcw, f ^ 1 ^max ' ri ' Cnoi kcwx k •r C J max 3 nom kc-w,, \ // t ' k r-C ^ 2 max '2 ^nam kc-w2 k ■r -C ^ 1 ""max '2 ^nom kcw2 (11) r1 r2 1 — + — + — = 1 t t t From (10), (11) and (12) we can obtain: 1 1 + ma^ nom 2 -2 2 t ■ ■ + W W2 W3 + ) (12) (13) Using (8) we can rewrite (13): £p — t ■ k 1 1+- t ■ Kr (oKR ■ Q (14) For constant Q at fc, the expression from the right side in (14) is constant. Note that the expression doesn't vary with the frequency, since it cancels out. Minimal error can be obtained in the case when the left and the right side of (14) are equal. It will be the case if and only if: k • r • C k • r • C k • r • C 1 I _max M v-'nom _ j | _max '2 v-'nom _ j + _max '3 ^nom (15) Kc W Kc W Kc W We can than rewrite (15) into condition: Wi W2 W3 (16) With specified Q-factor at fc and (16) and (8) we can obtain the widths of the switches for all three capacitors. Note that with choosing Q-factor value at f, we determine the capacitor error, too. So if the error for chosen Q-factor is not satisfactory, one can decrease it at the cost of higher IL. For QC=40 we obtain maximal error of £p=2% which is acceptable. For the capacitor C2 the switches are sized for these values. For C1 and C3 we are restricted with the minimal size of switches in the used technology. In this case, QC=35 for £p=2%. Note that the worst IL degradation and maximum error arise in the case of different corners. For selected switch widths, the IL degradation at fc is below 0.6 dB. 3.3 Compensated filter The compensated filter is simulated on the extracted level through "fast", "typical" and "slow" corners and obtained S-parameter results are presented in Figure 7. a) b) Figure 7: S-parameters of the compensated filter in slow (blue), typical (green) and fast (red) corner- a) S21 b) S11 If we compare the results with the ones obtained in the non compensated case, Figure 2, we can conclude that the filter transfer characteristic variation of 5 dB at the critical frequency 6.4 GHz is lowered to only 0.6 dB and the specifications are met under all process variations. 2 1 ro + ri + r2 + r r r 2 3 271 B. Milinkovič et al; Informacije Midem, Vol. 45, No. 4 (2015), 266 - 276 3.4 Capacitor value estimation In this section, circuit that generates control bits for designed switches is described in detail. 3.4.1 Oscillator The oscillator concept is presented in Figure 8 and is in detail described in [3]. Single-ended oscillator circuit generates oscillations on the charge-pump principle. Although the topology is more-less the same like in [3], the design optimization differs a lot. As noted, the design procedure in this work gains the benefits from using the internal reference, since the accuracy of the capacitor value estimation is insensitive to the temperature, power supply and process variations and on the parasitic influences of the line connections. (p. UP / DOWN-t\ MM / MOS -¿-.v.. S Q- R Qn -j current mirroring, offset of operational amplifiers, V, and V2 variations, parasitic capacitance and resistance of the connection lines. Since non-idealities are almost the same in both cases of oscillations due to the same oscillator core, follows that aMIM=aMOS. Voltages V, and V2 have to be high enough that nonlinear behavior of MOS capacitor does not affect the calibration accuracy. From the other side, these voltages have to be low enough, so the "P side" of current mirrors has high output impedance. Proposed calculation shows the influence of V, and V2 voltages on the estimation error caused by MOS cap non-linearity. According to ACM (Advance Compact MOSFET) model, gate capacitance, for VDS=0, can be expressed by means of (21) [9]. Cgate - Cgs + Cgd + Cgb C = n-1 C +1C ^+IF -1 Cgate m C0x + m C0x .J\+^IF Vg Vto - VS,D = 0 [l + IF - 2 + ln(Vl + IF -1)] n n (20) (21) (22) Figure 8: Oscillator- concept n = n(VG), Cox = W ■ L ■ C0,« 26mV(t' = 27° C) (23) Digital logic coordinates the oscillator. Digital signal osc_enb sets the oscillator in the initial state and enables its running. The MIM / MOS signal determineds weather the oscillation are generated with MIM or MOS capacitance. The signal SEL in the oscillator has the rectangular shape. Its frequency corresponds to the oscillation frequency and is measured in the digital domain. The oscillation period is proportional to the value of the measured capacitance, (17). . 2 ' CMIM/MOS ' _ 2 ' CMIM/MOS ' (V2 Vl) Ib IB (17) In digital domain, the oscillations using each of capacitors are counted within predefined measure time, T . ' measure COUNTM T _ measure MIM / MOS L MIM / MOS COUNTmos _ Tmu_¡dml ■ (1 + aMU) _ CMM 1 + uM COUNTmm TmoS ideal ' (1 + aMOS) CMOS 1 + aMOS Cm (18) (19) In (21), C0x is gate oxide capacitance, n is so-called slope factor and is a function of gate voltage, IF is inversion factor which can be calculated using (22). In (22), VT0 is threshold voltage, Qt is thermal voltage and VG, VS and VD are transistor gate, source and drain voltages. For the chosen value of MOS capacitor and high enough VG, the Cox is determined. Using the procedure described in [9] we can extract parameters VT0 and n(VG). For VD=VS=0 from (22), we can express iF and substitute it in (21). Now we are obtaining the gate capacitance as a function of gate voltage, Cgate= Cgate(V, "gatev G' With this expression, we can calculate deviation of TMIM/ 1) Tmos ratio in nominal conditions from ideal (T, as a function of V. mim/tmos Using (24) we can express voltage across MOS cap (gate voltage) as a function of time. We are assuming that capacitor charges from voltage V1 with constant bias current, IB. Ib = Cgate (vc ) ^, vc (0) = Vi (24) In (19) aMIM and aMOS model the oscillation period deviations from the nominal values caused by non-idealities; namely, inaccurate on-chip current source, non-ideal From (25) we can find time needed to charge observed cap from V, to V2, namely TMOS(V,,V2). vc(t) = V2 ^ Tmos(V1,V2) (25) UP C 272 B. Milinkovič et al; Informacije Midem, Vol. 45, No. 4 (2015), 266 - 276 In order to have ideal ratio TMIM/TMOS=1, we are choosing: C = MIM Cgate (V1 ) + Cgate (V2 ) 2 (26) Combining (17) and (26) we can express TMIM=TMIM(V1 ,V2). With that and (25), we can express error (TMIM/TMOS-1)-100% in respect to V1 i V2. The absolute error is depicted in Figure 9 as the function of V1 for V2=V1+0.1 V, V2=V1+0.2 V and V2=V1+0.3 V. As can be seen from the Figure 9 the error caused by MOS cap non linearity is negligible for V1>0.6 V for V2-V1<0.2 V. In order to have constant current capacitor (de)charg-ing, which is assumed during all calculations, current mirrors should have high output resistance. Furthermore, Tosc /2 should be larger than clock for digital logic under all PVT variations in order to synchronize and sense the oscillations in digital network. The nominal values of Cm^mos=30 pF, Ib=100 mA, V=0.6 V and V=0.8 V allow these conditions to be realizable with the acceptable area of the oscillator. The oscillator with the bias sources is fully implemented. Two current sources are designed, one for the comparators polarization, another for the purpose of charging and discharging the capacitors through current mirror. The sources are self-biased and operate using the positive feedback. For each source, Schmitt trigger is designed in order to provide certain start under all PVT variations. Oscillation frequency for both, MOS and MIM capacitors, simulated through 81 different PVT combinations, Figure 9: Error in MIM cap value estimation due to the finite MOS cap linearity versus V1, for V2=V1+0.1 V (green), V2=V1+0.2 V (purple) and V2=V1+0.3 V (blue) changes a lot, due to the full on-chip implementation. The obtained frequencies are in the range from 3.37MHz to 15.41MHz. Figure 10 presents time waveforms of the slowest, nominal and fastest oscillations that occur with MIM-capacitors. Figure 10: Oscillation waveforms in the slowest, nominal and fastest case Table 4: CMIM/CMOS ratio for different PVT values on the extracted level Item Vdd=1.14V Vdd=1.2V Vdd=1.26V T [°C] -40 27 90 -40 27 90 -40 27 90 CORE corner MIM cap in slow corner (ideal=1.15) slow 1.17 1.17 1.18 1.16 1.17 1.17 1.16 1.16 1.17 typical 1.13 1.14 1.14 1.13 1.14 1.14 1.12 1.13 1.14 fast 1.10 1.11 1.11 1.09 1.10 1.11 1.09 1.10 1.10 MIM ca p in typical corner (ideal= =1) slow 1.03 1.04 1.04 1.02 1.03 1.04 1.00 1.03 1.04 typical 1.00 1.01 1.01 0.99 1.00 1.01 0.99 1.00 1.01 fast 0.97 0.98 0.99 0.97 0.98 0.98 0.96 0.97 0.98 MIM ca p in fast corner (ideal=0.85) slow 0.89 0.90 0.91 0.89 0.90 0.90 0.88 0.89 0.90 typical 0.87 0.88 0.89 0.86 0.87 0.88 0.86 0.87 0.88 fast 0.84 0.85 0.86 0.84 0.85 0.86 0.83 0.84 0.86 273 B. Milinkovič et al; Informacije Midem, Vol. 45, No. 4 (2015), 266 - 276 Table 4 summarizes estimated values of MIM-capacitor through different corners, supply voltages and temperatures. Nine different combinations of temperature and supply voltage are considered- when all except CMIM are in one corner, core corner, and CMIM is in another, non-correlated corner. Estimation error is always smaller or equal to 6% (in 96.3% cases error is <5%). 3.4.2 Digital logic Since the calibration process is being performed only once after power supply is applied, the speed and the low power consumption of the digital logic are not so important requirements. The area should be restricted, which is not a problem, due to low complexity and large level of integration of digital logic. Block diagram of the digital logic is presented in Figure 11. The logic is synchronized with an external clock of 32 MHz. Digital logic coordinates the oscillator running, determines the ratio of the oscillation frequencies and according to the ratio value, sets the control bits for the filter capacitor bank. Figure 12: Control block- FSM (Finite State Machine) Figure 11: Digital network for generating filter control bits Figure 13: Counter of the oscillations and time counter The listed digital blocks are described via Verilog code and are implemented in the silicon. Whole logic is implemented using 450 digital gates and takes the area of 114^m x 110^m. After synthesis and place-and-route, timing and functional checks were performed. External signal reset_n sets the initial state of the logic. All external signals are synchronized with the clock in order not to violate setup and hold times of used flipflops, to avoid flip-flops to reach metastable state. Chosen oscillations that should be measured are presented at the input port osc of the digital network. Signal cal is external and it starts the calibration process again. Output signals flt_ctrl_b[2:0] control the switches in the filter adjustable capacitor bank. Digital part of the design consists of the four main blocks described by Verilog code: (1) CONTROL BLOCK, which is the core of the digital logic realized as the finite state machine, Figure 12; (2) OSC_COUNTER, that counts oscillation in the predefined time period T , equation (18); measure' " \ /1 (3) DIVIDER, which divides COUNTmos and COUNTMIM equation (19); (4) FLT_CTRL block, that generates filter control bits according to the division result. 4 Experimental results- Measurements The filter with its compensation capacitors, oscillator and digital network are designed and fully integrated. The layout of the whole design is presented in Figure 14. As it can be observed from the figure, the compensation capacitors are realized with multiple capacitors connected in series. This has been done due to the high minimal value of MIM capacitors in used technology. The effective area of the design is significantly smaller than the size of the entire chip. The reason for that and for layout aspect ratio is adjusting the design to available on-chip measurement equipment and integration of the test chip on the multi-project-wafer available area. It should be emphasized that, in order to have possibility of external calibration, an additional circuit is added. The circuit is composed of the three multiplexers controlled by signal reset_n which determines whether the calibration is internal or external. Also, shift register is implemented for writing three control bits via two external signals. 274 B. Milinkovič et al; Informacije Midem, Vol. 45, No. 4 (2015), 266 - 276 OSCILLATOR Figure 14: Integrated design- layout view The Figure 15 shows the measurement results of the circuit using internal calibration procedure. Measurements are performed under nominal conditions - at the room temperature and nominal supply voltage. As it can be seen from the figure, the compensated filter transfer characteristic matches well with the simulated one - at the cutoff frequency the difference is 0.6 dB. Also, uncompensated filter characteristic is shown. In this case, control bits have random values. The difference between simulated and non-compensated case at cut-off frequency is unacceptable 2dB. Figure 16 and Figure 17 present the photo of the IC die and the measurement set-up using the on-wafer probes. -0-Simulated -(-Compensated -o- Non-compensated f 1^0(4 ^GjHzj r 3, 525dB) ÏV 1 (a : i Old 1 4 8 C H _c .E ÎÉ •4 0 X 1, ■ — + - it S ■■■ S H 0 2.5 5.0 7.5 freq (GHz) a) Simulated + Compensated -»-Non-compensated O-i f £ 0- C se h z _ 8 3 3 B 'd \ r "i o- 3= f ?f 4 ? 1 HP 5 : r ............ 0- v \ K 4 H Hz -1 Z / Hb ) i i \ r st 1 > t n i 1 t * \ / J t 0 2.5 5.0 7.5 freq (GHz) Figure 15: Filter a) S21 and b) S11 parameters in compensated (green), simulated (red) and noncompensated case (purple) Figure 16: Die photo 5 Conclusion This paper proposes one way of fully integrated on-chip calibration of MIM-capacitor process induced variation, utilizing more stable MOS capacitor as reference. The test circuit is designed and verified using standard 130 nm CMOS process. The concept is applied to low-pass filter design and is verified through simulations and measurements. After the calibration is applied, MIM capacitance variation is lowered from 15% to 8%.. Moreover, optimization of RF switches is proposed. 275 B. Milinkovič et al; Informacije Midem, Vol. 45, No. 4 (2015), 266 - 276 Figure 17: Die with probes With adopted optimization, the switches increase filter insertion loss no more than 0.6 dB in "on" state, and introduce additional capacitor error below 2% when they are all "off". The same method can be used for compensating the process variation in any other circuit type and in any other CMOS technology process. 6 Acknowledgments The authors would like to thank Faculty of Technical Science, Department for Power, Electronic and Telecommunication Engineering in Novi Sad, Serbia, for providing measurement facilities. The design is part of the SENSEIVER project- www.senseiver.com founded by European Union's Seventh Framework Programme. 4. IEEE Std 802.15.4a-2007 (2007) Amendment to 802.15.4- 2006: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs) 5. R. Rhea (1994) HF Filter Design and Computer Simulation, Noble Publishing Corporation, Georgia- USA 6. B. Razavi (2001) Design of Analog CMOS Integ rated Circuits, McGraw-Hill, New York 7. B. Min (2008) SiGe/CMOS Millimeter-Wave Integrated Circuits and Wafer-Scale Packaging for Phased Array Systems, Ph.D. thesis, The University of Michigan 8. A. Niknejad (2007) Electromagnetics for HighSpeed Analog and Digital Communication Circuit, Cambridge University Press, New York 9. M. Schneider, C. Galup-Montoro (2010) CMOS Analog Design Using All-Region MOSFET Modeling, Cambridge University Press, New York 10. J. Bhasker, R. Chadha (2009) Static Timing Analysis for Nanometer Designs- A Practical Approach, Springer, New York 11. D. Harris, S. Harris (2013) Digital Design and Computer Architecture, Elsevier, Waltham, Massachusetts Arrived: 04. 12. 2015 Accepted: 31 12. 2015 7 References 1. M. Pastre, M. Kayal (2006) Methodology for the Digital Calibration of Analog Circuits and Systems, Springer, Netherlands 2. C.-W. Lee (2012) On-chip Benchmarking and Calibration without External References, Ph.D. thesis, EECS Department, University of California, Berkeley 3. I. Milosavljevic, D. Grujic, D. Simic, J. Popovic-Bozovic (2014) Estimation and compensation of process-induced variations in capacitors for improved reliability in integrated circuits, Analog Integrated Circuits and Signal Processing, vol. 81, no 1, pp. 253-264 276