PENALTY FUNCTION APPROACH TO ROBUST ANALOG IC DESIGN Arpad Bürmen, Drago Strle, Franc Bratkovič, Janez Puhan, Iztok Fajfar, Tadej Turna University of Ljubljana, Faculty of Electrical Engineering, Ljubljana, Slovenia Keywords; circuit sizing, analog IC, optimization, penalty function, CAD. Abstract: Automating the robust IC design process is becoming more and more important due to its complexity and decreasing time to market. In order for the circuit to be robust it must satisfy all design requirements across a range of operating conditions and manufacturing process variations. Part of the design process, which is performed by experienced analog IC designers, is automated. A transformation of the robust design problem into a constrained optimization problem by means of penalty functions is presented. The method is illustrated on a robust differential amplifier design problem. The results show that it is capable of sizing a circuit and reaching comparable or to some extent even superior performance to a humanly designed circuit. The method has great potential in parallel processing although it is efficient enough to be executed on a single computer. Robustno načrtovanje analognih integriranih vezij z uporabo kazenskih funkcij Ključne besede: dimenzioniranje vezij, analogna integrirana vezja, optimizacija, kazenske funkcije, računalniško podprto načrtovanje. Izvleček: Avtomatizacija postopka robustnega načrtovanja IV postaja vse bolj pomembna zaradi zahtevnosti samega postopka in čedalje krajšega časa od začetka načrtovanja do pojave vezja na tržišču. Da je vezje robustno, mora zadostiti vsem načrtovalskim zahtevam za dano območje pogojev delovanja in možnih variacij parametrov postopka izdelave. Predstavljen je avtomatiziran postopek načrtovanja, po zgledu postopka, ki ga izvajajo načrtovalci IV. Podana je preslikava iz problema robustnega načrtovanja v omejen optimizacijski problem. Pri tem se poslužujemo kazenskih funkcij za definicijo kriteri-jske funckcije. Uporaba metode je prikazana na robustnem načrtovanju diferencialnega ojačevalnika. Rezultati kažejo, da je metoda sposobna poiskati nabor parametrov vezja, ki da primerljivo ali pa do neke mere celo boljše vezje kot ga načrtuje človek. Pristop ima velik potencial v vzporednem računanju, a je kljub temu dovolj učinkovit, da lahko pridemo do sprejemljivih rezultatov z uporabo enega samega računalnika. 1 Introduction A major issue in analog IC design is robustness. A robust design satisfies the design requirements in all foreseen operating conditions. Furthermore, a robust design must fulfil all design requirements regardless of the expected process variations that may occur during the fabrication of the designed IC. As the time-to-market becomes shorter automating the design process is becoming an important task/1/. By design requirements we mean circuit characteristics which are of Importance to the user of the designed circuit and can be expressed by real values, such as gain, phase margin, gain-bandwidth product, common mode rejection ratio, distortion, output rise time, input impedance, current consumption, etc. A circuit fulfils the design requirements if all circuit characteristics, which are of importance to its user, lie Inside some predefined Intervals. An IC must fulfil the design requirements in various operating conditions, which also Include various environmental effects. Some common operating conditions whose variations can cause Improper circuit operation are power supply voltage, bias currents and load characteristics. The most common environmental condition that affects the operation of a circuit is the temperature. In order to obtain a robust design the circuit must fulfil the design requirements for a given range of operating conditions. Process variations are another reason speaking in favour of robust design. IC manufacturers describe process variations by so called corner models. Corner models describe several extreme conditions, which can occur during IC fabrication and result In some extreme circuit behaviour. Fora CMOS process usually 4 different corner models are provided to the designer: worst one (WO), worst zero (WZ), worst power (WP) and worst speed (WS). Beside corner models, IC manufacturers also supply a typical mean (TM) model. If robustness is not foreseen at the design stage and already Incorporated in the design, one can expect that only a small number of fabricated ICs will fulfil the design requirements at nominal operating conditions due to process variations. Furthermore only a fraction of these ICs will fulfil the design requirements In all foreseen operating conditions. In the past a lot of effort was invested in finding efficient means of automated nominal design (/2/, /3/, /6/, /5/, /6/). Nominal design however does not produce robust circuits. The resulting circuits satisfy the design requirements only in nominal operating conditions and forthe typ- ical process. In order to obtain a robust circuit and additional step of design centering is required. Design centering techniques are either statistical (/7/, /8/) or deterministic (/9/, /10/, /11/). The whole idea of robust design (as sometimes practised by IC designers) relies on the assumption, that the circuit characteristics reach their extreme values at points where the operating conditions and process variations take their so-called corner values. In order to establish, whether the design is robust, designers examine the performance of the circuit for all combinations of corner values. Every such combination represents a corner point of the design. The number of corner points can be large. Beside 4 corner points for MOS transistors (result of the process variations), every operating condition brings along at least two extreme values - the minimal and the maximal value. For the operating temperature IC designers usually examine more than the two extreme values. The same can also be the case for other operating conditions and process variations. The reason why one examines the circuit for more than only the extreme operating conditions is the fact that the circuit characteristics are not necessarily monotonic functions of operating conditions and process variations. When these functions are not monotonic, the probability of making a wrong conclusion increases with the distance between individual corner points. By examining the circuit at a larger number of "corner" points this distance is decreased. In order to obtain a robust design an IC designer varies the dimensions of individual transistors and other elements of the design until the design fulfils the requirements in all relevant corner points. Whether or not a particular design is robust can be examined by simulating it at those corner points. If one examines the circuit for all combinations of 5 MOS corners, 3 temperature corners and 2 power supply voltage corners, a total of 30 corners must be examined. IC designers practise robust design by iterating corner point simulation and circuit parameter adjustments for selected structure (topology). Obviously the only part of this process where the computer plays a role is the simulation. The parameter adjustment is still performed by the designer manually and is based on knowledge and past experience. One way of automating the process of parameter adjustment is the transformation of the robust design problem, as perceived by the IC designer, into a (constrained) optimization problem. There exist many algorithms for solving (constrained) optimization problems that can be applied to solve the IC designer's robust design problem. The remainder of this paper is organised as follows: first the robust design method is mathematically formulated. A short introduction to optimization is given upon which the relationship between robust design and cost function used in the process of optimization is established. The cost func- tion is divided in two parts: penalties for circuits that cause the simulator to fail at evaluating the circuit and penalties arising from design requirements. The use of the method is illustrated on a robust amplifier design problem. Finally the conclusions and ideas for future work are given. 2 Design Methodology 2.1 Circuit design and corner points The robust design process as perceived and practised by an IC designer is based on the notion of corner points. A corner point is a combination of some process variation and M operating conditions. Suppose that we have a set of possible process variations (1) and for every operating condition a set of values that are of particular interest to the designer (2) Po stands for the characteristics of the nominal IC fabrication process and pI,p\,-;Pm for the nominal operating conditions. The cross product of M + 1 sets from (1) and (2) is the set of corner points C. In general a subset of these points is examined during the process of robust design The number of corners is M K^lln, (3) (4) (=0 The performance of the circuit, (which is the result of some combination of process variations during its fabrication and operating conditions during its use), is described by a vector of N real values y = [v,,..., i?". We represent the circuit as a function that for any combination of n circuit parameters denoted by vector x and some combination of process variations and operating conditions denoted by q produces a vector of circuit characteristics y. y xe R'\qe C,ye R' yix, q) = [yi {x, q), y^ (x, (x, q) = [mx,q),D,(x,q),...,DJx,q)] (5) In the subsequent sections we also use the following notation for (5): Two vectors express the design requirements: a vector of lower bounds b = [b,,...,b^]e R'^ and a vector of upper bounds B = i?"- For the sake of simplicity we allow for any lower bound to take the value - o«, meaning that there is no lower bound on the respective circuit characteristic. Similarly any upper bound can take the value + tx), meaning that no upper bound exists on the respective circuit characteristic. A circuit with circuit parameters x satisfies the design requirements for a particular corner point geC if the following set of relations holds: (6) Let g(x) denote some continuous monotonically increasing function defined for x > 0. Define a new function: 0 x<0 g(x)-giO) x>0 (7) (7) is used to establish the relation between the robust design problem and the constrained optimization problem. A circuit design is satisfactory if it satisfies the design requirements for all corner points from set C. 2.2 Constrained optimization Problems of the form = r(x) s czr" are n-dimensional unconstrained global optimization problems, is the global optimum and r(x) is a cost function. Most unconstrained optimization methods search merely for a local optimum, where the following relation holds: Vr(x)=0 If the search space is constrained, i.e. S cR", the problem becomes a constrained optimization problem. The notion of global optimum remains unchanged, but the definition of local optimum changes. The search space in constrained optimization is defined by means of constraints. In general two kinds of constraints exist. Explicit constraints have the form b0 or h(x)=0. The former one is an inequality constraint and the latter one is an equality constraint. Note, that/!(x) can be any function. Handling implicit constraints is more complicated than handling explicit constraints. When optimizing integrated circuits, the vector of optimized parameters ^ includes mostly circuit parameters like element widths and lengths, although in some cases also cur- rent, frequency, resistance and other values can be among optimized parameters. Explicit constraints are mostly used for setting the limits imposed by the technology like minimum dimensions. Another possible use of explicit constraints is to force a parameter to remain in a particular interval, e.g. one could restrict the transistor width of a differential pair to stay above some given value. Explicit equality constraints can be used to impose a fixed dependence of a parameter on some subset of circuit parameters. Such constraints are easily enforced during optimization. More complex explicit constraints (i.e. explicit constraints on circuit characteristics, explicit inequality constraints) are also possible. Nevertheless one should keep in mind that a large number of more complex explicit constraints could in practice reduce the performance of an optimization algorithm. Another important thing to note regarding optimization algorithms is that in practical cases they do produce a decrease in the cost function value when compared to the initial value. But in general, a large amount of computing time and resources has to be invested in order to find the global optimum of an optimization problem. Generally one is satisfied if: an optimization algorithm provides an improvement over the best economically justified human design, (at least partially) solves some problem without human intervention or helps the designer to speed up the design process. In the past many efficient optimization algorithms that relied on the cost function value along with the values of its derivatives were developed. Since the sensitivity information is generally not available from circuit simulators (at least not to the extent required to calculate the partial derivatives of the cost function), one must rely to a different class of methods. Direct search methods /12/ rely only on cost function value and require no derivative information from the simulator. They are the methods of choice in this work. 2.3 Penalty function for enforcing constraints on circuit performance In order to exploit optimization for robust circuit design a cost function has to be defined. The cost function is supposed to rank the set of possible designs thus making it ordered. Throughout the optimization all designs have the same structure (topology). Only the nominal circuit parameter values (x) are varied. Consider the following penalty function: Filkl (=1 f V V A: + / hiiL A, (8) // Function (8) penalises any design with one or more characteristics lying outside the intervals defined by the respective lower and upper bounds on circuit performance. The penalty is proportionate to the distance from the boundary of the interval. Fora design which characteristics lie inside the intervals defined by b and B, the function returns 0. Note that the penalty function applies to the circuit characteristics for a particular corner point. Since "bad" designs are associated with higher values of the penalty function and "good" designs are associated with 0, the definition of a cost function (which will in turn be minimised by the optimization algorithm) is right at hands: (9) One can stop the optimization algorithm as soon as (9) reaches 0, since the algorithm found a point in the search space for which the corresponding design satisfies all performance constraints (6) in all corners. Furthermore, if the algorithm has a way of detecting the existence of a neighbourhood of x„ where corresponding designs are all satisfactory, one can tell that the design requirements are too "loose". Ideally the design requirements should be so tight that every satisfactory point in the search space has no neighbourhood where all designs fulfil the design requirements. In such case one could be assured that the capabilities of the technology are fully exploited for the particular circuit structure. Pv. ) 1=2,.(11) Based on the results obtained for these corners, further 2N corners are generated (two for every circuit characteristic; one where the lowest value and one where the highest value is expected to take place) and examined: / { If I] If \ // = arg min k=\,...,nj 7 = 0,...,M (12) By searching through corners defined by (11) and (12) we M need to check only K^, -M + 2A^ + 1 corners. The 1=0 price to pay is the risk of obtaining a narrower range for the circuit characteristic y; in case the function DXx,q) is not monotonic with regard to the intervals enclosing operating conditions and intervals enclosing model parameters of process variations. 2.4 Heuristic corner search In previous section robust design was achieved by checking the circuit performance in all relevant corner points of the design (3). Since the total number of corner points grows exponentially with the increasing number of operating conditions (4), the analysis of circuit performance becomes intractable. Approaches for reducing the number of analysed corner points become of interest where one replaces the search through the complete set of corners C by its subset Q Consequently the number of checked corners is reduced to = |Q| < AT and the corresponding term in the cost function becomes: K„ rM=l,F{p{x,s{i))) (10) i=l Several different heuristics can be defined for choosing the set Cs. The method of choice in this paper first examines the individual influences of operating conditions. The collected information is used for predicting the corners where circuit characteristics are expected to reach their extreme values, upon which those corners are examined. In the first part the following set of corners is examined: Inon, = 4 = ■^l' = 4 = Pm ) So = ipü,p\,-,PM) i = 2,...,Ho 2.5 Cumulative cost function The cumulative cost function r^) equals (9) (or (10) if heuristic corner search is used). This causes the optimizer to search for a circuit satisfying all design requirements. The optimization can be stopped as soon as some point where r(x)=0 is found. One also has to consider the case that the simulation itself fails to converge thus rendering the optimization incapable of determining the cost function value for a particular combination of circuit parameters. Besides that the simulator may succeed to simulate certain circuits, but the performance of these circuits is far from the desired performance (e.g. some cf the transistors that are supposed to be in saturation, are not). To resolve the problem an additional penalty term r^^x) is introduced into the cumulative cost function. The value of r^(x) for such circuits should be significantly larger than the contribution of the penalty functions r^(x) (or The additional pen- alty should be proportionate to the severity of the convergence problem (circuit performance problem). Applying optimization to the cumulative cost function can solve the robust design problem. Any box-constrained optimization method can be used. The reason due to which box constraints are sufficient is the fact that we only need to constrain circuit parameters such as transistor widths and lengths to intervals of possible values. The implicit constraints arising from the design requirements are handled by the penalty functions. 3 Results To illustrate the method, robust design has been applied to the circuit structure in Figure 1 /18/. The circuit is an amplifier with differential input, differential output and common mode feedback. The M and W/L values of transistors in Figure 1 (reference circuit) were designed by an IC designer. Since the pd signal is kept low throughout normal operation so inverter Invl and transistors M1 and M2 are irrelevant to the design. An external current source pulls 16|iA from the bias input in order to set the operating point of the circuit. During normal operation Vdda is set to 5Vand Vssa to OV. The agnd input voltage is in the middle between vdda and vssa since it is the analog reference level. The differential input is at v(inp, inn), whereas v(outp, outn) constitutes the differential output. Ideally the cmf input is kept at (v(outp)+v(outn))/2. In the circuit there are several groups of transistors whose dimensions are mutually dependent. Their ratios were kept constant throughout the search. A similar approach can be found in /13/. The lengths of transistors M4-M11 are identical. The ratios of widths for these transistors M4-M11 are also kept constant since they constitute the current mirrors that set the operating point of the circuit. The same goes for M13-M22. The widths of M3 and M12 are adjusted according to designer's experience with regard to the W/L ratios of M4 and M13. Transistors M23, M24 must have the same widths. The same goes for M25 and M26. Transistors in both differential pairs must also be of the same width (M27-M28 and M29-M30). In the automated design process the same values for M were used as in figure 1. 3.1 Design requirements Note that Vds and Vdsat denote the drain-source voltage and the drain-source saturation voltage. For p-MOS they represent the absolute values of respective quantities. Refer to Figure 2 for the test circuit. Vcmf = (outn+outp)/2 Vcom Figure 2: Test setup for the circuit in figure 1. First of all we require that for the operating point of all transistors except Ml, M2 and the transistors in Invl Vds > Vdsat + 0.005 holds in all examined corners. Let Mrei denote the set of all relevant MOS transistors. The saturation measure is defined as Ps., = I rampiv,^.^, (M)+ 0.005 - (M)) Next the offset voltage (i.e. the common mode output voltage at Vjij- = 0, V.„, =0) is measured. Vdda Vdsat holds for all transistors in Mrei- In the AC analysis (transfer function from (inp, inn) to (outp, outn)) the gain at OHz, phase margin (difference to 180° at OdB gain) and the frequency where gain falls to OdB are measured. Noise analysis is performed with output at (outp, outn) and input at Vdif. Input noise spectrum density is measured at two frequencies: 10Hz (ni) and 1 kHz (n?). The measure of the amplifier area is defined as the sum of WL products for all transistors in Mrei- 3.2 The set of corner points A total of 5 CMOS corners arising from random process variations were examined along with the corners for temperature, Vdda, Ibias, and Ci. See Table 1 for the complete list of examined values. A total of 405 corners for the exhaustive corner search and 13+20=33 corners forthe heuristic corner search must be examined. Nominal Extreme values MOS comers TM WO, WZ, WP, WS Temperature 25°C -40°C, 125 °C Power supply SV 4.5V, 5.5V Bias current leuA 13.6uA, 18.4UA Load capacitance 6pF 4.2pF, 7.8pF Table 1: Corners of the design. Table 2 lists the design requirements (lower and upper bounds on individual circuit characteristics). 3.3 Results of optimization experiment The optimizer tried to find a solution starting from a design that didn't work (all widths were 20|j,m, lengths 2\im and M3/M4 (M12/M13) width ratios were 0.2). 12 parame- ters were optimized. The range for transistor dimensions was 0.6|im to lOOOjim for widths (5 parameters), 0.6jim to 3|im for lengths (5 parameters), and 0.01 to 1.0 for M3/ M4 (M12/M13) width ratios (2 parameters). Additional penalty terms (r^i^) were introduced in the following cases: 1. In case a failure in initial OP analysis occurred penalty of 10® was added. The offset was set to 10V and the remaining analyses (DC analyses, AC analysis and NOISE analysis) were skipped for the particular corner. All problems encountered in this analysis would reoccur in all other analyses since OP analysis precedes or is included in any other type of analysis. 2. In case a failure in the differential mode DC sweep analysis occurred the linear range was set to 0%. 3. In case of a failure in the common mode DC sweep analysis the lower (upper) bound for the common mode range was set to +5V (-5V). 4. In case the AC analysis failed, OHz gain, phase margin and OdB frequency were set to 0. 5. In case the NOISE analysis failed n? {nz) was set to 10-"^ VI4h~z (^Q-^Vlitfz). 6. If any of the failures from cases 1-5 occurred in the first part of the heuristic search, the second part of the search was skipped with additional penalty of 10®. 7. In case of a failure in OP analysis (case 1) when the remaining analyses were skipped for a particular corner, circuit characteristics that were supposed to result from the skipped analyses were set to the values mentioned in cases 2-5. SPICE was used as the circuit simulator /14/. The optimization method (/15/, /16/) was a modified constrained simplex method based on /17/, The results are summarized in Tables 3-5. The optimization was stopped as soon as some circuit with cost function value less or equal 0 was found. Requirements b (min) B (max) A (1 penalty point per) Sat. measure — OO 0 0.001m Offset voltage 0 (or — oo) 50mV ImV Linear range 73% 1 00% (or -f- CO ) 0.1% CM range (low) — oo -1.2V 1mV CM range (high) 1.2V -f- CO ImV OHz gain 60dB -)- CO IdB Phase margin 50° 180° (or-h oo ) 1° OdB frequency 7.0 MHz -1- oo 0.1MHz Noise at 1 OHz - CO 620 nV/Vnz 100 nV /Vhz Noise at 1 kHz - CO 62 nV /a/hz 10 nV /Vhz Area 0 um ^ (or — oo) 8300 |j m ^ lOOum^ Table 2: Design requirements. 154 Lowest Nominal Higliest Offset voltage 0.195mV 5.5mV 32.7mV Linear range 74.0% 79.4% 81.6% CM range (lo.) -1.65V -1.40V -1.15V CM range