19
Original scientific paper
 MIDEM Society
1 Introduction
In recent years, with miniaturization of technology, the 
demand of low voltage power supply has become es-
sential. For designing of analog circuits, it has become 
the major factor that they operate with low supply volt-
age and power as their digital counterparts. Analog 
designers face many difficulties and challenges due 
to the limited voltage headroom, because the thresh-
old voltage and drain-to-source saturation voltage of 
CMOS technologies do not scale down at the same rate 
as the supply voltage or do not scale at all with low sup-
ply voltage. The power supply requirement of analog 
circuits can be reduced by two techniques known as 
technology modification and transistor implementa-
Low-Voltage Highly Linear Floating Gate 
MOSFET Based Source Degenerated OTA and its 
Applications
Tanmay Dubey, Rishikesh Pandey
Thapar University, Department of Electronics and Communication Engineering, Patiala, India
Abstract: The paper proposes a novel low-voltage highly linear floating gate MOSFET based source degenerated OTA. The low 
voltage operation of the proposed OTA is achieved by using floating gate MOSFETs as input transistors and the linearity is increased 
by using source degeneration linearization technique. The proposed OTA has low power supply requirement of ±0.6V, rail-to-rail input 
differential voltage range and wide bandwidth of 1.472 GHz. The applications of the proposed OTA such as active inductor, tunable 
resistors and filters are also proposed. Finally, the simulation results of the proposed circuits using typical parameters of UMC 0.18 μm 
CMOS technology are depicted to confirm the theoretical analysis.
Keywords: Active inductor; filters; floating gate MOSFET; OTA; resistors 
Nizkonapetostni linearen vhodno izrojen OTA na 
osnovi MOSFETa s plavajočimi vrati in njegova 
uporaba
Izvleček: Članek predlaga nov nizkonapetostni linearen vhodno izrojen OTA na osnovi MOSFETa s plavajočimi vrati. Nizko napetostno 
delovanje je zagotovljeno z uporabo vhodnih MOSFET-ov s plavajočimi vrati, linearnost pa je povečana za uporabo tehnike izroditve 
vira. Predlagan OTA zahteva napajanje ±0.6V, polni diferencialen napetostni obseg in široko pasovno širino 1.472 GHz. Predlagana je 
uporaba OTA kot dušilka, nastavljiv upor in filter. Simulacijski rezultati v UMC 0.18μm CMOS tehnologiji potrjujejo teoretične analize.
Ključne besede: aktivna dušilka; filter; MOSFETR s plavajočimi vrati; OTA; upor
* Corresponding Author’s e-mail: riship23@gmail.com
Journal of Microelectronics, 
Electronic Components and Materials
Vol. 48, No. 1(2018), 19 – 28
tion [1]. Using technology modification technique, the 
device technology dependent threshold voltage can 
be reduced. But, higher threshold voltage gives bet-
ter noise immunity and the lower threshold voltage 
reduces the noise margin to result in poor signal to 
noise ratio (SNR). Hence, for present day CMOS tech-
nology, reduction in threshold voltage is limited to the 
noise floor level, below which further reduction will in-
troduce an amount of noise sufficient to result in very 
complex circuits. 
Some of the transistor implementation techniques 
available in literature are level shifters, self-cascode 
MOSFETs, sub-threshold MOSFETs, bulk-driven MOS-

20
FETs, floating gate MOSFETs [2-3], etc. Out of these 
floating gate MOSFETs present a unique advantage of 
programmability of threshold voltage, which can be 
lowered from its conventional value, thus makes it suit-
able for low voltage applications [4-5]. FGMOS is also 
compatible with standard double-poly CMOS process 
technology and has been used to develop digital-to-
analog (D/A) converters [6], voltage controlled resistors 
[7]-[8], neural networks [9], operational transconduct-
ance amplifiers [5], dividers [8, 10], etc. Motivated by 
the unique characteristics of the floating gate MOS-
FETs, a highly linear OTA is proposed. The OTA is a versa-
tile building block employed as the active cell in many 
analog integrated circuits such as continuous-time fil-
ters [11-14], variable gain amplifiers [15], etc. 
The paper is organized as follows. The operation of 
floating gate MOSFET is discussed in Section 2. Sec-
tion 3 proposes floating gate MOSFET based source 
degenerated OTA. The applications of proposed OTA 
such as active inductor, tunable resistors and filters are 
proposed in Section 4. In Section 5, simulation results 
are given to demonstrate the effectiveness of the pro-
posed circuits. The paper is concluded in Section 6. 
2 Operation of floating gate MOSFET
The structure of floating gate MOSFET is similar to a 
conventional MOSFET. The difference between these 
two is the gate, which is electronically isolated, creating 
a floating node in DC, and a number of secondary gates 
electrically isolated from the floating gate, above which 
they are deposited. There exist only capacitive connec-
tion between inputs and floating gate [16]. The floating 
gate which is completely surrounded by highly resis-
tive material serves as charge storage device. There-
fore, the first application of the floating gate MOSFET 
was to store the digital information for very long pe-
riod in structures such as EPROMs, EEPROMs and Flash 
memories [17]. Along with this, floating gate MOSFET 
devices show easy addition and compression of volt-
age signals, as well as allow a reduction of the effective 
threshold voltage. The threshold voltage of a floating 
gate MOSFET can be controlled by the amount of the 
static charge stored in the floating gate. This proper-
ty has prompted their use in low voltage low power 
analog circuits [18]. The symbol and equivalent circuit 
model of N-input floating gate MOSFET are shown in 
Figures 1 (a) and (b) respectively. In both the figures, V
i
 
(for i=1, 2,…, N) are the control input voltages and D, S 
and B are the drain, source and substrate, respectively.
The drain current I
D 
of n-type N-input floating gate 
MOSFET in saturation region is given as [19, 20]:
 
()
2
N
ii S
GD GB i1
Dn ox DS BS T
TT T
CV
CC 1
W
Iμ CV V V
L
2C CC
=

=+ +− 


∑
  (1)
Where µ
n
 is the electron mobility, C
ox
 is
 
the gate-oxide 
capacitance per unit area, (W/L) is the aspect ratio, 
 
N
i
i1
C
=
∑ 
is the sum of the N-input capacitances, V
iS
 is the 
applied input voltage at the i
th
 input gate with respect 
to source, V
DS
 is the drain-to-source voltage, V
BS
 is the 
substrate-to-source voltage, V
T 
 is the threshold volt-
age, C
T 
(= 
 
N
iG DG SG B
i1
 CC CC
=
+++
∑
) is the total capaci-
tance seen by the floating-gate, C
GD
 is the parasitic 
capacitance between floating-gate and drain, C
GS
 is 
the parasitic capacitance between floating-gate and 
source, and C
GB
 is the capacitance between floating-
gate and substrate. Equation (1) can also be written as:
 
()
2
Dn FGST
IK VV       =−
   (2)
T. Dubey et al; Informacije Midem, Vol. 48, No. 1(2018), 19 – 28
Figure 1: Floating gate MOSFET (a) Symbol and (b) 
equivalent circuit model
(a)
(b)

21
Where 
 
() nn ox
1
W
K μC 
L
2

=


 is the transconductance 
parameter and V
FGS
   
 
N
ii S
GD GB i1
DS BS
TT T
CV
CC
 V V
CC C
=

=+ + 


∑
 
is the voltage between floating gate and source of the 
floating gate MOSFET. 
3 Proposed floating gate MOSFET 
based source degenerated OTA
The proposed floating gate MOSFET based source de-
generated OTA is shown in Figure 2. The two differential 
pairs formed using two-input floating gate MOSFETs 
M
1
, M
3
 and M
2
, M
4
 are connected in series to reduce the 
distortion [21]. The transistors M
1
-M
4
 are biased in the 
saturation region. The differential pairs are also source 
degenerated by resistors R
1
 and R
2
. Two input voltages 
V
1
 and V
2
 are applied at one of the gate terminals of 
transistors M
1
 and M
2
, respectively. The proposed cir-
cuit is properly biased with current sources of same 
values connected to the source terminals of transistors 
M
1
, M
2
, M
3
 and M
4
. 
Figure 2: Proposed floating gate MOSFET based source 
degenerated OTA
Using (2), the drain currents I
D1
, I
D2
, I
D3
 and I
D4
 of transis-
tors M
1
, M
2
, M
3
 and M
4
, respectively are given as
 
()
2
B
D1 nF GS1T
I
II KV V       
2
=+ =−
   (3)
 
()
2
B
D2 nF GS2T
I
II KV V    (
2
=− =−  (4)
 
()
2
B
D3 nF GS3T
I
II KV V 
2
=− =−
   (5)
 
()
2
B
D4 nF GS4T
I
II KV V  
2
=+ =−  (6)
where I
B
 is the bias current, I is the current flowing 
through the resistors R
1
 and R
2
, K
n
 is the transconduct-
ance parameter, V
T
 is the threshold voltage, V
FGS1 
is the 
voltage between floating-gate and source of transis-
tor M
1
, V
FGS2 
is the voltage between floating-gate and 
source of transistor M
2
, V
FGS3
 is the voltage between 
floating-gate and source of transistor M
3 
and V
FGS4
 is the 
voltage between floating-gate and source of transistor 
M
4
. 
The voltages V
FGS1, 
V
FGS2
, V
FGS3
, and V
FGS4 
are given as
 
GD GB 12
FGS1 1S bS DS1B S1
TT TT
CC CC
VV VV V
CC CC
=+++ (7)
 
GD GB 12
FGS2 2S bS DS2B S2
TT TT
CC CC
VV VV V
CC CC
=+++  (8)
 
GD GB 12
FGS3 xS bS DS3B S3
TT TT
CC CC
VV VV V
CC CC
=+++  (9)
 
GD GB 12
FGS4 xS bS DS4B S4
TT TT
CC CC
VV VV V
CC CC
=+++     (10)
where C
1
 & C
2
 are input capacitances, V
1S 
& V
2S 
 are the 
applied input voltages with respect to source at one of 
the gate terminals of transistors M
1
 & M
2
 respectively, V
X
 
is the applied voltage with respect to source at one of 
the gate terminals of transistors M
3
 & M
4
, V
bs
 is DC bias 
voltage with respect to source, V
DS1
,
 
V
DS2
, V
DS3
 & V
DS4
  are 
drain-to-source voltages of transistors M
1
, M
2
, M
3
 & M
4 
respectively, V
BS1
, V
BS2
, V
BS3
 &V
BS4
  are substrate-to-source 
voltages of transistors M
1
, M
2
, M
3
 & M
4 
respectively,
 
 and 
C
T 
(=
 
N
iG DG SG B
i1
 CC CC
=
+++
∑
) is the total capacitance 
seen by the floating-gate. Applying KVL in the loop AB-
CDEFG of Figure 2, the loop equation can be written as
 
1F GS11 FGS3 FGS4 2F GS22
VV IR VVIR VV 0  −− +−−+ −=  (11)
Substituting V
1
-V
2
= V
in
 (differential input voltage) and 
R
1
=R
2
=R, (11) is modified as
 
in FGS1 FGS3 FGS4 FGS2
V2 IR VVVV  −= −+−                 (12)
Using (7), (8), (9), and (10) in (12), the current (I) flowing 
through resisters R
1
 and R
2
 is given as
T. Dubey et al; Informacije Midem, Vol. 48, No. 1(2018), 19 – 28

22
 
() ()
2
ni ni n
B
KV 2IRV 2IR
I
I    
22 K1 6
−−
=−
      (13)
From Figure 2, the output current (I
out
) of proposed OTA 
can be observed as
 
out D1 D2
II I2 I =−=                   (14)
Using
 (13) and (14), the output current (I
out
) is given as
 
()
()
2
in out
B
outn in out
VI R
I
I KV IR  
2K 16
−
=− −
       (15) 
Equation (15) shows the relationship between output 
current (I
out
) and differential input voltage (V
in
) of pro-
posed OTA. The transconductance of the proposed OTA 
can be calculated as
 
m
m
m
g
G     
1g R
=
+
                   (16)
where 
 
nB
m
KI
g=
2
 is the transconductance of the tran-
sistors M
1
-M
4
.  The nonlinear term in (15) depends on 
V
in
 – I
out
R rather than V
in
. When R>>1/g
m
, the nonline-
ar term becomes zero and thereby high linearity can 
be achieved. The complete circuit of proposed OTA is 
shown in Figure 3, in which resistors R1 and R2 are re-
placed with the help of transistors M
R1
-M
R2
 and M
R3
-M
R4
, 
respectively.  These transistors (M
R1
-M
R4
) are operating 
in the ohmic region. The differential inputs V
1
 and V
2
 are 
applied at one of the input gates of floating-gate transis-
tors M
1 
and M
2 
respectively and the output currents I
out1
 
and I
out2 
are also taken out differentially, which allows the 
proposed OTA to be categorized as fully differential OTA. 
The fully differential structure of the OTA helps for bet-
ter linearity as the even harmonics are cancelled out and 
only odd harmonics are left to contribute in total har-
monic distortion. The common-mode voltage variations 
at the output nodes due to the fully differential structure 
can be stabilized by Common-Mode Feedback (CMFB) 
circuits. But the inclusion of CMFB circuits may results in 
stability issues as well as increases the complexity and 
power consumption. A current source formed by PMOS 
transistor M
5
 is used for biasing purpose. Three current 
mirrors are formed using NMOS transistors M
6
–M
10
, M
17
–
M
18
, M
19
–M
20
 and two current mirrors are formed using 
PMOS transistors M
11
 – M
13,
 M
14
 – M
16. 
These current mir-
rors are used to copy the currents at the appropriate 
nodes of the circuit. The remaining transistors are used 
to transfer the currents at the appropriate nodes. 
4 Applications of proposed OTA
The proposed OTA is used to develop some of the im-
portant analog building blocks such as active inductor, 
tunable resistors and filters. 
Figure 3: Complete circuit diagram of proposed OTA
T. Dubey et al; Informacije Midem, Vol. 48, No. 1(2018), 19 – 28

23
4.1 Active inductor
The proposed active inductor is shown in Figure 4. The 
inductor has been developed using a capacitor C and 
two proposed OTA.  
Figure 4: Proposed active inductor
In Figure 4, the current (I
2
) flowing through capacitor C 
is given as
 
2O 1m 1
II GV   ==                   (17)
where G
m
 is the transconductance of the proposed OTA 
and V
1
 is the input voltage.
The input current (I
1
) can be written as
 
2
1O 2m 2m
I
II GV G 
sC
== = ;                  (18)
where V
2
 is the voltage across capacitor C. 
Using (17) and  (18), the current (I
1
) is modified as
 
11
1
eq
2
m
VV
I 
sL
C
s
G
==



; where 
 
2 eq
m
C
L .
G
=
 (19)
From (19), it can be seen that the value of equivalent in-
ductance depends on the transconductance G
m 
of the 
proposed OTA.
4.2 Tunable resistors
Tunable resistors have a significant role in the analog 
circuit design because they can be employed as tun-
ing elements in various analog circuit applications. The 
tunable floating and grounded resistors based on pro-
posed OTA are shown in Figures 5 (a) and (b), respec-
tively. 
Figure 5: Proposed tunable resistors (a)  floating resis-
tor and (b) grounded resistor
In Figure 5 (a), the input current (I
in
) is given as
 
()
in out m1 2
II GVV  == −                 (20)
where V
1 
and V
2 
are the input voltages and G
m
 is the 
transconductance of proposed OTA.
From (20), the equivalent resistance (R
Feq
) is given as
 
()
12
Feq
in m
VV
1
R    
IG
−
== ; 
where                     (21)
 
 
()
in
m
12
I
G
VV
=
−
 
The grounded resistor shown in Fig 5(b), it is observed 
that V
2 
= 0, and V
1 
= V
in
. Substituting the values of V
1 
and 
V
2 
in (21), the equivalent resistance (R
eq
) is given as
 
in
eq '
in m
V 1
R
IG
==
;  where 
 
' in
m
in
I
G
V
=
                 (22)
From (21) and (22), it can be seen that the equivalent 
resistances R
Feq  
and R
eq
 of floating and grounded resis-
tors, respectively are varied with the transconductance.
4.3 Tunable filters
The tunable low-pass, high-pass and band-pass filters 
based on proposed OTA are presented.
(a)
(b)
T. Dubey et al; Informacije Midem, Vol. 48, No. 1(2018), 19 – 28

24
4.3.1 Low-pass filters
The low-pass filters based on proposed OTA is shown 
in Figure 6.  
Figure 6: Proposed low-pass filter
In the figure, the current (I) flowing through capacitor C 
and the output voltage (
0
V ) are given as
 
()
mi n0
IGVV   =−                   (23)
 
0
I
V    
sC
=                   (24)
where G
m
 is the transconductance of proposed OTA. 
Using (23) and (24), the transfer function of first order 
low-pass filter can be written as
 
o m
in m
V G
     
VG sC
=
+
                   (25)
4.3.2 High-pass filters
The high-pass filter based on proposed OTA is shown 
in Figure 7. 
Figure 7: Proposed high-pass filter
In the figure, applying KCL at node 1, we get
 
()
in 0m 0
VV sC GV 0 −−=                  (26)
where G
m
 is the transconductance of proposed OTA. 
From (26), the transfer function of first order high-pass 
filter can be written as
 
o
in m
V sC
 
VG sC
=
+
                   (27)
4.3.3 Proposed band-pass filters 
The band-pass filter based on proposed OTA is shown 
in Figure 8. In the figure, applying KCL at nodes 1 and 
2, we get
 
() ()
in 11 m1 10 m
VV sC GV VV G −= +−                (28)
 
()
20 m1 0
sC VG VV =−
                  (29)
Using (28) and (29), the transfer function of first order 
band-pass filter can be written as
 
()
o 1m
22
in 12 m1 2m
V sCG
Vs CC sG C2 CG
=
++ +
                (30)
Figure 8: Proposed band-pass filter
5 Simulation results
In this Section, the simulation results of proposed OTA 
and its applications such as inductor, tunable resistors 
and filters are presented. The workability of all of the pro-
posed circuits have been verified by Cadence EDA tool us-
ing typical parameters of UMC 0.18μm CMOS technology.
5.1 Simulation results of floating-gate MOSFET based 
source degenerated OTA
The DC transfer characteristic of the proposed OTA (Fig-
ure 3) is shown in Figure 9. From the plot, it can be seen 
that the output current of the OTA varies linearly with 
respect to the input differential voltage (V
in
) and the 
range of the input differential voltage for linear opera-
tion is -0.6V to +0.6V. 
T. Dubey et al; Informacije Midem, Vol. 48, No. 1(2018), 19 – 28

25
Figure 9: DC transfer characteristic of proposed OTA
The frequency response of the proposed OTA is shown 
in Figure 10. From figure, the transconductance is ob-
served as -82.41dB (75.5μA/V) and the bandwidth is 
1.47GHz for capacitive load of 1pF. Also, it is evident 
that the proposed OTA is stable as the gain is negative 
in decibels (dB) when phase angle is -180
0
. The band-
width gradually decreases for the larger values of ca-
pacitive loads.  
Figure 10: Frequency response of proposed OTA
The variation of the transconductance with respect to 
bias current (I
B
), ranging from 120µA to 200µA with the 
increment of 20µA is plotted in Figure 11 and the cor-
responding values of transconductance are obtained 
as 70.08 μA/V, 72.78 μA/V, 75.54 μA/V, 80.18 μA/V and 
87.85 μA/V, respectively. 
Figure 11: Variation of transconductance with respect 
to bias current (I
B
)
For the distortion analysis of the proposed OTA, the sinu-
soidal differential input voltage of 5MHz with peak-to-
peak amplitude ranging from 0.1V to 1.2V is employed. 
Figure 12: Total Harmonic Distortion plot of proposed 
OTA
Table 1. Comparison of proposed OTA with other OTAs available in literature
References Power
Supply
(V)
Gm
(μA/V)
Bandwidth
(MHz)
Input 
Range
(Vpp)
Power
Consumption
(mW)
THD (db)
@Frequency (MHz)
@Input (Vpp)
[22] ±0.9 22 - 1 0.057 -
[23] 1.5 40 65 0.95 0.126 -110@0.001@0.35
[24] 0.8 28.4 - 0.8 0.0312 -40@1@0.8
[25] 1.5 155 40 0.6 0.042 -55@5@0.1
[26] 2 266 175 0.6 0.160 -48@0.001@0.4
[27] ±1.5 850 780 0.4 20 -
[28] ±1.5 46 - 3 2.6 -60@0.1@3
[29] 0.5 245 10 0.5 0.11 -45@5@0.4
[30] 0.7 - - 1.4 0.010 -35@5@0.4
Proposed work ±0.6 75.5 1472 1.2 0.56 -42@5@1
T. Dubey et al; Informacije Midem, Vol. 48, No. 1(2018), 19 – 28

26
Figure 12 shows the total harmonic distortion (THD) 
obtained in the output waveform as a function of the 
peak-to-peak input voltage and it is observed that for 
differential input voltage (V
in
) ranging from 0.1V to 1V, 
distortion is still low (≤ -42dB). The comparison be-
tween the performance parameters of proposed high-
ly linear floating gate MOSFET based source degener-
ated OTA with the existing OTAs available in literature 
is listed in Table 1. From the table it is observed that 
the proposed circuit has rail-to-rail input voltage range 
with low power supply and high bandwidth.
5.3 Simulation results of active inductor
For the simulated inductances the value of the capaci-
tance (C) is chosen as 1pF. The values of equivalent 
inductance (L
eq
) are obtained as 0.129 mH, 0.155mH, 
0.175 mH, 0.188 mH and 0.203 mH for different   values 
of transconductance (Gm) as 87.85 μA/V, 80.18 μA/V, 
75.54 μA/V, 72.78 μA/V and 70.08 μA/V, respectively. 
5.4 Simulation results of proposed tunable resistors
Figure 13 shows the I-V characteristics of the floating 
resistor (Figure 5(a)) operating at supply voltages of 
±0.6V. The current I
in
 is plotted for various values of V
2
 
ranging from -0.3V to 0.3V with the increment of 0.15V, 
while V
1
 is varied from -0.3V to 0.3V. From the plot, it 
can be seen that the proposed circuit behaves as lin-
ear floating resistor over the differential input voltage 
range from -0.3V to 0.3V. The values of the equivalent 
resistance (R
Feq
) are obtained as 9.21 KΩ, 8.84 KΩ, 8.69 
KΩ, 8.43 KΩ and 8.21 KΩ for V
2
 equals to -0.30V, -0.15V, 
0V, 0.15V and 0.30V, respectively. Also, the grounded 
resistor is realized by connecting the second input volt-
age source (V
2
) to the ground. The values of the equiva-
lent grounded resistor (R
eq
) for different values of ap-
plied bias current (I
B
) as 120 μA , 140 μA, 160 μA , 180 μA 
and 200 μA are obtained as 10.82 KΩ , 9.5 KΩ, 8.69 KΩ, 
7.75 KΩ and 7.19 KΩ, respectively. 
Figure 13: DC characteristic of proposed floating resis-
tor
5.5 Simulation results of proposed filters
The proposed OTA is used to develop first order low 
pass, high pass and band pass filters. The frequency re-
sponse of first order low pass, high pass and band pass 
filters for various values of bias current ranging from 
120μA to 200μA with the increment of 20μA are shown 
in Figures 14 (a), (b) and (c), respectively. 
Figure 14: Frequency response of proposed first order: 
(a) low pass, (b) high pass and (c) band pass filters
6 Conclusions
A highly linear floating gate MOSFET based source de-
generated OTA is developed. The proposed OTA utilizes 
floating gate MOSFETs to reduce the power supply re-
quirement of the circuit and source degeneration tech-
nique is used to increase the linearity of the designed 
OTA. The proposed OTA operates at ±0.6V power sup-
ply. The circuit has rail-to-rail input voltage range with 
transconductance gain of 75.5μA/V. The 3db band-
width of the designed OTA is 1.47GHz. The proposed 
OTA has wide input voltage differential range, low 
power supply requirement and high bandwidth. 
7 Acknowledgment
The authors would like to express their sincere thanks 
to Prof. Vijaya Bhadauria from Motilal Nehru Institute 
(a)
(b)
(c)
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of Technology Allahabad, India for her valuable com-
ments and suggestions.
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Arrived: 18. 09. 2017
Accepted: 04. 01. 2018
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