Elektrotehniski vestnik 78(4): 229-235, 2011 English edition Effective Controller Design for the Cascaded H-bridge Multilevel DSTATCOM for Reactive Compensation in Distribution Utilities Lin Xu1, Yang Han2 1Sichuan Electric Power Research Institute, No.24, QingHua Road, QingYang District, 610072 Chengdu, China E-mail: xulin198431 @hotmail.com 2School of Mechatronics Engineering, University of Electronics Science and Technology of China, No.2006 XiYuan Road, West Park of Chengdu High-Tech Zone, 611731 Chengdu, China E-mail: hanyang_facts @ hotmail. com Abstract. The Static Synchronous Compensators (STATCOMs) have been recoginzed as the most effective solution for dynamic reactive power compensation, voltage stability enhancement and subsynchronous resonance damping purposes in the electric power systems. The STATCOMs in the distribution utilites (DSTATCOMs) are increasingly investigated for dynamic reactive power compensation and power quality improvement in the distribution utilites. This paper presents a novel control scheme for the cascaded H-bridge (CHB) DSTATCOM. The principle of the carrier phase-shifted pulse-width modulation (CPS-PWM) and the mathematical model of the CHB-DSTATCOM are presented. The power balancing mechanism and the stable control region are analyzed. The current loop controller and the dc-link voltage balancing controller are synthesized and the design guidelines are provided. The simulation results obtained from the Electromagnetic Transient Program / Alternative Transient Program (EMTP/ATP) are presented and evaluated, which verifies the validity and effectiveness of the devised control scheme. Keywords: Multilevel inverter, cascaded H-bridge, reactive power compensation, PLL, DSTATCOM, adaptive filter, EMTP/ATP 1 Introduction In recent years, the power quality issues have become important topic due to the proliferation of disturbing loads, which causes significant voltage fluctuations, sag/swell and temporary interruptions. To mitigate the voltage disturbance problems, the static synchronous compensator (STATCOM) are the most suitable solutions, which can be installed at the transmission networks or at the distribution networks to protect the voltage sensitive loads. Due to its modularity and flexibility of manufacturing, the cascaded H-bridge (CHB) inverter is appreciated for high-power medium-voltage power quality conditioner applications. However, restricted by the limited switching frequency of the power electronic devices, achieving dc-link voltage balancing and sufficient controller bandwidth is rather complicated [1-3, 5]. The design guidelines for CHB-DSTATCOM have not been reported in the previous literatures. Hence, this paper aims to cover this gap. The analysis for active and reactive power distribution between the two cells is presented. Based on the power balancing mechanism, a novel dc-link voltage control scheme is proposed by splitting the control task into two parts, i.e., the average voltage controller and voltage balancing controller. A novel grid-synchronization scheme based on the adaptive linear neural network (ADALINE) is devised to acquire the phase angle of grid voltage [4]. Simulation results obtained from the alternative transient program (ATP) are provided, which verifies the validity and effectiveness of the devised control scheme. 2 Principle of the carrier phase-shifted PWM Fig.1 shows the circuit diagram of the five-level cascaded multilevel DSTATCOM based on two H-bridge modules. In Fig. 1, Lg and Rg indicate the line impedance. Each H-bridge includes four IGBT switches with anti-parallel diodes and a dc-link capacitor. Thus the output voltages of the CHB-DSTATCOM can be derived as: vaN=vai+va2. Assuming vdc1=vdc2=Vdc in steady state and the unipolar modulation scheme is adopted in the PWM process, thus each H-bridge would produce three voltage levels: -Vdc, 0, Vdc. With reference to the upper bridge, it is possible to set va1=+Vdc by turning on switches Sii and S14 and va1=-Vdc by turning on switches S12 and S13. Moreover, it is possible to set va1=0 by turning on either S11 and S12 or S13 and S14, the lower bridge operates in a similar manner. Thus five distinct voltage levels can be synthesized at the ac terminals. It is worth noticing that, the switching states of Sx1, Sx2 (x=1, 2, 3) must be complementary to those of Sx3, Sx4 (x=1, 2, 3) in order to avoid short circuit of the H-bridges [2, 3], 0.180 0.184 0.188 0.192 0.196 [s] 0.200 (file CHB_APF_Var_2B_Aug18.pl4; x-var t) t: CTR_H1° t: CTR_H2D t: VTRI* t: VTR_2* v:VOUT -• factors: 11 1 11 2.50E-03 offsets: 0 0 -3 0 -3 -6 (a) 2-i- 0 0 A-V WV -A- tri "TV V \ / V V V V \ / V V V v \ 4-.................... "u u U "L J u u n . u .1 r A; IT n .............. 0 1111 pnnnnnnnnrmTr^ Figure 1. Block diagram of the cascaded H-bridge multilevel DSTATCOM. To obtain five level output voltage at the ac terminal, the carrier signals utilized in each cell must be phase shifted by 90 degree in case of two H-bridge module configuration. Fig.2(a) shows the waveforms of the modulation signal, phase-shifted carriers and the output multilevel voltage of the CHB-DSTATCOM. Fig.2(b) shows the enlarged view of Fig.2(a) including the gating signals of the first IGBT for each H-bridge inverter. Notably, the variables in this paper are as follows: t:CTR_H1^The modulation signal of the first cell; t:CTR_H2^ The modulation signal of the second cell; t:VTRI^The carrier signal of the first cell; t:VTR_2^ The carrier signal of the second cell; v: 'VOUT -'^The synthesizes multilevel voltage 'vaN'; t: 'SIG1'^The gating signal for IGBT S11; t: 'SIG5'^The gating signal for IGBT S21; t:VBC_H1^The output of the first VBC controller; t:VBC_H2^The output of the second VBC controller; t:P1, t:P2^The output of the average voltage controller; t:VDC1^The dc-link voltage in the first inverter; t:VDC2^The dc-link voltage in the second inverter; c: 'SA -MA'^The grid side current; t: IS_REF ->The reference signal for the grid current; t: IS_ERR ^The grid side tracking error; It should be noticed that, the scaling factors and offsets of these signals are marked at the bottom of each figure. 0.180 0.181 0.182 0.183 0.184 [s] 0.185 (file CHB_APF_Var_2B_Aug18.pl4; x-var t) t: CTR_H1° t: CTR_H2° t: VTRß t: VTR_2x factors: 11 1 11 offsets: 0 0 -5 0 -5 v:VOUT - t: SIG1 t: SIG5 . 5.00E-03 1 1 -10 -3 -8 (b) Figure 2. The simulated waveforms of the CHB-DSTATCOM: (a) The waveform of the modulation signal, phase-shifted carriers and the output multilevel voltage; (b) The enlarged view of (a) including the gating signals of the first IGBT for each H-bridge inverter. 3 The Model Derivation of CHB-DSTATCOM Referring to Fig.1, the switching functions of the multilevel CHB-DSTATCOM can be derived as [2, 3]: \fl = s11 ' s14 - s12 ' s13 (i) [ f2 = s21 ' s24 — s22 ' s23 The value of fx (x=1, 2) indicates the dynamic process of charging and discharging between the dc-link capacitors C1 and C2. Supposing the DSTATCOM current ic is positive, then the capacitor Cx (x=1, 2) is charging if fx=1, discharging if fx =-1, and not undergoing any of these processes if fx=0. Complementary phenomenon appears if the inverter current is negative. The following assumptions are made for deriving the model of the cascaded H-bridge inverters: (a)The grid is assumed to be AC voltage source; (b)The losses of the multilevel DSTATCOM are categorized as effective series loss and parallel loss. The series loss and interfacing inductor loss are represented as equivalent series resistance (ESR). Parallel losses are represented as shunt connected resistances across the dc-link capacitors, corresponding to the active power loss of the H-bridge, including blocking loss, capacitor loss and absorbing circuit loss, etc. The differential equation describing the dynamics of the coupling inductor between the cascaded H-bridge inverter and the grid is derived as [5]: dlc- + MM + f2 Vdc 2 (2) vr„ = RL + L- dt where the variable vsa represents grid voltage at the point of common coupling (PCC) [see Figure 1], L represents the inductance of the coupling inductor and R represents the equivalent series resistance. The variables vdc1 and vdc2 are the actual voltages across the dc-link capacitors of the cascaded H-bridge inverter, which may not equal to the reference voltage during dynamic process. According to the Kirchoff's law, the currents flowing into the dc-link capacitors C1 and C2 can be expressed as: lC1 = Ci- dv, del dt — lo1 lR1 — f1le lC 2 = C dv de2 dt — lo2 lR2 - f2le Vde1 Ri v de 2 R2 where R1 and R2 are the equivalent resistance of each H-bridges, representing the parallel losses. The variables lo1 and lo2 represent the total dc-link current and lR1 and lR2 represent the currents in the dc-link resistance of the individual H-bridge module. Let the vector of state variables as X2=[lc, vdc1, vdc2]T and U2=[vsa, 0, 0]T, as input vector, rearranging Eqs.(1)-(3), the state equations can be rewritten in the compact matrix form as: X2 - a2X2 + b2U >2U 2 (4) where a 2 - R _ f _A L L L f1 1 0 C1 R1C1 f2 C2 0 1 R2C2 b2 I 0 0 L 0 0 0 0 0 0 Figure 3. The DSTATCOM. equivalent circuit diagram of the CHB- }a1 — f1Vde1 ' PrI — Vde1lR1 ;a2 — f2Vde2' Pr2 — Vde2lR2 (5) where pR1 and pR2 represents the active power consumed by the effective resistance across the dc-link capacitors. For the sake of brevity, the equivalent resitance of the coupling inductor is neglected, hence Eq.(2) can be rewritten as: r die — L— + Va1 + v, dt Va 2 (6) (3) From Fig.1 and Fig.3, the power balancing equations of the CHB-DSTATCOM can be derived as: V l — Cd (Vde1 Va1le — C1 , ( 0 dt 2 ) + Pr1 (7) Vn oh d V 2 —C2-(-d2 )+pr 2 (8) v_dc 2 dr 2 The behavior of the CHB-DSTATCOM is charaterized by the inductor current dynamics and the dc-link capacitor voltage dynamics. The power balance between the two H-bridge inverters depends on the dc-link voltages and the individual modulation signals. To better illustrate the mechanism of power exchange between the two modules, the phasor diagram of the output voltages and current of the CHB-DSTATCOM is given in Fig.4. In the analysis, it is assumed that vaN is calculated in such a way that lc is 90 degree phase-shifted with respect to vsa. The angles 01 and 02 represent the phase shifts of the output voltages va1 and va2 with respect to vsa, leading to a reactive power exchange between the individual H-bridge inverter with the grid. Figure 4. The phasor diagram of the voltages and current. 4 The Analysis of Power Balancing Mechanism Fig.3 shows the equivalent circuit of the multilevel CHB-DSTATCOM for the steady-state power balance analysis. In Fig.3, the individual H-bridge inverters are represented by AC voltage sources va1 and va2, which are derived as [2, 3]: Figure 5. The stable control area of the CHB-DSTATCOM. V In the phasorial diagram (Fig.4), the maximum output voltages in root-mean square (rms) values of each H-bridge can be calculated as: 4 _ 4 rvdc1 > va2m = Tt vdc2 (9) va1m dc1 a 2 m W2 W 2 The reactive power injected by each H-bridge inverter to the grid depends on the value of the capacitor voltage in the cell and the control signal modulated by each module. To ensure stable operation of the CHB-DSTATCOM, both cells must be utilized to synthesize the output voltage vaN. Fig.5 shows the red marked area the possible points to achieve the desired output voltage. Any point outside of this region makes the system unstable since the output voltage of the CHB-DSTATCOM cannot be modulated with those values of the dc-link capacitor voltages. Furthermore, as shown in Fig.5, the projections of va1 and va2 over vsa are always positive. Hence, the reactive powers in both converters are positive, indicating that both inverters of CHB-DSTATCOM inject reactive power to the grid simultaneously. Moreover, it is not possible to find a point where one of the cells injects reactive power and, at the same time, the other cell absorbs reactive power from the grid. (a) (b) Figure 6. The diagram of maximum and minimum reactive power limits. Fig.6 shows that, for a given total amount of reactive power to be supplied or absorbed by the H-bridge inverter, the reactive power sharing by each cell has to be between a minimum and maximum value to achieve a stable operation of the CHB-inverter. Fig.6(a) shows the minimum reactive power supplied by the first inverter, which corresponds to the minimum reachable length of the projection of va1 over vsa, represented by va1q,min. As the amount of reactive power supplied by the CHB-DSTATCOM is fixed, this value is related with the maximum reactive power that is supplied to the second cell, shown in Fig6(a) as va2qmax, which is the maximum reachable length of the projection of va2 over vsa. In the same way, the values for the maximum reactive power supplied by the first inverter va1q,max and the minimum reactive power supplied by the second inverter va2qmin can also be illustrated, as shown in Fig.6(b). 5 Controller Synthesis Methodologies Based on the analysis of the power balancing mechanism, the control block diagram can be synthesized, as shown in Fig.7. The control algorithm consists of five blocks, i.e., the reference current generation (RCG) unit, the phase-locked loop (PLL), the current loop controller (CC), the average dc-link voltage controller (AVC) and the dc voltage balancing controller (VBC). Further, the voltage balancing scheme based on the AVC and VBC control achieves equal reactive power sharing of the two cells by dynamically exchanging active power within the two inverters, and the outputs of the AVC controller (P1 and P2) are applied to the VBC controller to regulate the difference of dc voltages. Figure 7. The block diagram of the devised control algorithms. 5.1 Novel Phase-locked Loop (PLL) based on Adaptive Linear Neural Network (ADALINE) Figure 8. The proposed ADALINE-PLL (APLL) (a) overview of the APLL;(b)the block diagram for the hth order harmonic component Accurate synchronization of the multilevel CHB-DSTATCOM to the grid is vital to ensure its stable operation since the phase angle of the grid voltage was utilized to achieve the active and reactive power balancing for the individual H-bridge modules. Fig.8 shows the diagram of the ADALINE-based PLL for grid synchronization based on the least-mean square (LMS) estimation algorithm [4]. Here the mathematical formulation of the APLL is briefly outlined. An arbitrary grid voltage can be represented as: N vsa (0 = sinC^f + ft) + IX ^(»w + ft,) (10) n=2 where ) sin(&>0i + 6X) + Vl sin(A<91)cos(iy0i + 6'1) N + cos(«A6> +(ft, -nq\))sva\n(atf + (12) ii=2 N + Z {K sin(«A^ + {(pn - n(px)) cos[«(ft»0i + 6>)]} (13) From Eq.(13), the weights of the fundamental frequency component are denoted as con and con, hence the phase estimation error denoted by A0X can be regulated to zero by using a properly designed closed-loop control system, which resembles that of the existing grid synchronization schemes. As shown in Fig.8(a), the per unit representation of the weight co 12 is utilized as the input signal for the loop filter (LF) of the APLL, derived as [4]: con fc V1 sin(AÖ[) (14) ^V;2 sin2(Aöl) + V12 cos2(A^) = sin(A^) The weights updating process of the proposed APLL is similar to the adaptive linear neural network (ADALINE), which was based on the recursively searching the optimal point of the quadratic cost function, i.e., the least square (LS) error. Notably, the difference between the ADALINE algorithm and the proposed APLL is that, the frequency and phase angle signals utilized in the ADALINE weights updating process were assumed to be constant. However, in case of the APLL, the frequency and phase angle of the fundamental grid voltage is recursively updated by the loop filter (LF) and voltage controlled oscillator (VCO) [Fig.8], 5.2 Current Loop Controller Design From (12), it can be deduced that the original signal denoted by Eq.(10) can be regenerated by adjusting the coefficients Vncos(nA0i+((pn-n(pi)), Vnûn(nA0i+((pn-n(pi)) («=1, ..., N), even though the phase angle of the original signal is unknown. The weight vector W denotes the coefficients of the corresponding trigonometric functions. From the above defintion, the fundamental grid voltage can be expressed as: Y =WTX , where Y is the estimated output of the fundamental grid voltage by using the LMS-based weights estimation scheme. The vector W and X corresponding to the weight vector and the input vector, respectively, are represented as: W = [Vl cos(A0! ), Vl sin(A^ ),..., Vn cos(nA6l +((pn -rupj), Vn sin(/7AÖ, +((pn -n(px))] = [con,con,...,coiA,conl} X = [sin(£y0i + 6X ), cos(£y0i + 6X ),..., sin[n(û)0t + #,)], cos[«(ffi»0i + Ö,)]]1 Figure 9. The closed-loop block diagram of the current tracking loop. Fig.9 shows the discrete control diagram of the current loop controller for the CHB-DSTATCOM, where the transfer function C(z) represents proportional-integral (PI) regulator: C{z) = kp+^-\ (15) z~l where kp and ki denote the proportional and integral gains. The plant of the current controller is the coupling inductor, and Gp(s)=l/(L0s+R0), where L0 and R0 denote the nominal parameters. Eq.(6) can be discretized using the zero-order hold (ZOH) method, as: Gt(z, m) = Z l—e~ -G(s)e- z-l z\Gp(s) ^_smTs (16) TJb-z- Z 'i s J z-(l-R0T/L0) where 'm' denotes the equivalent sample of control delay. Neglecting the effect of the grid voltage and consider m=1, the open loop transfer function of the current loop controller can be derived as: cc kpTs GZn (z) = z - (l - (kT / kp)) L0 z(z -1)[z - (l- (RT / Lo))] (17) Hence, the closed-loop transfer function can be easily derived from Eq.(17). Open-Loop F'hase (deg) Figure 10. The open-loop Nichols diagram of the average voltage controller (AVC) when rc=100^s. 5.3 Voltage balancing controller design The voltage regulation loop includes the average voltage controller (AVC), which is designed to regulate the total active power balance between the CHB-DSTATCOM with the grid, and the voltage balancing controller (VBC), which is designed to regulate active power exchange between the two H-bridge inverters and achieve the equal reactive power sharing for the two cells. designed as kpVBC=0.1, ki,VBC=1.2. It shows that a gain margin (GM) of 36.5dB and a phase margin (PM) of 86.8 degree is achieved, thus the stability of the VBC loop is guaranteed. 6 Simulation Results and Discussions In order to verify the effectiveness of the devised control scheme, digital simulation using the Alternative Transient Program (ATP/EMTP) was performed and the results are evaluated. The parameters of the system are: Lg=50^H, Rg=20m^, L=1.5mH, R=50m^, and the nominal dc-link parameters are: Q=C2=2000^F, r1=r2=39000Q, sampling time 7>100^s, the grid voltage vsa=220V(rms), the target inverter dc-link voltage is 200V. -50- 0.00 0.03 0.06 0.09 0.12 [s] 0.15 (file CHB_APF_Var_2B_Aug18.pl4; x-var t) t: VDC1° t: VDC2a c:SA -MAA t: IS_REFx factors: 1111 1 offsets: 0 0 0 0 0 t: IS_ERR® v:VOU ■ 1 0.1 0 100 (a) WvVvWu "360 -315 -270 -225 -180 -135 -90 -45 0 Open-Loop Phase (deg) Figure 11. The open-loop Nichols diagram of the voltage balancing controller (VBC) when Tc=100^s. Fig.10 shows the open-loop Nichols diagram of the AVC, where the proportional -integral parameters are designed as kp AVC=0.6, kiAVC=12. It shows that a gain margin (GM) of 30.5dB and a phase margin (PM) of 83.6 degree is achieved. Hence the AVC loop is stable. Fig.11 shows the open-loop Nichols diagram of the VBC, where the proportional- integral parameters are 0.24 0.26 0.28 0.30 0.32 0.34 0.36 0.38 [s] 0.40 (file CHB_APF_Var_2B_Aug18.pl4; x-var t) t: VDClO t: VDC20 c:SA -MAA t: IS_REFX t: IS_ERF0 ■ fsctors: 11 1 1 1 1 0,1 ollsets: 0 0 0 0 0 0 100 (b) Figure 12. The simulation results of the CHB-DSTATCOM under nominal power-stage parameters. (a) The convergence process after system start-up; (b) Transient response from inductive mode to capactive mode. Fig.12 shows the time domain simulation results under nominal parameters, where the dc-link voltages, and the synthesized multilevel voltage, grid side current and its reference as well as the tracking error are illustrated. The convergence process after the system start-up is shown in Fig.12(a), where the initial dc-link voltages are set to 180 V and 220V, respectively. It can be observed that the dc-link voltages converge to the same value after a few cycles. And the grid-side current tracks its reference value with fast dynamics and the 150 100 0 tracking error approaches zero in the steady state. Fig.12(b) shows the dynamic response of the DSTATCOM when the reference current is undergone a transient change from inductive mode to capacitive mode. It can be observed that the stability of the dc-link voltages is preserved under the transient perturbations. And the grid current tracks its reference within two fundamental cycles, which demonstrates the validity of the control scheme. -500.00 0.03 0.06 0.09 0.12 [s] 0.15 (file CHB_APF_Var_2 B_Au g18.pl 4; x-var t) t: VDC1° t: 7002° c:SA -MAA t: IS_REFX factors: 1111 1 offsets: 0 0 0 0 0 t: IS_ERR* v:VOU ■ 1 0.1 0 100 (a) VWVWV -500.24 0.26 0.28 0.30 0.32 0.34 0.36 0.38 [s] 0.40 (file CHB_APF_Va r_2 B_Au g18.p 14; x-var t) t: VDC10 t: 7002° c:SA -MAA t: IS_REF* factors: 1111 1 offsets: 0 0 0 0 0 t: IS_ERR" 1 0 v:VOUT -0.1 100 (b) Figure 13. The simulation results of the CHB-DSTATCOM when Rdc2=100fi and Cdc2=4000^F. (a) The convergence process after system start-up; (b) Transient response from inductive mode to capacitive mode. Fig.13 shows the scenario when the resistor and capacitor value of the second inverter are changed as Cdc2=4000^F, Rdc2=100Q while other parameters remain unchanged. It shows that the stability of the DSTATCOM is ensured and all the waveforms resemble those in Fig.12. However, the dc-link voltage ripple of the second inverter is much less than the first one. And the tracking error of the grid side current is higher in the steady state compared to the case in Fig.12. Besides, a settling time of two cycles under transient perturbation of the reference current can also be observed. Fig.13 imply that the devised control scheme is quite robustness under power stage parameter variations since the dc-link voltage stability is ensured and the sinusoidal waveform is obtained in the grid side current, with a total harmonic distortion of less than 5% for all these scenarios. It can be inferred that the devised control scheme would produce robust control effect for the CHB-DSTATCOM. Normally, the power-stage parameters deviation is quite small hence a sufficient stability margin can be achieved. 7 Conclusions This paper presents an effective control scheme for the cascaded H-bridge (CHB) DSTATCOM. The principle of multilevel carrier-shifted pulse-width modulation (CSPWM) and the mechanism of power balancing among individual H-bridges inverters are presented. The controller synthesis of the CHB-DSTATCOM is provided, which consists of current tracking controller design, the average dc-link voltage controller (AVC) and voltage balancing controller (VBC), which are devised from the devised power balance mechanism. The validity of the devised control scheme is validated by the simulation results from the alternative transient program (ATP/EMTP). references [1] Han Y., Xu L., Yao G., Zhou L., Khan MM, Chen C., Flicker mitigation of arc furnace load using modified p-q-r method, Przeglad Elektrot., vol.85, no.1,pp. 225-229, 2009. [2] M. Malinowski, K. Gopakumar, J. Rodriguez, M. A. Pérez, A survey on cascaded multilevel inverters, IEEE Trans. Ind. Electron., vol.57, no.7, pp.2197-2206, Jul. 2010. [3] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, B. Wu, J. Rodriguez, M. A. Perez, J. I. Leon, Recent advances and industrial applications of multilevel converters, IEEE Trans. Ind. Electron., vol.57, no.8, pp.2553-2580, Aug.2010. [4] Y. Han, L. Xu, M. M. Khan, G. Yao, L. Zhou, C. Chen, A novel synchronization scheme for grid-connected converters by using adaptive linear optimal filter based PLL (ALOF-PLL), Simulation Modeling Practice and Theory, vol.17, no.7, pp.1299-1345, 2009. [5] Han Y., Xu L., Yao G., Zhou L., Khan MM, Chen C., StateSpace Averaging (SSA) Technique for Modeling of the Cascaded H-Bridge Multilevel DSTATCOMs and Active Filters, International Review of Electrical Engineering-IREE, vol.4, n.5, pp.744-760, 2010. Lin Xu received the Ph.D. degree in electrical engineering from Shanghai JiaoTong University (SJTU), Shanghai, China, in 2011. Currently, she is working at Sichuan Electric Power Research Institute, Chengdu, China. Her research interests include power system analysis and real-time digital simulator (RTDS), flexible Ac transmission systems (FACTS), such as TCSCs, STATCOMs, and power quality conditioners (DVRs, APFs). Yang Han (S'08-M'10) received the B. E. degree in electrical engineering from University of Electronic Science and Technology of China (UESTC), Chengdu, P. R. China. He received the Ph. D. degree in electrical engineering from Shanghai JiaoTong University (SJTU), Shanghai, China, in 2010. Currently, he is with the Univerity of Electronic Science and Technology of China (UESTC), Chengdu, China. His research interests include power system analysis and simulation, power quality conditioners, voltage source inverters, (STATCOMs) and active power filters.