247
Original scientific paper
 MIDEM Society
An Improved Low Phase Noise LC-VCO with Wide 
Frequency Tuning Range Used in CPPLL
Xiaofeng Wang, Zhiyu Wang, Haoming Li, Rongqian Tian, Jiarui Liu, and Faxin Yu
School of Aeronautics and Astronautics, Zhejiang University, Hangzhou, China
Abstract: Based on TSMC 0.18μm CMOS process, a complementary cross-coupled differential LC voltage controlled oscillator (LC-VCO) 
used in charge pump phase-locked loop (CPPLL) frequency synthesizer for satellite receiver with low phase noise and wide frequency 
tuning range is designed and implemented. The VCO adopts self-bias structure to remove flicker noise produced by tail current. 
Programmable LC tanks are introduced at the common source of cross-couple transistors to eliminate second harmonics of resonant 
frequency. Distributed biasing is applied for a wider linear tuning range. An optimized switch is proposed to lower on-resistance. The 
measured results show that the VCO exhibits a 53.8% tuning range from 1.02GHz to 1.77GHz. From the carrier frequency of 1.4 GHz, 
the phase noise of the VCO can reach -131.2 dBc/Hz at 1MHz offset. The core circuit consumes 7.7mA with 1.8V supply voltage.
Keywords: low phase noise; wide tuning range; distributed biasing; optimized switch
Izboljšan LC-VCO z nizkim faznim šumom in 
širokim področjem nastavljanja frekvence za 
uporabo v PLL s črpalko nabojev
Izvleček: Razvit in uporabljen je bil komplementarni sklopljen difencialni LC napetostno krmiljen oscilator (LC-VCO) za uporabo 
v frekvenčnem sintetizatorju s fazno-skelnjeno zanko (PLL) s črpalko nabojev, namenjen uporabi v satelitskih sprejemnikih z 
nizkim faznim šumom in širokim področjem nastavljanja frekvenc. Izveden je v TSMC 0.18 um CMOS tehnologiji. VCO uporablja 
samonapajalno strukturo za izničenje šuma 1/f, ki bi ga povzročal tokovni vir. Za izločanje drugega harmonika frekvence so uvedene 
nastavljive LC zapore na skupnem viru napajanja križno sklopljenih tranzistorjev. Za širšo območje nastavljanja je uporabljeno 
porazdeljeno napajanje uglaševalnih varaktorjev. Rezultati izkazujejo 53.8% nastavljivo območje VCOja med 1.02 GHz in 1.77 GHz. Pri 
nosilni frekvenci 1.4 GHz in odmiku 1 MHz lahko fazni šum VCO doseže -131.2 dBc/Hz. Pri napajalni napetosti 1.8 V jedro vezja porablja 
7.7 mA.GHz.   
Ključne besede: nizek fazni šum; široko območje nastavljanja; porazdeljeno napajanje; optimizirano stikalo
* Corresponding Author’s e-mail: jrliu@zju.edu.cn
Journal of Microelectronics, 
Electronic Components and Materials
Vol. 47, No. 4(2017), 247 – 253
1 Introduction
Frequency modulation is widely used in communica-
tion system especially for long distance communica-
tion. A wide utilization of frequency synthesizer in the 
RF system makes it possible to generate an accurate 
frequency signal for frequency modulation [1]. In the 
RF system, noise produced by frequency synthesizer di-
rectly deteriorates the overall noise performance of the 
system [2]. Meanwhile, the VCO is one of the major con-
tributors of the out-of-band noise in a PLL frequency 
synthesizer [3]. Thus, to design a low phase noise VCO is 
necessary and significant for a high performance com-
munication system, which is a challenge for us in con-
sideration of tuning range, power consumption and 
other characteristics.
With a mature understanding of phase noise mecha-
nism [4]-[6], many attempts to optimize phase noise 
of VCO have been made in recent years. In reference 
[7], switchable cross-coupled pairs are used for lower 
transconductance and thereby improve 1/f 3 noise. 
However, as a result, the complexity of the timing logic 
is inevitably increased. In order to prevent the Q-factor 
degradation of resonant tanks in VCO, MOS switches 
248
X. Wang et al; Informacije Midem, Vol. 47, No. 4(2017), 247 – 253
featuring high off-on resistance ratio (ROFF/RON) are 
used, and transistors with large gate width are intro-
duced to achieve a sufficiently low RON. However, the 
COFF associated with such wide transistors will cause se-
rious performance degradation [8, 9].
This paper introduce how VCO contribute phase noise 
to CPPLL, presents a complementary cross-coupled dif-
ferential LC-VCO that can achieve low phase noise and 
large frequency tuning range. Self-bias structure is ap-
plied to remove flicker noise produced by tail current. 
Programmable LC tanks are introduced at the source of 
cross-coupled transistors to eliminate second harmon-
ics of resonant frequency. Distributed biasing is adopt-
ed to widen the linear tuning range of every selected 
band. The switches used in the design have been op-
timized to enhance the Q-factor. The presented VCO 
is fabricated using TSMC 0.18μm CMOS technology, 
measurement of which is performed for validation.
2 CPPLL noise analysis
We choose CPPLL rather than others for its stability and 
larger acquisition range. A brief block diagram of the 
CPPLL is shown in Fig. 1. Phase/frequency detectors 
(PFD) sense phase and frequency differences between 
reference clock signal and output of divider. Charge 
pump sinks or sources current for a limited period of 
time according to the voltage produced by the pre-
vious PFD. The loop filter (consisting of R1, C1 and C2) 
following CP produces voltage which controls VCO. 
The low dropout regulator (LDO) supplies for the VCO. 
The frequency divider (FD) between VCO output and 
PFD input makes a feed-back loop to ensure that out-
put signal frequency is independent of process, supply 
voltage, temperature and other interferences.
Figure 1: CPPLL block diagram.
To formulate the CPPLL output phase noise contribut-
ed by VCO, we need to derive the transfer function from 
the VCO phase to the CPPLL output phase. Although 
CPPLL is a nonlinear system, in the vicinity of lock state 
we can make a linear approximation in phase domain 
for intuitive understanding. A linear model is construct-
ed in Fig. 2, where 
 p
1
1 2
1 1//
2π
I R
sC sC
 +   , 
 VCOK
s  and 
 1
N  repre-
sent CP, VCO and FD respectively.
Figure 2: Phase-domain linear model for deriving 
VCO’s effect on CPPLL phase noise
In order to analyze VCO’s effect, we make Fin = 0  to 
signify that reference clock signal is noiseless. Starting 
from the output, we have:
 out p VCO
1 VCO  out
1 2
1 1[ // ] = 
2π
I KR
N sC sC s
φ φ φ − + ⋅ +  
 (1)
Equation （1） allows us to derive phase transfer func-
tion from VCO to PLL output as :
 1 23 2
out 1 1 2
1 2 p VCO p VCOVCO 3 2
1 1 2 2 1 1 2
(s) 1 1
2π 2π
C Cs s
R C C
C C I K I Ks s s
R C C N C N R C C
φ
φ
++ ⋅
= ++ ⋅ + ⋅ ⋅ + ⋅
  (2)
The transfer function contains two zeros at the origin 
and one zero near origin, three poles on the right of 
the zeros, exhibiting a high-pass behavior. The VCO 
phase noise is shaped by the transfer function. It can 
be proved that the phase noise out of loop bandwidth 
follows VCO’s phase noise [3].
Taking other noise sources (reference clock, PFD, CP, FD 
and etc.) into consideration, we can make a conclusion 
that PLL’s output phase noise measured at high offset 
frequencies is worse than VCO’s.
3 Circuit Design
The theories to derive the phase noise of VCO have 
been researched for many years. Based on the deriva-
tion in [10], the theory proposed by D.B. Leeson [4], 
which can make a qualitative prediction about the 
phase noise is described in equation (3):
 32O{ } 10 log 1+ 1+ 1Hz          [dBc/Hz]  
2 2
f
s L
fFkTL
P Q f
ff f
1/
   ∆    ∆ = ⋅ ⋅ ⋅ ⋅     ∆ ∆      
 (3)
where F is the noise figure of the active device used 
under large signal conditions in this design, k is Boltz-
mann’s constant in Joules/Kelvin, T is the temperature 
in Kelvin, Ps is the average power dissipated in the resis-
tive part of the tank in Watt, fO is the carrier frequency 
249
(Hz), QL is the effective quality factor of the tank, ∆f is 
the offset frequency (Hz) from the carrier and  3ff1/∆  is 
the frequency (Hz) of the corner between the 1/f3 and 
1/f2 regions. The corner frequency of the semiconduc-
tor process we used in the design is about 20 kHz, 
which means  3ff1/∆   is about 20 kHz.  
In this design, guided by equation (3), the LC-VCO with 
optimized phase noise is presented, the core schematic 
of which is shown in Fig. 3.
Figure 3: The proposed VCO core schematic.
There is no current source in the schematic, so the flick-
er noise due to current source can be removed totally. 
A complementary cross-coupled structure is adopted 
rather than only a cross-coupled structure because the 
structure can produce twice the voltage swing for a 
given current and inductor design, which can reduce 
phase noise according to equation (3). The direct-cur-
rent operating points are determined by diode-con-
nected MOS transistors between power and ground 
provided by LDO which can reduce VCO’s sensitivity to 
supply voltage. MOS transistors here are used to work 
as negative resistor, cancelling loss in the LC tank due 
to parasitic resistance of inductor, capacitor and others. 
In this design, the parameters of PMOS and NMOS are 
set to produced symmetric output swing by simulation 
iteration operation for a given frequency range, which 
benefits phase noise optimization [11]. The parameter 
of main components in VCO is shown in Table 1. 
Table 1: Parameters of main components in VCO 
Components Parameter Value
L1 Inductance[nH] 2.95
L2(L3) Inductance[nH] 1.69
Mn1(Mn2) W/L[μm/μm] 32*(2/0.2)
Mp1(Mp2) W/L[μm/μm] 32*(6/0.2)
There are two 7-bit binary-weighted switched capaci-
tor arrays controlled by the same digital codes, D<6:0>, 
in the proposed topology. For a compromise of the 
linearity and layout area, the codes are implemented 
with a segmented architecture, in which the 2 LSBs are 
implemented using a binary architecture while the 5 
MSBs are implemented in a unary way. The capacitor 
array in parallel with L1 is proposed to extend the tun-
ing range instead of increasing VCO gain, which can 
realize coarse tuning. The other connected between 
nodes P and N is in parallel with L2 and L3, whose pur-
pose is to compose a narrow band circuit for resonance 
at second harmonic, preventing the degradation of the 
Q-factor of the tank when the transistors operate in the 
triode region [12]. We choose programmable switched 
capacitors between nodes P and N rather than a fixed 
capacitor because we can choose appropriate resonant 
frequency according to the band selection.
In order to perform the fine tuning of VCO with a wide 
linear range, distributed MOS varactor biasing is ap-
plied [13].The varactor we used in the design is accu-
mulation-mode MOS varactor, which is shown in Fig. 
4 (a). This structure is obtained by placing an NMOS 
transistor inside an n-well. If VG<VS, then electrons in 
the n-well are repelled from silicon/oxide interface and 
a depletion region is formed. Under this condition, the 
capacitance seen from the gate is given by the series 
combination of the oxide and depletion capacitance. 
As VG exceeds VS, the interface attracts electrons from 
the n+ source/drain terminals, creating a conduction 
channel. As a result, the total capacitance seen from 
the gate rises to that of the oxide. The C/V character-
istics of the varactor is shown in Fig. 4 (b). The linear 
range of the structure is limited. To solve this problem, 
we shunt two varactors in parallel with two different 
voltage bias, VBH and VBL, which is shown in Fig. 3. 
The C/V characteristics of distributed biasing varac-
tors is shown in Fig. 5. Compared to the conventional 
structure whose varactor is biased by a single reference 
voltage, this design can achieve almost twice linear 
range. As a consequence, we can enlarge tuning range 
of every selected band and reduce the VCO gain for a 
given frequency range, which makes a good trade-off 
between phase noise and tuning range.
X. Wang et al; Informacije Midem, Vol. 47, No. 4(2017), 247 – 253
250
Figure 4: (a) MOS varactor, (b) resulting C/V character-
istic of the varactor
Figure 5: C/V characteristic of the varactors with dis-
tributed biasing
Another issue should be paid attention to is the design 
of the switch used in capacitor arrays, which concerns 
the Q-factor of the LC tank. We hope the switch is ideal, 
but the parasitic effect and voltage swing between 
the switch make it hard to implement an ideal switch. 
There is a trade-off in the design of switch size. To real-
ize high quality of capacitor when the switch is on, we 
need large size switch to minimize the on-resistance. 
To minimize parasitic capacitance of the switch when 
the switch is off, we need to design small size switch 
MOS transistor to degrade Cgs and Cgd. A conventional 
structure is shown in Fig. 6 (a), where the on-resistance 
is introduced by MOS switch. Ideally, the switch transis-
tor is in deep triode region when the switch is on. The 
resistor is equal to
 
on
n ox GS TH
1
( )
R WC V V
L
µ
=
−
   (4)
However, the voltage swing appearing at source of the 
MOS switch may drive it out of the region. As a result, 
the on-resistance varies along with the output volt-
age swing of the VCO, which will deteriorate the phase 
noise of the VCO. To solve the problem, an optimized 
structure is used in this design as described in Fig. 6 (b). 
Since the structure is symmetrical with differential volt-
age swing, node A is ac ground here. When the switch 
is on, the common source of the two transistor experi-
ences little voltage swing and the on-resistance almost 
keeps a constant consequently. Additionally, when 
the switch is off, the optimized structure is switched 
off more thoroughly and introduces almost half para-
sitic capacitance if the switch sizes are equal in the two 
structures.
a)
b)
Figure 6: (a) a conventional switch (b) an optimized 
switch
4 Implementation and Measurements
This proposed low phase noise VCO is integrated in a 
receiver which is fabricated using TSMC 0.18μm CMOS 
technology. In our frequency synthesizer, the VCO out-
put is divided by a divide-by-2 quadrature frequency 
divider to generate quadrature local oscillating (LO) 
a)
b)
X. Wang et al; Informacije Midem, Vol. 47, No. 4(2017), 247 – 253
251
signal for quadrature down conversion. After the divid-
er, an output buffer is adopted for testing. According 
to the system requirement, the loop bandwidth of the 
frequency synthesizer is set to 100 kHz. Fig. 7 shows a 
micrograph of the proposed VCO, occupying an area of 
820*1080μm2.
Figure 7: Micrograph of proposed VCO.
An Agilent E5052B signal source analyzer is used to 
measure the synthesizer parameters in the test. The f -V 
tuning characteristic of the VCO is shown in Fig. 9 (a). 
The VCO achieves a tuning range of 53.8% from 1.02 
GHz to 1.77 GHz. Fig. 9 (b) shows the phase noise meas-
ured at the carrier frequency of 700 MHz. The measured 
result is -104.3 dBc/Hz at 100-kHz offset and -135.6 dBc/
Hz at 1-MHz offset respectively. The VCO phase noise is 
-98.3 dBc/Hz at 100-kHz and -129.6 dBc/Hz at 1-MHz 
offset respectively after adding 6 dB, while consuming 
current of 7.7 mA from a supply voltage of 1.8V. Fig. 9 
(c) shows phase noise performance across the VCO fre-
quency range at 1 MHz offset, which confirms the VCO 
has a good noise performance in the entire frequency 
range. In contrast, Fig. 8 shows the simulation result 
of the free running VCO at the carrier frequency of 1.4 
GHz, which is close to the test result at 1 MHz offset.
A figure-of-merit (FOM) is employed to evaluate the 
four performance parameters of the VCO: frequency, 
phase noise, power consumption and frequency tun-
ing range [14], which can be expressed as:
 o
TFOM =20log 10log PN+20log(FTR/10)
1mW
f P
f
− −
∆
 (5)
 max min cFTR=[( - )/ ] 100%f f f ×    (6)
Where fo is the oscillation frequency, fmax, fmin are the 
maximal, minimal operation frequency, respectively, fc 
is the center oscillation frequency, ∆f is the offset fre-
quency, P is power dissipation valued in mW, and PN is 
the phase noise valued in dBc/Hz.
Figure 8: free running VCO output phase noise simula-
tion result at 1.4 GHz
Based on the measured results above, Table II sum-
marizes the measured performance comparison of 
the VCO in this work with other recent state-of-the-art 
VCOs in published literatures. The wide frequency tun-
ing range with the proposed scheme shows better per-
formance than the LC-VCO in [8] and the two LC-VCOs 
in [9] which have ordinary phase noise performance at 
higher oscillation frequency with higher power con-
sumption. The LC-VCO reported in [7] has lower power 
Table 2: Performance comparison CMOS VCO
Ref CMOS process (nm) Power (mW)
Tuning range 
(GHz) fc (GHz) Phase noise (dBc/Hz) FoMT (dBc/Hz)
[7] 65 8 1.6~2.6 2.1 -124@1MHz 195.0
[8] 90 23 2.55~4.084.9~5.75 2.1
-126@1MHz
-125@1MHz
192.1
181.9
[9] 180 18 1.35~2.052.05~2.75
1.7
2.4
-122@1MHz
-119.5@1MHz
186.3
183.8
This work 180 14 1.02~1.77 1.4 -129.6@1MHz 195.7
X. Wang et al; Informacije Midem, Vol. 47, No. 4(2017), 247 – 253
252
consumption and ordinary phase noise performance 
at higher oscillation frequency, but utilizing a more ex-
pensive 65nm process.
5 Conclusion
In this letter, a wide-tuning-range low-phase-noise VCO 
is reported. An optimized switch structure and pro-
grammable LC-tanks are applied in the self-bias struc-
ture of VCO to optimize noise performance. The perfor-
mance outcomes well validate the effectiveness of the 
topologies and methodologies used in the design. The 
fabricated VCO exhibits a tuning range of 53.8% from 
1.02 GHz to 1.77 GHz, a phase noise of -129.6 dBc/Hz 
at 1 MHz offset from the carrier frequency of 1.4 GHz. 
The measured results show a wide tuning range, good 
noise performance of the presented LC-VCO.
6 Acknowledgment
This work was supported by the National Natural Sci-
ence Foundation of China under Grant 61401395 
and 61604128, the Scientific Research Fund of Zhe-
jiang Provincial Education Department under Grant 
Y201533913, and the Fundamental Research Funds 
for the Central Universities under Grant 2016QNA4025 
and 2017QN81002.
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Figure 9: (a) f-V tuning characteristic refers to the 7-bit 
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Arrived: 27. 07. 2017
Accepted: 06. 11. 2017
X. Wang et al; Informacije Midem, Vol. 47, No. 4(2017), 247 – 253