BVceo engineering in SOI LBT STRUCTURE WITH TOP
CONTACTED BASE
Marko Koričic, Tomislav Suligoj
Department of Electronics, Microelectronics, Computing and Intelligent Systems, Faculty of Electrical Engineering and Computing, University of Zagreb,
Zagreb, Croatia
Key words: SOI, lateral bipolar transistor, extrinsic base, charge sharing effect, common-emitter breakdown voltage, cutoff frequency
Abstract: Properties of SOI LBT structure with the base contact on top are analyzed by device simulations. The effect of the extrinsic base width on the common-emitter breakdown voltage (BVCEO) is studied in detail. Charge sharing between extrinsic and intrinsic base acceptors can be controlled to achieve fully depleted collector. Shielding of the electric field across intrinsic junction by the extrinsic base electric field can be used to limit the peak value of the electric field along the current path in the collector-base depletion region and to increase the value of BVCEO. Two peaks of electric field appear in the base-collector depletion region - the first one at the intrinsic junction and the second in the drift region toward extrinsic collector. The area in which breakdown occurs depends on the value of the electric field in two peaks, which can be controlled by the extrinsic base width (wbex,).
Inženiring parametra BVCEO v SOI LBT tranzistorski strukturi z
baznim kontaktom na vrhu
Kjučne besede: SOI, bipolarni tranzistor, ekstrinzična baza, deljenje naboja, prebojna napetost s skupnim emiterjem, mejna frekvenca
Izvleček: Simulirali smo lastnosti SOI LBT tranzistorske strukture z baznim kontaktom na vrhu. Podrobno smo proučili vpliv širine ekstrinzične baze na prebojno napetost tranzistorja, BVCEO Kontroliramo lahko porazdelitev naboja akceptorjev intrinzične in ekstrinzične baze, da dosežemo popolnoma osiromašen kolektor. Senčenje električnega polja ekstrinzične baze čez intrinzičen spoj lahko uporabimo za omejitev najvišje vrednosti električnega polja vzdolž tokovne poti v osiromašenem področju spoja kolektor-baza, kakor tudi za povečanje prebojne napetosti BVCEO Pojavita se dva vrhova električnega polja v osiromašenem področju spoja baza-kolektor. Področje, kjer pride do preboja, je odvisno od vrednosti električnega polja teh dveh vrhov, ki ju lahko kontroliramo s širino baze, wbex,.
1. Introduction
Recently, the extremely-thin silicon-on-insulator (SOI) has been marked as a potential CMOS technology for 22 nm node and below, /1/. Small parasitic capacitances inherent for SOI technology, good electrostatic behavior and low variability due to undoped channel promise a good solution for short channel effects (SCE) and scaling properties of such CMOS. This trend in IC industry will force SOI wafer manufacturers to improve wafer production in terms of lower defect density and reduced cost. It can be expected that wafer cost of not only ultra-thin-film SOI, but also thicker film SOI, will be reduced in the near future. In the past years, thin-film SOI technology has been proposed as a potential technology for radio-frequency (RF) system-on-chip (SoC) integration /2/, /3/. Excellent characteristics regarding the device isolation and small parasitic capacitances, as well as higher quality passives compared to bulk-silicon technologies, make this technology appropriate for low-power battery supplied applications like mobile phones, GPS, WiFi, etc. In order to achieve SoC level of integration for RF applications, bipolar transistors are desired in a technology platform due to their superior analog performance such as lower noise figure and higher gain. Vertical bipolar transistors in SOI may become prohibitively expensive due to more
complex process /4/, which in addition to the higher cost of SOI wafers may result in a technology that is not economically viable. On the other hand, lateral bipolar transistors (LBTs) in SOI can be fabricated in a process that is less complex with the significant cost reduction compared to the vertical bipolar transistors, either in bulk or SOI substrates. It can be expected that cost of technology will be reduced further with the advance in SOI wafer manufacturing. Due to the nature of intrinsic base fabrication, which relies on the spacer technique and lateral redistribution of impurities, cutoff frequencies (fT) of SOI LBTs above 20 GHz were not reported. The only LBT with reported state-of-the-art electrical performance is Horizontal Current Bipolar Transistor (HCBT) but it is fabricated in bulk-silicon wafers /5/. However, reported AC performance of SOI LBTs is still suitable for applications in microwave frequency range including the most important wireless application standards. Several LBT structures have been proposed so far and can be roughly categorized with respect to the base contact position as laterally contacted /6/, /7/, /8/ and top-contacted structures /2/, /3/, /9/, /10/. One benefit of placing the base contact on the top is that transistor length can be increased in the third dimension by the mask design if higher current drive is needed in the applications. In the case of laterally contacted base, i.e. two-sided base contact, transistor
operating current cannot be increased by increasing the emitter length, because the intrinsic base resistance would be increased. The ultimate result is that AC performance of the transistor is degraded through the reduction of maximum oscillation frequency (fma,). To overcome this issue, transistors of unit emitter size can be connected in parallel, which gives less flexibility in the circuit design. In order to achieve a SoC level of integration, transistors with different values of breakdown voltages should be available in a certain technology. In standard vertical transistors it is accomplished by the different parameters of the selectively implanted collector, which implies the usage of additional lithographic masks and results in an increased process complexity and ultimately higher cost of technology. On the other hand, in LBT structures with top contacted base, different values of breakdown voltages can be obtained by the mask design and the control of the width of the base contact region, i.e. extrinsic base width (wbex,), without any increase in the process complexity. In this paper, design tradeoff between cutoff frequency (fj) and common-emitter breakdown voltage (BVCEO), specific for SOI LBT structure with top-contacted base are analyzed by the device simulations. Physical mechanisms in the extrinsic base effect on transistor's breakdown voltage are analyzed in detail.
2. Simulation structure
A typical LBT structure such as the one reported in /2/ is analyzed by device simulation in MEDICI. The highest maximum oscillation frequency (fmax) and common emitter current gain (ß) as well as the lowest base resistance (Rg) among all LBTs are reported for this structure. Cross-section of the device with marked geometrical parameters and the doping profile of the intrinsic transistor are shown in Fig. 1 and 2, respectively. Technological parameters are summarized in Table 1. Emitter height (hE) is determined by the thickness of the silicon on insulator film and the small link-base region (lb), which is defined during the extrinsic
Table 1. Jechnological and geometrical parameters of the soi lbt simulation structure
0.0 0.1 0.2 Distance, ^m
Fig. 2. Doping profile of the intrinsic transistor.
base polysilicon overetching. In this way, the extrinsic base profile, which is diffused from the extrinsic-base polysilicon, does not overlap the upper edge of the emitter, which could reduce the current gain and degrade base current ideality at lower base-emitter voltages due to the high-field effects and band to band tunneling /11/. Intrinsic transistor is formed by ion implantation of the intrinsic base and emitter, which are separated by the spacer formed on the sidewall defined during the extrinsic base polysilicon etching. Later on in the process, dopants are laterally diffused to form the final intrinsic transistor profile. This represents the fundamental limit on the control of the intrinsic base profile and basewidths cannot be scaled below 100 nm as it is routinely done in standard vertical bipolar transistors. Since the emitter region is not implemented in polysilicon, the distance between emitter contact and the base-emitter junction should be larger than the minority hole diffusion length in order to obtain smaller associated component of the base current and the larger current gain. The minimum distance between highly doped n+ collector contact region, i.e. extrinsic collector, and the p+ extrinsic base is limited by breakdown voltages of the transistor. Extrinsic base polysilicon should be highly doped and thick enough to suppress electron diffusion to the extrinsic base region, which could
NABext, (cm-3)	Ndc, (cm-3)	(cm-3)	^bex,, (nm)	lb, (nm)	hE, (nm)	dpoly, (nm)	dE (nm)	dc (nm)	dOX (nm)		■ 1 ' 1	
										10^		- - Simulated ;i -Simulated ;J
2-1020	1.5-1017	1.8-1020	500	70	120	200	300	500	300	lo"		: Measured ;J
										lO-®		" Measured ll
						do				1		
BOX
B
p* ext. base poly


n
p intr.base
collector contact region
I
a O
Fig. 1. Cross-section of the device simulation structure with marked geometrical parameters.
0.2	0.4	0.6	0.8	1.0
Base-Emitter Voitage , V
Fig. 3. Simulated Gummel characteristics. Measured data from /2/ is included for reference.
increase the base current and degrade the current gain (ß). This structure has the base contact placed on the top and the base current is supplied only from one direction. Therefore, one-sided base contact is formed, which is not beneficial regarding the value of the base resistance (Rg). Nevertheless, the smallest RB and the highest fmax value among SOI LBTs are reported for this structure, owing to a small thickness of SOI film and silicided base contact, which results in a small intrinsic component of the base resistance and a small contact resistance, respectively.
3. Simulation of electrical characteristics
Simulated Gummel characteristics of the transistor are presented in Fig. 3. Measured data is taken from /2/ for the reference. Doping profile in the intrinsic base is adjusted to get reasonable fit of the collector current. Summary of the simulated characteristics is given in Table 2.
Table 2. Summary of the simulated electrical characteristics
ß	fj, (GHz)	fmax, (GHz)	RB, (")	Cbc, (fF)
83	12.7	67.1	250	1.55
3.1. Analysis of common emitter breakdown voltage and cutoff frequency
Tradeoff between speed and the breakdown voltage in bipolar transistors is well known. In order to suppress base widening at higher collector currents (i.e. Kirk effect) and to increase the cutoff frequency of the transistor (fj), collector doping concentrations are increased, which results in a higher electric field in the base collector depletion region and lower value of breakdown voltages. Common emitter breakdown voltage (BVCEO) is more important since it is typically 2 to 3 times lower than the common base breakdown voltage (BVcbo) and is responsible for evaluation of transistor's safe operating area. The tradeoff is usually evaluated in terms of (fjBVCEO) product, bounded by the Johnson's limit /12/, which approximately equals 200 GHzV and 400 GHzV for implanted base and SiGe epi-base transistors, respectively /13/. Cutoff frequency (fj) and common emitter breakdown voltage (BVCEO) are simulated in MEDICI. fj is calculated from AC analysis. Y-parameters are simulated and converted to ^-parameters. fj is determined as the frequency at which, h21 falls to unity. For evaluation of the common emitter breakdown voltage, base current reversal method in forced VBE measurement is used /13/. Base-emitter voltage (VBE) is set to 0.7 V and collector-emitter voltage (VCE) is swept. BVCEO is determined as the VCE at which the base current changes the sign, i.e. turns from positive to negative. Non-local impact ionization model based on lucky electron model with hard threshold energy /14/ is used in simulations. All BVCEO simulations are done with standard drift-diffusion model and the effects of self-heating are not considered. However, simulations
are done for VBE of 0.7 V at which collector current is small and no substantial self-heating is expected.
The unique geometry of LBTs with the base contact placed on the top results in a collector region which is surrounded by the extrinsic base from the top, the intrinsic base from one side and buried oxide from the bottom (Fig. 1). In the forward active mode of transistor operation, the base-collector junction is reversely polarized and the electric field is supported by the fixed charge in the depletion region. In the case of top contacted structure, there are two components of the electric field. Vertical component originates from the electric field lines which are terminated between collector donor charge and the extrinsic base acceptors, whereas horizontal component originates from the electric field lines which are terminated on the intrinsic base acceptors. Total amount of the collector charge is limited by the donor concentration in the collector and the thickness of the silicon on insulator film. This two-dimensional effect of collector charge sharing between extrinsic and intrinsic base acceptors, i.e. vertical and horizontal component of the electric field can be controlled in the way that collector becomes fully depleted and breakdown voltage improved for transistors with wider extrinsic base (wbext).
At first, dependence of the BVCEO on extrinsic base width (wbext) is investigated. Simulations are done for the structures with different collector concentrations (NDC). Intrinsic base profile is kept the same in the simulations, meaning that intrinsic base is narrower and current gain (ß) slightly higher for transistors with higher collector concentration. Results are shown in Fig. 4. For the doping concentrations up to 2.5-1017 cm-3 the effect of the BVCEO improvement can be observed if the extrinsic base width (w^^^f) is increased. BVceo value saturates for extrinsic base width larger than 0.8 Mm. Therefore, engineering of the breakdown voltage by the mask design is possible for extrinsic base widths up to 0.8 Mm. For collector doping concentrations larger than 2.5-1017 cm-3, breakdown voltages are sharply reduced and
o
Ul 0)
14 12 10 8 6 4 2
cm	cm —^—N^-3x^0 cm"
-Cr N ^^,=8x10cm -Q- N^=2x1 o" om-^ -o- w^=4x10 " cm" -^-N =10"cm^	=2.5x10"cm-^ -^-N =5x10" cm-
g^o-o-o-o-o.
0.0
0.5	1.0	1.5
Extrinsic Base Width, ^m
2.0
Fig. 4. Dependence of BVCEO on the extrinsic base width (wbex,) for different collector concentrations.
a)
Va,=3 V
1x10
E
-w" C
S
a
u «
«0
5x10
2	4
Collector-Emitter Voltage, V
b)
2	4	6
Collector-Emitter Voltage, V
Fig. 5. Simulation of BVCEO dependence on wbext for: a) Ndc=2.5^1017 ctTO-3, b) NDC=1.5^1017 cm3.
cannot be improved by extending BV^.^^ simulations for collector concentrations of 2.5-1017 and 1.5-1017 cm-3 are shown in Fig. 5.a and 5.b, respectively. For collector concentration of 2.5-1017 cm-3 a plateau in the base current is observed for transistors with wider extrinsic base. These characteristics indicate that electric field has two peak values in the base-collector depletion region. The first peak appears at the intrinsic base-collector junction and approaches the value of the critical electric field at V^,^ around 3 V. Weak avalanche starts and generated holes drift to the base side reducing the base current. However, peak electric field at the intrinsic base-collector junction is not increased for V^.,, larger than 3 V and impact ionization is limited as indicated by the plateau in the characteristics for voltages between 3 and 7 V. This is explained by the full depletion of the collector region and the extrinsic base shielding effect. Impact ionization rate in the transistor for of 3 and 9 V is shown in Fig. 6.a and 6.b, respectively. For Vce=3 V, just before full depletion of the collector, maximum impact ionization rate occurs at the intrinsic base-collector junction. When is further increased up to 9 V, another region with high impact ionization rate appears
E		extrinsic base	depletion region edge 1	C	Imp actlofiization Signed Lpg(cin-3B-1) 20 L8
	A i				
BOX peak impact ionization					
a)					
E		extrinsic base -^	depietion ' region edge	C	Impactlonlzation Signed Log (eia-aa- L) 20 IB
	s				
\ / BOX 2 peaks of impact ionization					
b)
Fig. 6. Impact ionization rate for structure with N^C=2.5^1017 cm-3 at VBE=0.7 Vand a) VCE=3 V, b) Vce=9 V.
in the drift region to the right side of the extrinsic base. Maximum rate occurs in the bottom part near the buried oxide interface since electrons are pushed down by the vertical component of field and current is crowded near the buried oxide interface. Since the holes generated by impact ionization drift to the base side and are injected to the emitter, a positive feedback of electrons due to transistor's current gain (ß) occurs and causes BVCEO to be 2 to 3 times lower than BVcbo. Moreover, for BVCEO to occur the critical electric field has to appear along the current path since the avalanche multiplication process is initiated by mobile electrons. Simulated distribution of electric potential, field and impact ionization rate for different VCE in the plane AA from Fig. 6. are shown in Fig. 7.a-c. From the potential distribution in Fig. 7.a it can be observed that collector is not fully depleted for VCE below 3 V. Potential is constant across neutral collector region below extrinsic base and electric field is zero. Potential drop appears across depletion region and peak electric field is placed at the intrinsic base-collector junction (Fig. 7.b). For VCE of 4 V and above, the collector under the extrinsic base is fully depleted. Characteristics of potential distribution bends and deviates from standard square function in the area below the extrinsic base and electric field magnitude in that area is reduced. Furthermore, the potential drop across the intrinsic-base-collector junction practically doesn't increase with VCE and the peak of the electric field at intrinsic base-collector junction is constant (Fig. 7.b). Since the collector charge under the extrinsic base is completely shared, there is no available charge to support increase of potential and electric field across the intrinsic base-collector junction. The rest of the potential drop appears across the drift-region on the right side with respect to the extrinsic base-collector junction. Electric field vectors for transistors with wbext of 0.5 Mm and 1 pm are shown in Fig. 8.a and 8.b, respectively. Direction of the vectors indicates the direction of the electric field, whereas length of the vectors is proportional to the magnitude of the electric field, i.e. density of the electric field lines in given points of the structure. In case of wbext=0.5 Mm, a part of the field lines terminated on the intrinsic base acceptors are originated from donors in the
a)
> H-
c Ä
£
■I
o «
iu
extrinsic base
CäFlft;
b)
E
a i
I
Uj
0.5	1.0
Distance , p.m
2.5x10
2.0x10
1.5x10
V =4-9V
5.0x10
0.0
0.5	1.0
Distance, [un
1.5
b)
3.5x10
0.5	1.0	1.5
Distance, lun
Fig. 7. Distribution of: a) electric potential, b) electric field, c) impact ionization rate dependence on VCE in the bottom part of the transistor, in the plane marked AAin Fig.6. 15 nm from the buried oxide. Extrinsic base is located between 0 and 1 ijm.
drift region, which can be observed as a longer horizontal arrows in Fig. 8a. Therefore, horizontal electric field is only partially shielded by the vertical field and the peak value

nii
c:
depletion region
BOX......"'^fastaritiaiiti^g^teheon'^^ ■ ■ j
(a)
	extrinsic base			
s	----------- ........I.. Ä	....	llf^ ............t	Illy
- B©X~---------srhaB honzontai bompohenl;;^ ; :: , :				
(b)
Fig. 8. Electric field lines at VCE=8 V for structures with a) wbex=0.5 im and b) wbex,=1 im
at the intrinsic junction can be increased with VCE but at a slower rate. Shielding is more efficient for larger wbext and the current generated by impact ionization is smaller, which can be observed as a smaller reduction of the base current in Fig. 5.a and the appearance of the plateau in the characteristics. For wbext=1 pm, intrinsic base electric field, which has only horizontal component is completely terminated between donors below the extrinsic base and the intrinsic base acceptors, which is observed as a shorter horizontal arrows in Fig. 8b. Therefore, horizontal electric field is effectively shielded by the extrinsic base vertical field and cannot be further increased with VCE. Density of electric field lines that are terminated on the extrinsic base acceptors is increased in the area next to the drift region, since there is more available donor charge in the area toward extrinsic collector. Field lines originated from donors in the drift region are spread laterally through the drift region and then bent upwards and terminated on the extrinsic base acceptors. Electric field associated with the extrinsic base-collector junction has vertical and horizontal component. The result of this effect is that the second peak of the electric field appears in the drift region as it can be observed in Fig. 7.b. For larger wbext, if VCEis further increased, critical field is exceeded in the drift region and transistor breakdown occurs. From the impact ionization rate shown in Fig. 7.c it can be seen that two regions of the high impact ionization rate associated with two peaks of the electric field, appear in the transistor. The first one is at the intrinsic base-collector junction, which does not increase substantially for voltages above 3 V, whereas the second is placed in the drift region and increases rapidly for VCE above 7 V. These observations are in a good agreement with the characteristics shown in Fig. 5.a. In the case of the characteristics in Fig. 5.b for collector concentration of 1.5-1017 cm-3 the peak of the electric field at the intrinsic base-collector junction does not approach the critical value and no substantial impact ionization occurs in this region. Critical electric field is achieved in the drift region only and no plateau in the characteristics in Fig. 5.b is observed.
Influence of the collector concentration on the cutoff frequency (fT) is simulated as well and the results are shown in Fig. 9. As expected, fT is increased for higher collector concentrations. This is attributed to the narrower intrinsic
40
-^N^=5x10 OT ^-N„;,=2.5x10 cm"
,17__-3
cm
-o—W..=2x10"cm''
>- Wo2=4x10 cm -N =5x10 "cm
O
Extrinsic Base Width , ^m
Fig. 9. Dependence of the cutoff frequency (fj) on extrinsic base width (wbext) for different collector concentrations.
base and the shorter base transit time. In addition, Kirk effect is pushed to higher current densities. It is also observed that fJ decreases for larger wbex,. This can be explained by the influence of the vertical electric field on the current flow under the extrinsic base. Electrons flowing through the base-collector depletion region are pushed down by the vertical electric field toward buried oxide and local current density is increased causing the Kirk effect to appear at lower values of the collector current. Furthermore, in the case of fully depleted collector, electrons have to travel through the wider depletion region, which results in a longer transit time. Both effects reduce cutoff frequency.
Influence of the distance between n+ extrinsic collector and the p+ extrinsic base is also investigated. BVCEO dependence on wbext is shown in Fig. 10. It can be seen that BVCEO can be increased for larger wbext. However, BVCEO saturates at smaller value if the distance between collector contact and extrinsic base (dc) is reduced. This is explained by
um —i^—d=0.3 (im —(y—d=0.5 (Un
ui
Ü ^
OQ

—^ .
0.5	1.0	1.5
Extrinsic Base Width , |iin
2.0
on wbext for different
Fig. 10. Dependence of BVCEO
distances between n+ collector and p+ extrinsic base (dc).
the reduced depletion region width if n+ region is brought closer to the p+ extrinsic base. Electric field is increased in the drift region and breakdown occurs at lower collector-emitter voltages. It can also be observed that the increase of BVceo with dc saturates at dc=0.4 pm. Obviously, for larger values of dc, the base-collector depletion region does not reach n+ extrinsic collector and does not cause an increase of the electric field in the drift region. Influence of dc on cutoff frequency is also investigated. However, less than 5% improvement in fJ can be achieved by bringing the n+ collector contact region closer to the extrinsic base.
3.2. Emitter height dependence
Dependence of the BVCEO and fJ on the emitter height (hE) is investigated next. Link base length (lb) of 70 nm and collector concentration of 1.5-1017 cm-3 are kept constant in the simulations. Intrinsic transistor profile from Fig. 2 is used in simulations. In the real process, hE would be determined by the thickness of the silicon on insulator film. Dependence of BVceo on hE with wbext as a parameter is shown in Fig. 11. It can be observed that BVCEO is increased with hE as long as collector is fully depleted for collector-emitter voltage that is lower than the breakdown voltage. Since the extrinsic base shielding effect is stronger for larger wbext, BVCEO has the tendency of rise even for larger values of hE. For larger wbext, electric field lines of the horizontal component of field are completely terminated between intrinsic base acceptors and donors below extrinsic base and there is no penetration of the horizontal field associated with intrinsic base-collector junction all the way to the drift region. Magnitude of the electric field for structures with hE of 0.2 pm and wbext of 1 pm and 0.5 pm are presented in Fig. 12.a and 12.b, respectively. It can be seen that for structure with wbext=1 pm peak electric field at the intrinsic base-collector junction rises for VCE voltages up to 5 V and after that it is practically constant. Horizontal field is shielded by the extrinsic base vertical field completely. If VCE is increased further, the second peak of the electric field appears in the drift region and causes the transistor breakdown to occur when critical field is reached. For structure with wbext=0.5 pm,
14 12 10
>
b S3
OQ
»4^=0.2 (im -11- ivj^=0.5 um ~Cr- w^=0.3 [im —o— wi^=0.6 ^m
cm
0.00 0.05 0.10 0.15 0.20 Emitter Height, |xm
0.25
0.30
Fig. 11. Dependence of BVCEO on hE for different wbext.
a)
E
I
u.
I
■S lu
b)
I i
u.
I
lu
Fig.
25
2.5x10
2.0x10
1.5x10
1.0x10
5.0x10
0.0
2.5x10
2.0x10
1.5x10
1.0x10
5.0x10
Distance, \m
12. Electric field in the transistor 15 nm from buried oxide for structure with NDC=1.5-1017 cm-3, hE=0.2 ^m and a) wbext=1 ^m, b) wbext=0.5 ^m.
the extrinsic base shielding is not complete. Peak electric field at the intrinsic base-collector junction increases even for voltages greater than 5 V and can reach the critical value for transistor breakdown. Since part of the electric field lines originated from donors in the drift region to the right side of the extrinsic base are terminated at extrinsic base acceptors, there are more available donor charge below extrinsic base which can support horizontal electric field over the intrinsic base-collector junction. Horizontal field penetrates toward the drift region and the peak at the intrinsic base-collector junction is increased. Avalanche multiplication and transistor breakdown occur at the intrinsic base-collector junction.
In addition, for larger wbext current flows over a longer distance under the influence of vertical electric field and is pushed down to the buried oxide interface. Therefore, current flows through the part of the drift region where magnitude of the electric field is smaller compared to the upper part, closer to the p+ extrinsic base region, resulting in a lower impact ionization rate.
20 -
15 -
...........		
»'t«,=0-2 Jim -	M-m	
-O "««»^O-ä -		
		
(9
li- 10
5 -
0.00
0.05
0.25
0.30
0.10 0.15 0.20 Emitter Height , jim
Fig. 13. Dependence of fj on hE for different wbext.
As hE is reduced, the amount of the available donor charge under the extrinsic base is reduced and voltage drop associated with vertical electric field is smaller. Therefore, a larger voltage drop appears laterally across the drift region and critical electric field for avalanche multiplication in the drift region is reached at lower VCE, causing the decrease in BVceo. For the largest values of hE, BVCEO decreases since collector is not fully depleted any more.
Simulation results of fj dependence on hE for different wbexf is presented in Fig. 13. For larger hE, fj is increased. As hE is increased, cross-section of the neutral collector is increased and current crowding due to vertical field influence is less pronounced. Kirk effect is pushed to higher collector currents as local current density is reduced and fj is increased. The current crowding effects are more pronounced for structures with larger wbexf which can be observed as a smaller value of fj in Fig. 13. In addition, electrons are traveling through the wider depletion region increasing the associated transit time. For wbexf larger than 0.5 Mm the transit time through the depletion region becomes comparable to the base transit time. Furthermore, time constant associated with the collector-base capacitance and the collector resistance i.e. RcCBc is increased for larger wbexf, which further reduces fj.
3.3. Link-base length dependence
Influence of the link-base length (lb) on BVCEO and fj is also investigated. Emitter height (hE) is kept constant at 120 nm and collector concentration is set to 1.5-1017 cm-3. By increasing lb, thickness of the n-collector under the extrinsic base is increased and a higher collector-emitter voltage is needed to reach full depletion of the collector region. Simulation results for BVCEO dependence on lb with wbext as a parameter are shown in Fig. 14. For larger wbext, shielding by the extrinsic base field is more efficient and higher BVceo values are observed. This dependence is similar to the dependence on hE, since in both cases the amount of collector charge is changed by the variation in the thickness of the n-collector below the extrinsic base. Results of
14 12 10
b ui
u ^
Q
-O-w 1^=0.2 iim —Tf—|im	(im
1^=0-3 urn	^=0.6 Jim	^m
0 0.00
0.05	0.10	0.15
Link Base Length , ^m
0.20
Fig. 14. Dependence of B VCEO on link-base length (lb) for different wb^ex,.
fT dependence on lb are presented in Fig. 15. showing the similar behavior as dependence on hE. Current crowding effects are relaxed by increasing the link-base length and fT is improved. Degradation of fT by current crowding is more severe in the case of larger wbext as seen from Fig. 15.
4. Conclusions
LBT structure with the base contact on top is analyzed by the device simulations. Influence of the extrinsic base width (wbext) on common-emitter breakdown voltage (BVCEO) and cutoff frequency (fT) is examined in detail. The effect of collector charge sharing can be used to obtain structures with different values of BVCEO and fT. Total amount of collector charge is determined by the collector concentration and the silicon film thickness, which can be controlled to achieve full depletion of the collector region. In case of fully depleted collector, two peaks of the electric field appear along the current path in the base-collector depletion region. The first one is at the intrinsic-base collector junction and the
25
20 -
15 -
		(im	
		Jim	urn
-A-»^^=0.4 |im			
CD
«J- 10
5 -
0 0.00
0.05	0.10	0.15
Link Base Length, ^m
0.20
Fig. 15. Dependence of fT on link-base length (lb) for different w .
second one in the drift region toward extrinsic collector. Extrinsic base shielding effect can be used to control the value of the peak electric field at the intrinsic-base collector junction. For smaller w^^^, the horizontal field associated with the intrinsic base junction is partially shielded and the peak electric field increases with VCE. In case of larger shielding is more effective; the peak electric field increases at slower rate with and approaches the critical value for avalanche multiplication at higher VCE. In both cases avalanche occurs at the intrinsic-base collector junction but BV^,^^ is increased for larger due to smaller increase of the peak electric field with VCE. For very large horizontal field is completely shielded by the vertical field and the peak electric field at the intrinsic base junction does not increase with VCE. However, the second peak in the drift region increases with V^,,, and can reach the critical value for avalanche multiplication. Transistor breakdown occurs in the drift region for transistors with larger It is shown that engineering can be achieved for below 0.8 Mm. Tradeoff between breakdown (BVCEO) and transistor's cutoff frequency (fT) is presented and design guidelines regarding collector concentration and transistor geometry is given. The potential of BVCEO engineering for top contacted SOI LBT structure without additional increase in cost of technology is demonstrated.
References
/1/ K. Cheng, A. Khakifirooz, P. Kulkarni, S. Ponoth, J. Kuss, D. Shahrjerdi, L. F. Edge, A. Kimball, S. Kanakasabapathy, K. Xiu, S. Schmitz, A. Reznicek, T. Adam, H. He, N. Loubet, S. Holmes, S. Mehta, D. Yang, A. Upham, S.-C. Seo, J. L. Herman, R. Johnson, Y. Zhu, P. Jamison, B. S. Haran, Z. Zhu, L. H. Vanamurth, S. Fan, D. Horak, H. Bu, P. J. Oldiges, D. K. Sadana, P. Kozlowski, D. McHerron, J. O'Neill, B. Doris, "Extremely Thin SOI (ETSOI) CMOS with Record Low Variability for Low Power System-on-Chip Applications", lEDM Tech. Dig., 2009, pp. 49-52
/2/ H. Nii, T. Yamada, K. Inoh, T. Shino, S. Kawanaka, M. Yoshimi, Y. Katsumata, "A Novel Lateral Bipolar Transistor with 67 GHz fma,, on Thin-Film SOI for RF Analog Applications", IEEE Trans. Electron Devices, Vol. 47, No. 7, pp. 1536-1541, July 2000.
/3/ M. Sun, W. T. Ng, K. Kanekiyo, T. Kobayashi, H. Mochizuki, M. Toita, H. Imai, A. Ishikawa, S. Tamura, K. Takasuka, "Lateral High-Speed Bipolar Transistors on SOI for RF SoC Applications", IEEE Trans. Electron Devices, Vol. 52, No. 7, pp. 1376-1383, July 2005.
/4/ J. Cai, M. Kumar, M. Steigerwalt, H. Ho, K. Schonenberg, K. Stein, H. Chen, K. Jenkins, Q. Ouyang, P. Pldiges, and T. Ning, "Vertical SiGe-base bipolar transistors on CMOS-compatible SOI substrate", Proc. Bipolar/BiCMOS Circuits Technol. Meeting, 2003, pp. 215-218.
/5/ T. Suligoj, M. Koričic, H. Mochizuki, S. Morita, K. Shinomura, and H. Imai, "Horizontal Current Bipolar Transistor (HCBT) with a Single Polysilicon Region for Improved High-Frequency Performance of BiCMOS ICs," IEEE Electron Device Lett., in press.
/6/ S. A. Parke, C. Hu, P. K. Ko, "A High-Performance Lateral Bipolar Transistor Fabricated on SIMOX', IEEE Electron Device Letters, Vol. 14, No. 1, pp 33-35, January 1993.
/7/ T. Shino, K. Inoh, T. Yamada, H. Nii, S. Kawanaka, T. Fuse, M. Yoshimi, Y. Katsumata, S. Watanabe, J. Matsunaga, "A 31 GHz fmax Lateral BJT on SOI Using Self-Aligned External Base Formation Technology", lEDM Tech. Dig., 1998, pp 953-956.
/8/..R. Dekker, W.T.A. v.d. Einden, H.G.R. Maas, "An Ultra Low Power Lateral Bipolar Polysilicon Emitter Technology on SOI", lEDM Tech. Dig., 1993, pp 75-78.
/9/ G. G. Shahidi, D. D. Tang, B. Davari, Y. Taur, P. McFarland, K. Jenkins,D. Danner, M. Rodriguez, A. Megdanis, E. Petrillo, M. Polcari, and T. H. Ning, "A novel high-performance lateral bipolar on SOI", lEDM Tech. Dig., 1991 pp. 663-666.
/10/ W. L. M. Huang, K. M. Klein, M. Grimaldi, M. Racanelli, S. Ra-maswami, J. Tsao, J. Foerstner, B. C. Hwang, "TFSOI Complementary BiCMOS Technology for Low Power Applications", IEEE Trans. Electron Devices, Vol. 42, No. 3, pp. 506-512, March 1995.
/11/ J. M. Stork, R. D. Isaac "Tunneling in Base-Emitter Junctions", IEEE Trans. Electron Devices, Vol. 30, No. 11, pp. 1527-1534, July. 1983.
/12/ E. O. Johnson, "Physical limitations on frequency and power parameters of transistors," RCA Rev., Vol. 26, pp. 163-177, 1965.
/13/ J. D. Cressler, G. Niu, Silicon-germanium Heterojunction Bipolar Transistors, Artech House,2003.
/14/ C.Jungemann, R.Thoma and W.L.Engl, "A Soft Threshold Lucky Electron Model for Efficient and Accurate Numerical Device
Simulation," Solid-State Electronics, Vol. 39, No. 7, pp.10791086, 1996.
Marko Koričic*, Tomislav Suligoj Department of Electronics, Microelectronics, Computing and Intelligent Systems, Faculty of Electrical Engineering and Computing, University of Zagreb, Unska 3, HR-10000 Zagreb, Croatia
* Corresponding author. Tel.: +385-1-6129671, fax.: +385-1-6129653, e-mail address: marko.koricic@ fer.hr
Prispelo: 27.05.2010
Sprejeto: 24.06.2011