Original scientific paper
Informacije
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A Innrnal of M
Journal of Microelectronics, Electronic Components and Materials Vol. 43, No. 4 (2013), 222 - 227
A linear current-controlled floating negative resistor
Hamdi Ercan
Department of Avionics, Erciyes University, Kayseri, Turkey
Abstract: In this article, a low voltage CMOS current controlled floating negative resistor which is convenient for integrated circuit implementation is designed by using a self-cascode composite transistor. The proposed circuit only required ± 0.75 V as a power supply has a simple circuit structure and a low power consumption of which value is only 65 ^W. The basic advantages of this circuit are a wide tuning range of the resistance value, an acceptable frequency performance and a wide dynamic range. The performances of the proposed circuit are simulated with SPICE to confirm the presented theory.
Keywords: Negative resistance, CMOS active resistor, current-controlled circuits, Current-mode, Integrated circuits
Linearen tokovno kontroli^ran plavajoči negativni upor
Izvleček: V članku je predstavljen nizko napetostni CMOS tokovno kontrolirani negativen upor, ki je uporaben v integriranih vezjih. Upor uporablja samo kaskaden kompozitni tranzistor. Predlagano vezje z napajalno napetostjo ± 0.75 V izkazuje nizko porabo okoli 65 ^W. Glavne prednosti vezja so široko uporovno območje, sprejemljive frekvenčne lastnosti in široka dinamično območje. Teoretični rezultati so preverjeni s pomočjo SPICE simulacij.
Ključne besede: negativna uporost, CMOS aktiven upor, tokovno kontrolirano vezje, tokovni način, integrirana vezja
* Corresponding Author's e-mail: hamdiercan@erciyes.edu.tr
1 Introduction
In recent years, the disposition of the analog circuit design with low-voltage operation capability has been raised owing to the fact that it is aimed to consume as little power as possible. The low power dissipation is an important factor for the weight and life of a battery. Thus, the design techniques and device technology for low-voltage low-power operation of the analogue circuits are required [1].
Large areas of the chip are required to obtain resistors which can be implemented by using diffusion areas in an integrated circuit. Also, these resistors cannot be easily adjusted to demanded values. To overcome these drawbacks, MOS and bipolar based active resistors topology have been reported in the previous studies [2-5].
Bipolar-based floating resistor was presented in the literature [4, 6]. Though these resistors have a good frequency performance, they have not only narrow dy-
namic range but also consume more power than the MOS-based active resistors. But at the same time, MOS resistors are limited with regard to frequency response and electronically tunability.
The voltage-controlled resistors have been used as an application in the analog circuit design area [7, 8]. The tunable resistance value of these circuits has been restricted by supply voltage. However, they have a wide dynamic range. The current-controlled resistors can be independently tuned over a wide range by biasing current. Also, they have a good frequency performance. Recently, active resistors have been used as not only positive but also negative resistor in some applications. Active positive/negative resistors have been used in a lot of implementations such as oscillators, amplifiers and filters [4, 9, 10,11].
In this paper, a linear current-controlled negative resistor based on self-cascode composite transistor has been introduced. The proposed circuit offers the advantages of a good linearity, a high dynamic range
and low power consumption. This circuit only operates at low voltage as ± 0.75 V. Until now, it has not been shown that low-voltage negative resistor structures are designed in somewhere else. The main contribution of this design to the literature leads to use the low voltage and low power applications. Having a simple structure, the resistance value of the resistor is obtained as the positive and negative.
2
Floating negative resistor
Self-cascode composite transistor structure is shown in Fig. 1. In practical cases, for optimal operation the W/L ratio of the MA should be larger than the W/L ratio of the Mb, that is, a > 1. Moreover, the transistor MB must be in triode region. Depending on the drain voltage, transistor Ma can work in saturation region or triode region. The aspect ratio (W/L) of the equivalent MOS transistor shown in Fig. 1 is decreased. This circuit structure takes an advantage in terms of linearity, dynamic range and electronically controllable resistance range.
Figure 1: The self-cascode composite transistor.
Fig. 2 indicates the proposed linear current-controlled floating negative resistor.
The drain currents of transistors M1and M4 can be written as,
Idi = 2 - Vs 5 - VTH	(1)
2	a +1 L	. (1)
ID4 = 2- Vs8 - VTH	(2)
2	a +1 L	. (2)
ID1 and ID4 are the drain currents of transistors M1 and M4, respectively. In addition, VS5 and VS3 are the source voltages of transistors M5 and Mg, respectively. From Eqs. (1) and (2), the relationship between V1 and V2 shown in Fig. 2 can be expressed as
Figure 2: The current-controlled floating negative resistor.
Vi - =
10 -
, , a .W a +1 L
Io + ii
aW
'-'-a+i )^z) (3)
Current i1 shown in Fig. 2 is given as:
k.	/ \ a ^	W'
2 n	a +1 , V y	L _
1 / 2
X
X
210 - kf
a
a +1
W
L
(l - ^2 )2
1 / 2
(4)
where kn is the transconductance parameter of the NMOS transistor. ^n is the electron mobility and Cox is the oxide capacitance per unit area. I0 is the biasing current. For a very small difference voltage which gives 2I0>> (1/2)kn(a/a+1)(W/L)(V1-V2)2 , the current i1 exhibits a quite linear behavior. As shown in Eq. (4), linearity of the resistance highly depends on the aspect ratio (W/L) of the equivalent self-cascode composite MOS transistors and the difference voltage. Therefore, i, can be further reduced to:
=-((i - V2 )kn
^ a \ W
a +1
L
1 / 2
(5)
In this instance, it is clear that i2 = -i1. The resistance of the proposed circuit can be written as
^12 =-
kn
a
a +1
W
L
-1 / 2
(6)
0
0
The resistance value can be easily controlled by biasing current as shown in Eq. (6). The proposed negative resistor shown in Fig. 2 can be easily converted to the positive resistor. A connection is made between the gates of transistor M1, M2 and drain of M2 instead of M4's drain. Additively, the gates of M3 and M4 are connected to the drain of M4 instead of M2's drain. In this case, it is clear that i1 = -i2. So, the definition of the positive resistance may be as follow:
Ri2 =
a
a +1
W
L
-1 / 2
(7)
The positive resistance of the resistor is able to be easily tuned by biasing current, too. Also, building two different kinds of in a single circuit is one of the important features of the proposed circuit. These features take essential advantages for the analog circuit applications.
For operating at low-voltage, this circuit requires to ensure the below-mentioned condition.
Vdd -(- Vss )> Vthp + 4Vdssat
(8)
Table 1: Aspect ratio of the transistors.
Transistor	M1 - M4	M5 - M3	m9 - m15
W/L	5/1	1/2	30/0.26
I / V characteristics of the proposed resistor are shown in Fig. 3.
Figure 3: I / V characteristics of the proposed resistor.
where VDD and -VSS are the supply voltages of the circuit. VTHp is the threshold voltage of the PMOS and VDSsat is the drain-source saturation voltage of the transistors. The value of the VTHP is approximately 0.4 V for 0.13 ^m technology [12]. The lower drain currents have values, the more drain-source saturation voltage is reduced. Thus, the proposed circuit can be operated at low-voltage. Additionally, the estimation of the proposed circuit's dynamic-range is calculated as
Vl - V2
<
a +1
a
I0
K W
—
2 n L
1 / 2
(9)
The dynamic range highly depends on the biasing current as shown in Eq. (9). Thus, the dynamic range will be expanded for the high values of the biasing current.
3 Simulation results
The proposed linear current-controlled floating negative resistor was simulated by SPICE owing to approve the theoretical approaches. The SPICE model 0.13 ^m CMOS parameter for the transistors are used in [12]. The supply voltage is ± 0.75 V and the aspect ratio of the transistors is presented in the Table I.
Both theoretical and simulation results of the proposed resistor have been given in Fig. 3. It is shown that behaviour of the proposed resistor is highly linear from -250 mV to +250 mV. Fig. 4 shows the input voltage versus the input current of the simulated resistor.
Figure 4: I / V characteristics for the different biasing current.
The biasing current of the resistor is varied from 15 ^A to 45 ^A step by step. The resistance value of the resistor can be easily adjusted by biasing current I0 as shown in Fig. 4. The frequency response of the proposed resistor is illustrated in Fig. 5.
When the frequencies are increased, it is found that the proposed resistor can be operated with the -3dB bandwidth of about 148.3 MHz, 195.4 MHz and 222.1 MHz for 15 ^A, 30 ^A and 45 ^A of the biasing current, respectively. Taking into consideration these results,
k
0
n
1kHz 10 kHz 100 kHz 1MHz 10 MHz 100 MHz 1GHz
Frequency
Figure 5: The frequency response of the proposed resistor.
the proposed circuit exhibits a good frequency performance.
The variation of the total harmonic distortion with peak to peak input voltage for I0 = 15 ^A and R12 = 8.7 kQ is displayed in Fig. 6.
Peak to peak input voltage (mV) Figure 6: THD % versus input voltage.
The variation of the THD with input signal amplitude for a biasing current of 15 ^A as shown in Fig. 6 is illustrated. We can evidently see that the THD value is 0.465 % at 250 mVp-p. It is depicted that the THD values obtained according to different peak to peak input voltages are acceptable values. Also, the total power consumption of the proposed circuit is obtained as low value as 65 ^W. The resistance of the proposed circuit has been calculated as both theoretical and simulation. The negative resistance of the proposed resistor for different bias currents is shown in Fig. 7.
The negative resistance is able to be tuned from 5.9 kQ to 243 kQ when the biasing current is adjusted between 0.1 ^A and 60 ^A. Note that, this circuit has a wide range negative resistance (R12).
Noise is a main contributor to the inaccuracy of the analog circuits. The main source of the noise in a MOS
10" 10' Bias Current (pA) Figure 7: The negative resistance versus bias current.
transistor is the thermal noise owing to the thermal effect of the electrons in the resistive channel. The voltage noise of a MOS transistor is given in Eq. (10).
3	Hz
(10)
where k is Boltzmann's constant and T is the temperature. gm and r0 are the transconductance and output resistance of the MOS transistor, respectively. Due to the fact that gm can be changed by the drain current of the transistor, the noise of the proposed circuit indicated in Fig. 2 depends on the biasing current.
A noise analysis of the negative resistor was performed in SPICE. Therefore, in accordance with SPICE results, the noise contributions of each transistor to the total output voltage noise are given in Table II.
Table 2: Noise sources of the proposed negative resistor.
Transistors	The voltage noise (V2/Hz)	(V2/Hz)	
M1	6.72x10-18	M9	2.60x10-15
M2	2.24x10-18	M10	6.80x10-16
M3	1.08x10-19	M11	6.80x10-16
M4	0.67x10-19	M12	19.77x10-2"
M5	62.83x10-18	M13	7.03x10-21
M6	71.17x10-18	M14	1.70x10-18
M7	21.38x10-21	M15	1.00x10-3"
M8	21.38x10-21		
Total voltage noise		64.07 nV/VHz	
The resistance value of the proposed circuit is -6.31 kQ for I0=45 ^A. The total voltage noise for the proposed circuit which has -6.31 kQ resistance value is 64.07 nV/VHz. The main contributors to the total noise are the three transistors M9, M10 and M11. Total voltage noises can be obtained as 571^44 nV/^/Hz, 63.003 nV/VHz and 64.070 nV/VHz for I0=15 ^A, I0=30 ^A and I0=45 ^A, respectively. In other words, the total voltage noise is strongly depends on transconductance as shown in Eq. (10).
the theoretical and simulation results by changing the value of the bias current. The total voltage noise and THD values of the proposed circuit have been calculated as 0.465 % and 64.07 nV/VHz, respectively. Finally, we expect that such a tunable behaviour of the proposed negative resistor could highly be appropriate for the low voltage integrated circuit realizations, considering into the perfect resemblance between all the simulated and theoretical performances.
The negative resistance having a wide tuning range is an important advantage for the analog circuit applications. The comparison of the performance parameters belongs to some resistors and the proposed negative resistor is displayed in Table III.
If the circuits are compared in terms of supply voltage, the proposed negative resistor requires a small supply voltage. As shown in Table III, the total harmonic distortion of the proposed circuit is lower than the others. Moreover, this circuit consumes low power of which has only 65 ^W value. The total voltage noise has not been studied in other cited paper. However, the total voltage noise of the proposed circuit can be obtained as 64.07 nV/VHz.
4 Conclusion
In this study, the self-cascode composite transistor based a linear current-controlled floating negative resistor has been presented. The circuit required low supply voltage as well as ±0.75 V consumes low power about 65 ^W. In addition, the circuit has highly basic circuit structure. The behaviour of the proposed resistor is highly linear from -250 mV to +250 mV. The value of the proposed resistance can also be adjusted from 5.9 kQ to 243 kQ with perfect correspondence between
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Table 3: Comparison between this study and the others.
Parameters	This study	[3]	[13]	[4]	[5]
Supply voltage	± 0.75 V	± 3 V	± 1.5 V	± 1.5 V	± 2.5 V
Input range	± 250 mV	± 1V	± 200 mV	± 30 mV	± 30 mV
Tuning range	5.9 kQ - 243 kQ	800 kQ - 4 MQ	60 kQ - ^	43Q - 516kQ	132 Q-1.25 kQ
Total harmonic distortion (THD)	0.465 % (at 1 MHz)	0.5 % (NA)	NA	0.747 % (at 1 MHz)	> 1 % (at 1 kHz)
Total voltage noise	64.07 nV/VHz	NA	NA	NA	NA
Power dissipation	65 ^W	NA	NA	0.9 mW	NA
Bandwidth	222.1 MHz	NA	NA	70.2 MHz	NA
Technology	CMOS (0.13 ^m)	CMOS (0.35 ^m)	CMOS	Bipolar	Bipolar
Positive resistance	Yes	Yes	Yes	Yes	Yes
Floating	Yes	Yes	Yes	Yes	Yes
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Arrived: 09. 08. 2013 Accepted: 08. 10. 2013