103
Original scientific paper
Journal of Microelectronics, 
Electronic Components and Materials
Vol. 53, No. 2(2023), 103 – 117
https://doi.org/10.33180/InfMIDEM2023.205
How to cite:
Ž. Rojec, “Towards Smaller Single-point Failure-resilient Analog Circuits by Use of a Genetic Algorithm", Inf. Midem-J. Microelectron. Elec-
tron. Compon. Mater., Vol. 53, No. 2(2023), pp. 103–117
T owards Smaller Single-point Failure-resilient 
Analog Circuits by Use of a Genetic Algorithm
Žiga Rojec
Department EDA, Faculty of Electrical Engineering, University of Ljubljana, Slovenia
Abstract: Failure-resilient analog circuits are difficult to design, but artificial intelligence can help crawl the topology solution space. 
Using evolutionary computation-based topology synthesis we evolve analog arcus tangent computational circuits, resilient to any 
rectifying diode or resistor high-impedance single failure or removal. We encode analog circuit topologies as individuals with an 
upper-triangular incident matrix. Circuits are evolved using a combined technique utilizing parts of NSGA-II and PSADE, based on a 
special three-dimensional robustness function. We show that topology size for a failure-resilient circuit can be classes smaller than 
hand-made component-redundancy-based solutions. Our best failure-resilient topology comprises six diodes, three resistors, and a 
voltage offset source. 
Keywords: analog circuits, analog circuit synthesis, circuit optimization, failure-resilience, circuit robustness
Manjšanje analognih vezij odpornih na odpoved 
poljubne komponente z uporabo genetskega 
algoritma
Izvleček: Analogna vezja, ki so odporna na napake, je težko načrtovati. Pri prečesavanju prostora možnih topologij lahko pomaga 
umetna inteligenca. Z sintezo topologij, temelječi na evolucijskem algoritmu, smo razvili analogno računsko vezje za inverzni tangens, 
ki je odporno na visokoimpedančno okvaro posamezne komponente (diode ali upora) ali njene odstranitve. Topologija analognega 
vezja je v algoritmu zapisana v obliki zgornje-trikotne vpadne matrike. Vezja razvijemo z uporabo kombinirane metode z uporabo 
večkriterijskega optimizacijskega algoritma NSGA-II in PSADE, kjer je za usmerjanje sinteze razvita posebna tri-kriterijska funkcija 
robustnosti. V članku prikazujemo kako zmanjšati velikost topologije, odporne na odpoved komponente, na razrede manjšo velikost 
od ročno izdelanih robustnih topologij, ki temeljijo na redundanci posameznih komponent.  Naš najboljši rezultat je analogno 
računsko vezje za inverzni tangens, ki je sestavljeno iz šestih diod, treh uporov in odmičnega napetostnega vira. 
Ključne besede: analogna vezja, sinteza analognih vezij, optimizacija vezij, odpornost na napake, robustnost vezij
* Corresponding Author’s e-mail: ziga.rojec@fe.uni-lj.si 
1 Introduction
Design of an analog circuit is a challenging task, espe-
cially when the product has to meet high standards 
and fulfill tough requirements.
Designers often use various simulation tools to predict 
temperature, humidity, and electromagnetic behavior 
during circuit operation. Furthermore, to predict the 
blueprint manufacturability and maximize the produc-
tion yield, they also use statistical methods, such as  
Monte Carlo analysis [1]. 
However, customer requirements might get even hard-
er. When a device is targeted for use in harsh conditions 
(i. e., space exploration, aeronautical missions, auto-
motive, robotics), we expect the product to be robust 
against extreme temperature swings, high ionizing and 
electromagnetic radiation levels, high working cur-
rents, and more. That kind of stress can lead to compo-
nent faults and premature device failure. Furthermore, 
failed components in remote and unmanned missions 
could not be replaced easily. 

104
Ž. Rojec; Informacije Midem, Vol. 53, No. 2(2023), 103 – 117
Researchers have already focused on hardening elec-
tronic devices against failures per se [2]. The classical 
ways of doing that include component redundancy, 
overdesign, shielding and insulation, thermal manage-
ment, and so on. Most of the time such solutions signif-
icantly increase the size, weight, and finally, the cost of 
the device. The upper methods usually aim to protect 
every circuit component as if it was the main breaking 
point of the system. 
Researchers have already proposed systems resilient 
to failures that occur in vivo. Meaning, the circuit has 
the ability to persist functional when one or more com-
ponents fails during the circuit operation [3]–[6]. Such 
systems usually utilize duplicated circuit modules to 
form redundant sub-systems which are controlled by 
various voting mechanisms [3], [7]. However, the de-
multiplexer then becomes the weak part of the system. 
This paper shows an alternative method of evolv-
ing failure-resilient analog circuits. Using an intensive 
evolutionary search, we can find novel analog circuit 
topologies that exhibit robustness to any electronic 
component (semiconductor diode or resistor)  high-
impedance failure or removal, without a dedicated ac-
tive demultiplexing system. 
We show in this work, that by using an evolutionary to-
pology synthesis tool, we can greatly reduce the size 
and the number of needed components to achieve 
failure-resilience of an analog circuit, compared to ca-
nonical hand-made design. 
To the best of our knowledge, this is one of the few 
published works on the automated synthesis of a pri-
ori robust, failure-resilient nonlinear computational 
analog circuits [3], [4], [8]–[15], and also one of the first 
attempts of redundancy reduction by using evolution-
ary search. 
The paper is organized as follows. We summarize previ-
ous work on robust topology synthesis in Section 1.1 
and describe our motivation in 1.2. We describe the 
applied topology synthesis technique in Section 2. Re-
sults are given in Section 3, summarized in 3.8 and con-
cluded in Section 4. 
1.1 Previous work
The discovery of novel circuit topologies has been 
done by hand for over a century. This is changing with 
the availability of novel tools, relying on artificial intel-
ligence [16]. Since the beginning of this research area 
[17]–[19], computer-aided circuit synthesis has be-
come human-competitive and trustworthy for fabrica-
tion [16], [20]. We believe, rather than replacing a hu-
man expert in the industry, AI might help in the rapid 
exploring of undiscovered topology space, thereby 
helping and speeding up the design process. 
Reviews of existing analog circuit synthesis techniques 
can be found in existing literature [21], [22]. However, 
we give a brief overview of existing topology synthesis 
efforts for extremely robust and failure-resilient analog 
circuits below. 
1.1.1 Synthesis method
Analog topology synthesis is an extremely non-linear 
and complex task, which is why most existing ap-
proaches in this field search topology with a method, 
based on the Darwinian selection of the fittest, i.e. evo-
lutionary or genetic algorithm. 
Somehow special are the works of Zebulum and  Key-
meulen, et. Al., who presented an evolutionary algo-
rithm that is being run on the controlling unit of the 
circuit under failure, in vivo [4], [12]. 
Evolutionary methods demonstrate a capacity to tack-
le unconventional challenges. One compelling reason 
that supports the continued relevance of evolutionary 
computation, even when compared to neural networks 
like GNNs, is that they do not always require prior train-
ing to align with the defined cost function.
However, emerging tools rooted in GNNs, like CktGNN, 
showcase impressive capabilities in generating robust 
circuit topologies [23].
1.1.2 Synthesis goals and degrees of robustness
Passive filters are usually the entry point for showing 
the performance of analog circuit synthesis tools. Most 
of the works on failure-resilience also experimented 
with the synthesis of robust passive analog filter cir-
cuits, dealing with various degrees of component 
faults. Resistor/capacitor/inductor removal was con-
sidered in [9], [15], while in addition [3], [7] also stud-
ied the complexity of partial and full short-circuit and 
high-impedance faults. Studies [24]–[27] only consid-
ered R/L/C parameter perturbation without full com-
ponent failure. 
Other authors reported syntheses of
- compensator circuit [8] and 
- inverter, amplifier, and oscillator [13] resilient to 
bipolar transistor removal, 
- PID controller with R/L/C removal resilience [10], 
- transistor-fault resilient amplifier [11],
- half-wave rectifier, NOR gate, and voltage-con-
trolled oscillator for extreme temperature swings 
(in situ evolution) [12]

105
- XNOR gate, analog multiplier, and inverter resil-
ient to arbitrary faults in the controlling unit FPTA 
(Field Programmable Transistor Array) [4]
- the natural logarithm and square-root analog 
computational circuits resilient to semiconductor 
diode short-circuit or high-impedance malfunc-
tion [28] 
1.2 Motivation
1.2.1 Failure-resilience
For this work, let us define failure-resilience as an analog 
circuit topology property, where any of the basic com-
ponents (diode or resistor) can be removed or replaced 
with high-impedance failure, with the circuit showing 
minimal-to-zero deformation of nominal signal process-
ing abilities. The voltage source and the 10 k W input-
pullup resistor are excluded from the definition. 
The methodology incorporates various failure scenar-
ios using specialized “failure-defining” Spice models, 
as demonstrated in our prior work [28], where we suc-
cessfully synthesized analog circuits resilient to both 
high-impedance and short-impedance failures in semi-
conductor diodes. In this paper, we primarily concen-
trate on minimizing topologies that are fully resilient to 
high-impedance failures. However, due to high compu-
tational costs, we do not address short-circuit failures 
for all component types in this paper; this topic is left 
for future research.
1.2.2 Size of failure-resilient circuits 
Failure-robustness comes with a cost. It is generally 
paid by (often significantly) higher total number of 
needed components for the same nominal task as a 
non-robust circuit would perform. For a system to sur-
vive such rigorous change, as one or any component 
removal/failure, redundant elements and connections 
must be available in the system. 
Let us consider an example of a non-linear, computa-
tional analog circuit from Figure 1. The circuit outputs 
an inverse tangent of input voltage signal between 0 
and 10 V. It is a hand-designed linear voltage divider, 
with diodes used to switch between five linear seg-
ments, which closely interpolate the mathematical 
function [29]. Due to its simplicity, the topology is often 
used instead of the amplifier-chain summing circuit. If 
any of the components in the dotted square (except 
for the voltage source) fails (or is removed), the circuit’s 
transfer function severely changes as seen in Figure 2 
with absolute error range plot and Figure 3 with rela-
tive error plots. 
The most common and straightforward approach to 
achieving failure-resilience property is to introduce 
redundancy on a single-component level. In the case 
of an arctan circuit, every diode has to be paired in 
parallel and every resistor has to be (at least) tripled in 
parallel. Two diodes in parallel give a sub-circuit where, 
theoretically, any of the two diodes might enter high-
impedance failure without transfer function transfor-
mation. Single resistor with resistance R
n
 has to be re-
placed with three parallel resistances 3 R
n
 to maintain 
33% relative error of sub-circuit in case of one resistor 
entering high-impedance failure. 
Figure 4 shows a hand-designed topology that fulfills 
the failure-resilience criteria. Fair nominal response 
and narrow error range in failure cases are presented 
in Figure 5 and Figure 6.  Evidently, the circuit topology 
hence the number of needed components goes off-
scale. While the nominal non-robust topology includes 
10 resistors and 5 diodes (excluding the input resistor, 
see 1.2.1), the hand-made robust version comprises 30 
resistors and 10 diodes. In CMOS technology, for exam-
ple, resistors occupy large chip areas [30]. In addition, 
those resistances are multipliers of the nominal values, 
which further multiplies the needed area for fabrica-
tion. The circuit total cost would be above comparison 
to the nominal non-robust version.
However, novel studies of analog topology synthesis 
imply, that number of needed components for failure-
resilience might somehow be lower than expected in 
hand-made designs [3], [7]. The possible reason for that 
phenomenon is that open-ended topology synthesis 
allows component-level redundancy to be replaced 
with system-level redundancy. 
1.2.3 Topology size as a synthesis constraint
In this study, we explored the lower limits of topology 
size for a failure-resilient computational analog circuit. 
We show, that for the arcus-tangent circuit, the topol-
ogy could be reduced from 40 critical components in 
hand-made design down to 8 components by evolu-
tionary-based synthesis. This also has fewer compo-
nents than used hand-made non-robust design (15). 
Figure 1: Canonical hand-designed piece-wise linear 
arctan computational circuit topology. 
Ž. Rojec; Informacije Midem, Vol. 53, No. 2(2023), 103 – 117

106
Our study provides step-by-step size-reducing results 
for further investigation and a better understanding of 
underlying mechanisms. 
Primary contribution of this paper lies in the demonstration 
of a novel application of evolutionary methods, resulting in 
the attainment of system robustness that has not been ob-
served in any existing systems or circuits within the literature. 
Figure 2: Hand-designed non-robust arctan circuit: nomi-
nal response (black) completely covers the arctan func-
tion. The range of various failure responses is given in blue.
Figure 3: Relative error curves of nominal (solid) and 
component failures (dotted and dashed).
Figure 4: Hand-designed piece-wise linear arctan 
computational circuit, robust to any single component 
high-impedance failure or removal.
Figure 5: Hand-designed failure-resilient arctan circuit: 
nominal response (black) covers the arctan function. 
The range of various failure responses is given in blue.
Figure 6: Hand-designed failure-resilient arctan circuit: 
relative error curves of nominal (solid) and component 
failures (dotted and dashed).
2 Methods
In this section, we provide details of the methods used 
in this circuit synthesis. The applied approach is mostly 
based on [28]. 
2.1 Analog Circuit Representation
Upper-triangular incident matrix is a well-proven 
method of encoding an analog circuit topology [22], 
[28], [31]. It is based on a fixed set of available compo-
nent terminals. Each building block can comprise one 
or more input/output terminals (see Figure 7). Usually, 
the building-block terminals are located on the left 
side of the fixed set, and outer connections are located 
on the right-side of the set.  The set is then mirrored in 
two dimensions, forming a connection matrix, where 
the logical one represents an existing zero-impedance 
Ž. Rojec; Informacije Midem, Vol. 53, No. 2(2023), 103 – 117

107
connection between the terminals on both axes. The 
matrix is filled with logical ones on a diagonal so that 
by definition, every terminal is connected to itself. Only 
the upper matrix triangle is used to exclude half of the 
redundant mirror connections from the bottom trian-
gle, to reduce the effective matrix size, without sacrific-
ing any topology search space [31], [32]. Additionally, 
in the inner-connections sector of the matrix, we allow 
every possible connection, while in the outer-connec-
tion section only one positive logical value is allowed 
per line, filtering-out any connections between outer 
terminals. 
Figure 7: An example of an upper-triangular matrix, 
representing a simple T-shaped analog circuit topol-
ogy [31].
Components with adjustable parameters (i.e., resist-
ances, capacitances, transistor widths and lengths, etc.) 
have their values organized in a separate array, called 
value vector. While the topology matrix is purely bina-
ry, the value vector is a numeric entity. 
2.2 Genetic Reproduction and Sizing
For evolutionary computation and mimicking natu-
ral genetic reproduction, we use the topology-matrix 
crossover technique, described in [31]. Every terminal is 
connected to other terminals via the logical values that 
reside on a column and a row, intersecting the diago-
nal element, that represents the connection to itself. By 
exchanging the two lines of the matrix with another 
topology matrix, the information of the terminal con-
necting with the rest of the circuit is transferred. Figure 
8 shows two examples of newly-created offspring with 
one terminal (N=1) and three terminal (N=3) informa-
tion being exchanged. Note that in the applied algo-
rithm, the number of exchanged terminal connections 
N is a randomly-chosen number from the set {1,2,3}. 
Figure 8: Topology crossover examples. For better illus-
tration, parent no. 2 is a full upper-triangular matrix [31].
The value vector is being optimized using two different 
methods. The first one is a reproduction mechanism, 
inspired by a well-known intermediate crossover [33]. 
The choice between topology-matrix or value-vector 
crossover is initiated by the evolutionary algorithm. In 
one case offspring will inherit a modified topology and 
in another a modified parameter. 
Another parameter tuning technique in this work is an 
established PSADE (Parallel Simulated Annealing and 
Differential Evolution) [34]. Due to its computational 
expensiveness (yet effectiveness), it is triggered only 
every 10
th
 generation on one to three best individuals. 
2.3 Fitness function
The fitness function should encompass the desired 
properties of the circuit. Additionally, it should filter 
out individuals with unwanted properties and help to 
guide the searching algorithm through the valley of 
local minima. We will briefly review the applied fitness 
function below, but the full justification of chosen cri-
teria is given in [28]. 
In the case of open-ended topology synthesis, the fit-
ness function definition is rather complex and com-
Vin Vout
R1 R2 C1
!
!
!
!
!
!
!
!
!
! !
!
!
!
!
Inner-connections
Outer-connections
R1 R2
C1
R1 R2
C1
Forbidden sector
without connections
N=1
N=3
offspring 1 offspring 2 parents
Ž. Rojec; Informacije Midem, Vol. 53, No. 2(2023), 103 – 117

108
prises several stages. The first is an evaluation of the 
circuit’s transfer function, i.e. signal processing quality, 
using a DC analysis in Spice simulator. In the case of 
arctan circuit design (let us denote the mathematical 
function as g) we calculate the root mean square error 
(RMSE) between V
out
 (V
in
) and g(V
in
). We call the result 
fitness and denote it as f. 
Calculation of failure-resilient circuit fitness needs to 
be carried out for every predicted failure scenario. In 
our work, failure-resilience is defined as the high im-
pedance failure of any resistor or semiconductor diode 
(see 1.2.1). In the case of 30 resistors and 10 diodes, the 
total number of RMSE calculations must be 41 – that 
is one for nominal (no failure) scenario f
nom
, and 40 for 
every critical device failed, multiplied by the number 
of failure types considered (only one failure type in this 
case). Vector f comprises all RMSE results:
 
1,11 ,,
  , , ..., , ..., 
nom FN F
ff ff  

f  (1)
where N is the total number of critical components and 
F is the total number of failure types [28]. 
Failure-resilient circuit evaluation is carried out in mul-
tiple dimensions, and forms a three-dimension robust-
ness vector r: 
 
max
 
nom
f
f







f
r     (2)
where f
nom
 is RMSE result of no-failure, nominal circuit 
topology, f
max
 is the maximum of vector f and α
f
 is the 
standard deviation of the same vector [28]. Vector r 
gives insight into a single failure-resilient candidate 
- nominal performance
- performance in case of worse single-point failure and
- statistical failure scattering. 
This separation gives a chance to the NSGA-II algorithm 
to non-dominantly sort the individuals into Pareto-
fronts and by that maintain the genetic diversity, thus 
avoiding premature convergence. 
In the specific case of a failure resilient circuit synthesis, 
a practitioner might encounter a false-robustness phe-
nomenon, which we explain below. 
Let us consider an example of a simple diode half-wave 
rectifier (Figure 9, left). If D0 fails or is removed, the rec-
tifier is no longer working, and statistically, one critical 
component (diode) makes a 100% chance of circuit 
failure. Imagine a topology modification, that would 
harden the circuit against the D0 removal or high-im-
pedance failure. Let us have four additional diodes to 
fulfill that requirement (one would be enough, but we 
assume the search algorithm does not know that). The 
search algorithm can encounter a topology with four 
diodes with no effect on the nominal transfer function 
(example in Figure 9 (right)). Still, if D0 fails, the circuit 
does, too. However, if any of D1-4 fails, the circuit still 
delivers the transfer function. It appears as only 20% 
of critical components (diodes) cause a fatal scenario 
for the circuit. The latter circuit might get promoted 
because of its better “robustness” value. Obviously, this 
is not the case, because D1-4 are not electrically con-
nected and do not play any role in signal processing. 
That kind of circuit has to be ranked out since it does 
not contribute to real circuit robustness. 
Figure 9: False-robustness problem [28].
Inclusiveness [28] successfully unfolds the false-robust-
ness problem. Using modified diode models and SPICE 
simulator commands we determine which of the com-
ponents are electrically connected (included) and have 
an effect on signal processing. Inclusiveness (denoted 
by I) is calculated as a ratio between the number of all 
critical and included components. Having an updated 
robustness definition:
 
max
  
nom
f
fI







f
r
      (3)
circuits with greater inclusiveness are promoted over 
the circuits with floating or flawed connected com-
ponents. However, this can lead the synthesis to build 
larger circuits with excessive redundancy, so compo-
nent number limits must be set elsewhere in the algo-
rithm. In our case, the top number of available devices 
is set in the pre-defined component set, which also de-
fines the topology-matrix size. Note that only the inclu-
siveness of diodes was considered in our work. 
2.4 Synthesis algorithm
The search and sorting algorithm utilize major ideas 
from NSGA-II [35].
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109
The evolutionary algorithm is initiated by a randomly 
generated population. Then every individual is evalu-
ated according to the fitness/robustness from Section 0. 
Sorting is performed in three steps, following NSGA-II. 
In the first step, individuals that do not dominate each 
other (are not beaten in any combination of objectives) 
are assigned to a front (i.e. Pareto front). The remaining 
individuals are put in a second, third, etc., front, with the 
same non-dominance criteria. A new generation assem-
bly is the second step. We aggregate the new generation 
starting with individuals from the 1
st
 front, and continue 
with available individuals from further fronts. Because 
a union of parents and offspring is usually larger than 
available space in the new generation, there is a front of 
individuals, that does not fit as a whole to the new gen-
eration. A selection between non-dominated individu-
als needs to be undertaken. This is done in the third step, 
the crowding distance calculation. The crowding dis-
tance is the distance between two neighboring points 
(i.e. individuals) along each of the objective axes. Rank-
ing individuals with higher crowding distance helps to a 
more even distribution in a front of individuals. 
After the assembly of the new generation, a parent se-
lection process takes place. With the tournament, some 
randomly selected individuals are chosen from the 
generation. The selected individuals compete based 
on their front number (lower is better) and crowding 
distance (higher is better). Two tournaments take place 
to choose two future parents. 
Having selected two parents, their genetic material 
gets reproduced. This can be done by mating their 
genetic material as in 0 or by mutating it. Control over 
mating/mutation is a statistical probability, set at the 
beginning of the algorithm. Similarly, a probability pa-
rameter controls whether the topological or paramet-
ric part of the gene will be mated/mutated. 
We repeat the synthesis algorithm until at least one of 
the stopping criteria (i.e., design requirements, max. 
number of generations, timeout.) is met. When ten gen-
erations have passed, we run a PSADE [34] parameter 
optimization on three of the best circuits from the popu-
lation and thus fine-tune the ambitious individuals. 
Figure 10 summarizes the main synthesis algorithm 
steps. 
2.5 Finding minimal topology
Our objective was to evolve circuits with consistent 
performance even if devices are removed. Initially, 
we aimed to incorporate as many “redundant” com-
ponents as possible. However, circuit size doesn’t al-
ways reflect actual functional contributions, leading to 
“dummy” or electrically connected but non-functional 
components.
To address this, we introduced “Inclusiveness” to pre-
vent circuits dominated by dangling sub-circuits, 
enhancing evolutionary outcomes. Individuals with 
greater inclusiveness measure propagate more effec-
tively. Our experimentation revealed a paradox when 
maximizing redundancy while minimizing circuit size 
simultaneously. Hence, we perform separate stages for 
minimizing and maximizing circuit schematics. We are 
listing two more reasons, why the size of circuit sche-
matics is not another objective of NSGA-II search.
Our topology representation method using an upper-
triangular incident matrix limits arbitrary extensions 
during evolution runs. Varying matrix sizes in the evo-
lutionary pool cause inconsistent crossovers and mat-
ing patterns.
The third concern relates to the computational com-
plexity of NSGA-II and evaluating circuits under differ-
ent failure scenarios. A variable maximum component 
number during evolution would increase computa-
tional effort, impacting NSGA-II’s performance and cir-
cuit robustness evaluation. As a result, we chose not to 
experiment with variable component numbers to mini-
mize computational burden.
3 Results
Our experiment comprised eight independent topol-
ogy searches. For each synthesis we predefined the 
set of available components, that is N
d
 diodes and N
r
 
resistors that are subject to possible high-impedance 
failure. V
off
 and a R
in
 input resistor (the latter was non-
optional) were also available with each synthesis but 
were excluded from failure consideration. 
Initial population
Evaluation
Sorting
Tournament (parent selection)
(according to rank and crowding-distance)
(calculate fitness/robustness)
Reproduction (offspring creation)
Offspring evaluation
Criteria 
met?
END
True False
10th 
generation?
True
False
PSADE parameter opt. on 
3 of best individuals
Figure 10: The applied evolutionary algorithm flow-
chart [31].
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110
The main part of the experiment was discovering the 
possibilities of finding topologies with fewer compo-
nents than in hand-designed examples (e.g., from Fig-
ure 4), that perform arcus tangent analog calculation 
and exhibit the failure-resilience property (1.2.1). 
The genetic algorithm parameters were fixed through 
the experiment and are summarized in Table 1. 
Table 1: Genetic algorithm properties.
Parameter Value
Population 1000
Tournament 3
Mating prob. 0.6
Topology reproduction prob. 0.8
Resistance values were limited to the range between 
10 and 100 k W, and voltage source with DC range of 0 
to 6 V. Every synthesis was conducted on an i9 HP desk-
top, utilizing 16 computational threads on 8 processor 
cores. 
3.1 Synthesis with a max of 12 diodes, 12 resistors 
With the ambition to cut the number of needed com-
ponents for the circuit, we gave the first upper limit of 
Nd
max
 = 12 and Nr
max
=12. This is already a significant cut 
of the total number of components (Nd + Nr) in com-
parison to hand designed example from Figure 4 which 
comprises 40 components. The algorithm can, howev-
er, synthesize a topology with fewer elements. 
Starting with a random population, without any prior 
knowledge available in the population itself, we let the 
combined NSGA-II algorithm run for 306 generations 
(roughly 15 hours). The outcome is presented in Figure 
11. The final topology comprises all 12 available diodes. 
Some resistors were excluded from the final topology 
since they do not have any signal-processing effect 
(such as short-connected resistors, or resistors con-
nected to simulator-helper nodes). The voltage source 
was also not included in the final design. We excluded 
some of the components already from topology sche-
matics in Figure 11. 
We summarize the circuit performance in three param-
eters: nominal topology RMSE is 0.312, the worst failure 
RMSE is 0.370 and the standard distribution of all cases 
(nominal and failures) is 0.026. One can visualize those 
results in Figure 12 and Figure 13. 
Figure 12: Synthesized arctan computational circuit 
(Nd
max
 = 12, Nr
max
 = 12): nominal response (black), 
arctan function (red, dashed-dotted). The range of vari-
ous failure responses is given in blue.
Figure 13: Synthesized arctan computational circuit 
(Nd
max
 = 12, Nr
max
 = 12): relative error curves of nominal 
(solid) and component failures (dotted and dashed).
Together with a voltage source, six available resistors 
were not used in the final circuit. That is why we con-
Figure 11: Synthesized arctan computational circuit 
(Nd
max
 = 12, Nr
max
 = 12), robust to any single component 
high-impedance failure or removal. 
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111
ducted our experiment with tighter device component 
limits. 
3.2 Synthesis with a max of 10 diodes, 10 resistors
The next synthesis was limited to Nd
max
 = 10 and Nr
max
=10. 
We stopped the algorithm after 822 generations (that was 
after 33h).
The outcome is presented in Figure 14. The final topol-
ogy comprises all 10 available diodes. Two resistors 
were not included in the final topology. 
Figure 14: Synthesized arctan computational circuit 
(Nd
max
 = 10, Nr
max
 = 10), robust to any single component 
high-impedance failure or removal.
Circuit performance: nominal topology RMSE is 0.158, 
the worst failure RMSE is 0.270 and the standard distri-
bution of all cases (nominal and failures) is 0.032. One 
can visualize failure ranges in Figure 15 and Figure 16. 
This circuit performs better than the one from the pre-
vious synthesis, according to the three observables. It 
also comprises 2 diodes less and four resistors more. 
Figure 15: Synthesized arctan computational circuit 
(Nd
max
 = 10, Nr
max
 = 10): nominal response (black), 
arctan function (red, dashed-dotted). The range of vari-
ous failure responses is given in blue.
3.3 Synthesis with a max of 8 diodes, 8 resistors
We proceed with Nd
max
 = 8 and Nr
max
= 8. We stopped 
the algorithm after 432 generations (11h).
The outcome is presented in Figure 17. The final topol-
ogy comprises 6 diodes and 6 resistors that can fail dur-
ing the circuit operation. Two resistors and two diodes 
were not included in the final topology. 
Figure 17: Synthesized arctan computational circuit 
(Nd
max
 = 8, Nr
max
 = 8), robust to any single component 
high-impedance failure or removal.
Circuit performance: nominal topology RMSE is 0.149, 
the worst failure RMSE is 0.152 and the standard distri-
bution of all cases (nominal and failures) is 0.017. One 
can visualize failure ranges in Figure 18 and Figure 19.
Figure 16: Synthesized arctan computational circuit 
(Nd
max
 = 10, Nr
max
 = 10): relative error curves of nominal 
(solid) and component failures (dotted and dashed).
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112
Because the algorithm kept solving the problem using 
less than the maximum of available components, we 
proceed and further tighten the Nd
max
 and Nr
max
 criteria. 
3.4 Synthesis with a max of 6 diodes, 6 resistors
We stopped the Nd
max
 = 6 and Nr
max
= 6 synthesis after 
2340 generations (48 h). 
Figure 20 shows the outcome. The final topology uses all 
available diodes and three out of six available resistors.
Circuit performance: nominal topology RMSE is 0.106, 
the worst failure RMSE is 0.110 and the standard distri-
bution of all cases (nominal and failures) is 0.008. One 
can visualize failure ranges in Figure 21 and Figure 22.
3.5 Synthesis with a max of 5 diodes, 5 resistors
The Nd
max
 = 5 and Nr
max
= 5 synthesis was stopped after 
2582 generations (36 h). 
As shown in Figure 23, the final topology comprises all 
available components. 
Although the synthesis comprises only ten critical 
components (plus voltage source and input resistor), 
the performance was not yet diminished. The nominal 
Figure 18: Synthesized arctan computational circuit 
(Nd
max
 = 8, Nr
max
 = 8): nominal response (black), arctan 
function (red, dashed-dotted). The range of various fail-
ure responses is given in blue.
Figure 19: Synthesized arctan computational circuit 
(Nd
max
 = 8, Nr
max
 = 8): relative error curves of nominal 
(solid) and component failures (dotted and dashed).
Figure 20: Synthesized arctan computational circuit 
(Nd
max
 = 6, Nr
max
 = 6), robust to any single component 
high-impedance failure or removal.
Figure 21: Synthesized arctan computational circuit 
(Nd
max
 = 6, Nr
max
 = 6): nominal response (black), arctan 
function (red, dashed-dotted). The range of various fail-
ure responses is given in blue.
Ž. Rojec; Informacije Midem, Vol. 53, No. 2(2023), 103 – 117

113
topology RMSE is 0.108, the worst failure RMSE is 0.165 
and the standard distribution of all cases is 0.022. See 
failure ranges in Figure 24 and Figure 25.
3.6 Synthesis with a max of 4 diodes, 4 resistors
Searching for the bottom limit, we conducted the Nd
max
 = 4 
and Nr
max
= 4 synthesis. We finished it after 1077 generations 
and 12h.
The final topology comprised 4 resistors and 4 diodes 
(Figure 26). 
Figure 26: Synthesized arctan computational circuit 
(Nd
max
 = 4, Nr
max
 = 4), robust to any single component 
high-impedance failure or removal.
The nominal topology RMSE is 0.173, the worst failure 
RMSE is 0.217 and the standard distribution of all cases 
is 0.028. See failure ranges in Figure 27 and Figure 28.
We have discovered, that this synthesis is a probable 
bottom limit in our experiment. To illustrate, how a 
smaller design poorly fits the requirement, we show 
one more synthesis.
Figure 22: Synthesized arctan computational circuit 
(Nd
max
 = 6, Nr
max
 = 6): relative error curves of nominal 
(solid) and component failures (dotted and dashed).
Figure 23: Synthesized arctan computational circuit 
(Nd
max
 = 5, Nr
max
 = 5), robust to any single component 
high-impedance failure or removal.
Figure 24: Synthesized arctan computational circuit 
(Nd
max
 = 5, Nr
max
 = 5): nominal response (black), arctan 
function (red, dashed-dotted). The range of various fail-
ure responses is given in blue.
Figure 25: Synthesized arctan computational circuit 
(Nd
max
 = 5, Nr
max
 = 5): relative error curves of nominal 
(solid) and component failures (dotted and dashed).
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114
3.7 Synthesis with a max of 3 diodes, 3 resistors
Using limits Nd
max
 = 3 and Nr
max
= 3 synthesis, we fin-
ished the search after 3188 generations (11h). 
See Figure 29 for the topology. The nominal topology 
RMSE is 0.497, the worst failure RMSE is 0.507 and the 
standard distribution is 0.010. Failure ranges are shown 
in Figure 30 and Figure 31. We can observe a two-piece 
approximation of the arctan function, which yields 
high RMSE. 
Figure 30: Synthesized arctan computational circuit 
(Nd
max
 = 3, Nr
max
 = 3): nominal response (black), arctan 
function (red, dashed-dotted). The range of various fail-
ure responses is given in blue.
Figure 31: Synthesized arctan computational circuit 
(Nd
max
 = 3, Nr
max
 = 3): relative error curves of nominal 
(solid) and component failures (dotted and dashed).
3.8 Result Summary
Table 1 summarizes the experiment results. Surpris-
ingly, tightening the number of available diodes and 
resistors has led to improved circuit performance in 
Figure 27: Synthesized arctan computational circuit 
(Nd
max
 = 4, Nr
max
 = 4): nominal response (black), arctan 
function (red, dashed-dotted). The range of various fail-
ure responses is given in blue.
Figure 28: Synthesized arctan computational circuit 
(Nd
max
 = 4, Nr
max
 = 4): relative error curves of nominal 
(solid) and component failures (dotted and dashed).
Figure 29: Synthesized arctan computational circuit 
(Nd
max
 = 3, Nr
max
 = 3), robust to any single component 
high-impedance failure or removal.
Ž. Rojec; Informacije Midem, Vol. 53, No. 2(2023), 103 – 117

115
both nominal functionality and robustness, with its 
best at Nd=6, Nr=3. Although initial syntheses involved 
searches over Nd
max
 > 6,   Nr
max
 > 3 topology space, the 
Nd = 6, Nr = 3 best solution was not discovered in these.
Table 2: Results of a conducted experiment. Every row 
is an independent topology synthesis with different 
num. of component limits. The first row is the hand-
made robust design. 
Nd
max
Nr
max
Nd Nr f
nom
f
max
s
f
N/A N/A 10 30 0.116 0.262 0.047
12 12 12 6 0.312 0.370 0.026
10 10 10 8 0.158 0.270 0.032
8 8 6 6 0.149 0.152 0.017
6 6 6 3 0.106 0.110 0.008
5 5 5 5 0.108 0.165 0.022
4 4 4 4 0.173 0.217 0.028
3 3 2 3 0.497 0.507 0.010
There might be several reasons for that phenomenon. 
The first, most obvious one, is an enormous search 
space for topology search. Within one synthesis run, we 
cannot sample every possible circuit, but rather crawl 
the space using the evolutionary search. This is why 
two evolutionary syntheses with the same goal but 
different initial settings might not produce the same 
outcome. 
The second reason is more related specifically to the 
robustness definition in our experiment. As noted, our 
problem definition does not reward circuits with fewer 
components, but rather the opposite. Inclusiveness 
(see 2.3) rewards circuits that electrically include all 
available components to push means of redundancy 
into the circuit and avoid false robustness. During the 
synthesis, while the objectives might already be met 
with requirements, the inclusiveness criteria might 
draw the search toward more included components, 
which makes the search too wide and lasting long. We 
conclude, that with such-defined search problem, the 
hard limits on the topology size and the number of 
available components are key to an efficient small-size 
failure-resilient topology search. 
4 Conclusions
Using the topology synthesis tools, we can find to-
pologies, that exhibit novel properties, such as failure 
tolerance. We showed that failure-resilience in analog 
circuits can be achieved with smaller-than-expected 
topologies, by introducing system-level redundancy 
instead of much more expensive component-level re-
dundancy. Using an evolutionary-based topology syn-
thesis tool, we introduced novel topologies of analog 
arcus tangent circuit. The most compact one comprises 
six diodes, three resistors, a voltage source, and an in-
put resistor. Each of the diodes and the three resistors 
can fail or be removed, with almost no computational 
error. 
Based on this research, we can conclude that the inte-
gration of system redundancy for single-point failures 
was achieved by imposing a strict limitation on the 
maximum size of available components. We showed, 
that to achieve such resilience, surprisingly low num-
ber of electrical components is needed.
In the realm of CMOS design, reducing the number 
of components doesn’t necessarily translate to cost 
savings on its own.  However, we conducted a brief 
analysis of the total resistance for both robust circuits, 
encompassing both hand-crafted and synthesized de-
signs. Total resistance can provide a rough estimate of 
circuit area in certain CMOS processes. For instance, the 
total resistance of a hand-designed circuit (as shown in 
Fig. 4) amounts to approximately 219 k Ω, whereas the 
resistance of the best synthesized circuit totals around 
20 k Ω (a difference of a decade).
Furthermore, reducing the number of components 
can have a direct impact on cost savings in the realm 
of discrete electronics, such as PCBs. In the domain of 
discrete resistors, the resistance value itself does not 
significantly affect the cost of the device, assuming fac-
tors like manufacturer, package, power rating, and tol-
erance remain the same. With this in mind, the minimi-
zation of robust topologies emerges as a pivotal factor 
in achieving cost-effective and highly reliable circuits.
In comparison to previous experiments, this study con-
siders not only diodes, but also resistors to be a possi-
ble point of failure. We experimented with evolutionary 
search for circuits that are robust to both, short-circuit 
and open-circuit failures in all possible failure points 
(components), including some experiments including 
transistors. However, we acknowledge that further in-
vestigation and modified approaches are required to 
address this specific problem effectively.
We believe our work will inspire further practitioners in 
the field of analog circuit topology synthesis. 
5 Supplementary material
The source code of the synthesis tool is available online 
at https://github.com/zigarojec/MatrixCircEvolutions.
Ž. Rojec; Informacije Midem, Vol. 53, No. 2(2023), 103 – 117

116
6 Acknowledgments
I would like to thank my colleagues from the EDA de-
partment of the Faculty of Electrical Engineering, the 
University of Ljubljana for all the support in my work. 
The authors acknowledge the financial support from the 
Slovenian Research and Innovation Agency (research 
core funding No. P2-0246 ICT4QoL—Information and 
Communications Technologies for Quality of Life).
7 Conflict of Interest
We can declare no conflict of interest in this work. 
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Arrived: 17. 02. 2023
Accepted: 06. 10. 2023
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