NEW INTERPOLATION TECHNIQUE FOR HIGHLY
LINEAR CMOS ADC
Shazia Seemi, Mohd Shahiman Sulaiman, Arshad Suhail Farooqui, M.B.I. Reaz Faculty of Engineering, Multimedia University, Cyberjaya, Malaysia
Key words: CMOS ADC, flash, interpolation, high-speed ADC, data converter
Abstract: A new interpolation technique for high speed ADCs is described. Simple summing differential amplifiers operating in continuous time are used as the interpolator. Incorporated in a 1.3Gsample/s 6-bit CMOS Flash with Interpolation Analog-to-Digital Converter and prototyped on CMOS 0.18-um process, measured results indicated a significant improvement in converter linearity compared to other interpolation techniques.
Nova interpolacijska tehnika za zelo linearne CMOS ADC pretvornike
Kjučne besede: CMOS ADC, flash, interpolacija, hitri ADC, podatkovni pretvornik
izvleček:V prispevku opišemo novo interpolacijsko tehniko za zelo hitre ADC pretvornike. Kot interpolator uporabimo enostavne diferencijalne operacijske ojačevalnike v realnem času. Vgrajen v 6-bitni CMOS Flash z 1.3Gvzorcev/s in skupaj z ADC pretvornikom izdelan v 0.18um CMOS tehnologiji; merih/e pretvornika kažejo bistvene izboljšave v njegovi linearnosti v primerjavi z drugimi interpolacisjkimi tehnikami.
1 Introduction
High speed requirements for ADCs (Analog to Digital Converters) in the fields of data storage and digital communication has led to finding new ways to accomplish high speed without sacrifying dynamic and static performance /1/-/2/. Although Flash Architecture is a good choice for high speed ADCs, it has a large number of input amplifiers. This results in a large input capacitance and high power consumption /3/-/5/. An alternative approach is to use Interpolating architecture that has fewer amplifiers at the input stage /3/. Interpolation can be of two types, current mode or voltage mode. Current mode interpolation is based on the summation of currents reflected through current mirrors with different ratios. It is fast but power hungry and is not very precise due to non-idealities in current mirrors /Q/-/7/. Voltage interpolation requires less number of amplifiers, hence, consumes less power. One of the major drawbacks of voltage interpolation is the skew related to the delay from amplifier output to each comparator, i.e. delay from amplifier output to each comparator may not be the same. This delay is primarily due to the series resistance and input capacitance of the comparator. It can be reduced by adding series resistance at the input of the comparator but there could be phase errors when a sinusoidal input is applied. The phase errors degrade comparator's dynamic performance /8/. The interpolation circuit presented in this paper solved the issues faced by voit-age-mode interpolation by significantly reducing the delay mismatches and the phase errors and consuming power less than that of a current-mode interpolation circuit. When implemented in a data converter, the circuit demonstrates
that the new active/voltage-mode interpolation circuit is capable of working at the frequency before this only achievable by current-mode interpolator and with better linearity performance, compared to the work by/6/,/9/,/11/ and /13/. This circuit would allow more active interpolator to be used in the future to achieve low power consumption and high linearity.
2. Interpolator Cell Architecture
Active interpolation circuit is performed by summing the output currents of two differential pairs into resistive loads.
Figure 1 depicts the circuit diagram of the basic interpolator ceil. The two identical differential pairs (M1, M2, M5 and M3, M4, M6) share the same resistive loads Rli and Rl2. The small signal current through Ru is equal to the sum of currents flowing through M1 and M3, and the current through Rl2 is equal to the sum of currents flowing through M2 and M4, The differential output
{Voutp - Voutn) is proportional to the sum of differential input voltages
{Voutp - Voutn ) a (yinpl - Vinnl)+ tyinpl - Vinnl)
Hence, it is proportional to the average of the input voltages. From small-signal analysis, the interpolator output is given as
Voutp - Voutn = S.rAWinpl-nnniy{rwl-nnn2)]
1,4
\M1=I'I2=M3=; M5=M6
\



M2	M3
41
.5
L

\

\
Q
Vinnl Vinp2	Vinn2
Figure 1: Interpolator Cell
The new interpolation technique is performed by arranging the interpolator cells as illustrated in Figure 2. The signals to be interpolated {INn-i, INnand INn+i)are fed into the differential inputs of IAMPn-2 through IAMPn+2. Interpolated outputs are received as OUTn-2 through OUTn+2. The input pairs of IAMPn-2, lAMPn and IAMPn+2 are connected together. This is done in order to maintain the same common mode at all interpolator cell outputs and to equalize the path delays of interpolated and non-interpolated signals. Averaging resistors (Ravg) are used to reduce the effects of device mismatches, as demonstrated by /9/. Besides that, advanced circuit layout techniques such as gate-aligned and common-centroid are used to ensure device symmetry. The combination of active interpolation based on the new interpolator cell, resistive averaging and symmetrical layout techniques results in uniform path delays and fairly low nonlinearities, hence solving problems commonly faced by voltage interpolator.
Figure 2 : Delay equalization using interpolator cell
3. A 6-bit Interpolating ADC
The proposed interpolation scheme is verified by designing a 1.3Gsample/s 6-bit Interpolation with Flash ADC and prototyped on a CMOS 0.18-um CMOS process. Interpolation is performed by a two-stage 16-to-64 interpolator
with resistive terminated averaging. Figure 3 depicts the top segment of the interpolator. Figure 5 shows the ADC block diagram. The averaging and termination resistor values are calculated based on the following formulas
Rtrm = Kvg - Rl
where
Rl is the load resistor of interpolator cell.
Figure 3 : 16-to-64 Interpolator




>
-o-—[>„
o.....
—[>-
-o^-
Figure 5 : ADC Block Diagram
4. Results and Discussion
The whole ADC was prototyped on CMOS 0.18-um 6-met-al 1 -poly process, mounted on a 40-pin ceramic package.
The proposed interpolation technique achieves a phase difference of only 0.05° between the interpolated and non-interpolated outputs. This phase difference is significantly lower than 0.45° obtained using resistive interpolation /8/ and other voltage-mode interpolation techniques. The value of INL is +0.35 LSB at 1.3GSps, which is lower than
other interpolation based designs /6/,/11/. Figure 6 shows a plot of the measured DNL, which varies from +0.15LSB to -0.15LSB. This is the lowest DNL achieved in a CMOS-based high speed ADC {/9/,/12/,/13/) and is certainly the best DNL figure for voltage-mode interpolator. Table 1 compares various types of interpolation with the new technique proposed in this paper. It can be seen that the new technique offers an enormous decrease in pertinent phase delay problem of voltage interpolation. It can also be seen from the table that, the new technique has a better static performance as compared to current interpolation technique.
Figure 6: Measured DNL for ADC based on the new Active Interpolation Technique
Table 1: Comparisons with other Interpolating ADCs
	Voltage	Current	This work
Phase	>=0.45°	<=0.05°	<=0.05°
Delay	>±0.5 LSB	>=±0.4 LSB	±0.15 LSB
DNL	>=±0.5 LSB	>=±1 LSB	±0.35 LSB
INL	Low	High	Low
The whole interpolator for the ADC has a bandwidth of 750 MHz, occupies an active area of O.ISmm^ and consumes 122-mA current from a 1.8-V power supply. A parametric comparison between this design (ADC using Active Interpolation) and other works is summarized in Table 2.
Table 2 : Performance Comparison of ADCs based on various interpolator circuit
	DNL (LSB)	INL (LSB)	Power (mW)	Process (Mil)	Voltage Supply (V)
ADC1300 (This work) 6-bit, l,3Gsample/s	0.15	0,35	612	0.18	1,8
6-bit l,3Gsamp!es/s (Uyttenhove, Steyaert, 2003)	0.42	0.8	600	0,25	1.8 V(A) /2.5 V(D)
6-bit l,6Gsamples/s (Scholtens, Vertregt, 2002)	Approx. 0.25	0.42	340	0,18	1.95(A)/ 2.35(D)
10-bit, 300Mhz (Kimura, Matsuzawa, 1993)	0,4	1	400	I,bipolar	-5.2
5. Conclusion
The new interpolation technique offers extremely low phase delay between the interpolated and the non-interpolated signal, which improves its dynamic performance. At the same time, combination with resistive-averaging network when implemented in an ADC improves the static performance. The ADC's ability to achieve high sampling rate of 1.3Gsample/s while maintaining very low static and dynamic errors makes this interpolation technique suitable for implementation in high speed ADCs.
References
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Shazia Seemi, Mohd Shahiman Sulaiman, Arshad Suhaii Farooqui, M.B.I. Reaz Faculty of Engineering, Multimedia University, 63100 Cyberjaya, Malaysia