INTEGRAL NONLINEARITY DETERMINED BY SELECTION ORDER OF CURRENT ARRAY UNITS IN DA CONVERTERS Roman Benkovic\ Kosta Kovačič^ and Anton Pleteršek^ ^IDS, Ljubljana, Slovenia Faculty of Electrical Engineering - University of Ljubljana, Ljubljana, Slovenia. Key words: CMOS D/A converter, current array, bits-selection-order, thermometric converter Abstract: This paper analyses characteristic of switching-scheme for the curent source array that was used in 14-bit CMOS DA Converter It presents 8-bit thermometric bits-selection-order (BSO) analysis results, where the single bit current source is constructed as a group of two equal cell-units. The BSO order algorithm Vciriss position of tho Qroup, whils ths currsnt-cslls insids ths Qroup sr© siwsys piscsd simGtricslly ovsr ths csntsr of tho isyout srsa Bit-seiection-order value is a decimal code value of the position selection. The final solution is compared with straight horizontal and straight vertical BSO with different error distributions from which posible integral nonlinearity (iNL) of the final product, can be estimated. The analysis of error distribution influence on INL further demonstrates that with bits mixed selection-order INL error is always below 0.05 LSB when average current error is below 1%. Integralna nelinearnost določena z zaporedjem Izbire tokovih virov v DA pretvornikih Kjučne besede: CMOS D/A pretvornik, polje tokovnih virov, zaporedje preklapljanja bitov, termometričen pretvornik Izvleček: Ta članek obravnava karakteristiko preklopne sheme za polje tokovnih virov, ki je bilo uporabljeno v 14-bitnem CMOS digitalno - analognem pretvorniku. Predstavljeni so rezultati analize 8-bitnega termometričnega zaporedja izbire (BSO), kjer je bitni tokovni vir zgrajen kot enota dveh enakovrednih osnovnih tokovnih celic. BSO algoritem spreminja mesto bitnega tokovnega vira, medtem ko sta osnovi tokovni celici vedno postavljeni simetrično, glede na center geometrije polja tokovnih virov. BSC vrednost predstavlja decimalno kodo izbire mesta bitnega tokovnega vira. Integralna nelinearnost (INL) končnega izdelka je ovrednotna z različnimi porazdelitvami napake (Slika 3), glede na vodoraven (Slika 1) in navpičen (Slika 2) BSO algoritem. Analiza vpliva porazdelitve napake na INL kaže, daje INL napaka pri mešanem BSO (Slika 4) vedno pod 0,05 LSB, če je povprečna tokovna napaka pod 1%, 1. Introduction Low integral nonlinearity (INL) in high-bit-count DA Converters is dificult to accomplish with resistor-strings, R2R converters, or binary-weighted current sources /6, 1, 3, 5, 2/. Studies and measurenments indicate that there are non-constant process parameters and region gradient over silicon wafer. In our research we used aproach of two current arrays where each of the array was controlled with thermometer coders. It is therefore our goal to search for the most suitable organisation of an array, number of current units in one step group and, on the most suitable switching-scheme for 8-bit current array. As already explained in /4/, to suppress the linear error, the current step must be split into more than one current units per-step. To minimize the silicon area, only two current units per one unit group were used and placed symet-rically over center of the array. Considering last statement we have 2 x 256 current units. Because of technology isues, seperated functional blocks (sources, switches an selectors) would result in an increased circuit area. In our research our goal is to combine all functions in one cell - current logic block (CLB) cell /8/. CLB cells are composed of: current source with cascode devices, switches to one of two current outputs and digital selection circuit, which determines the state of the switches from horizontal and vertical control signals. Proportion of CLB dimensions is set to 1:10, so the shape of current array was chosen to be 8 x (32 x 2) with additional columns for biasing circuit. 2. First accession Two reference selection-orders of the BSG were used in analysis: horizontal selection-order (Figure 1) and vertical selection-order (Figure 2). For both reference principles, unit group consists of two CLB cells, placed symmetrically to center. To find proper solution, we have to cosider which effects have influence on the resulting INL error and how does the gradient of the process parameters effect the INL error (Figure 3 /7/). 300 250 200 150 100 50 0 100 Position y [urn] Figure 1: Horizontal selection-order. ■noo Position y [urn] Position* [urn] 30^75^00 ^ Figure 2: Vertical selection-order. All the results are found in Figure 5. It is evident that all even order distributions yield zero INL error, as we already assumed when splitting step units in two current cells (CLB's). As can be seen in Figures 3.c and 3.g for 1-D parabolic error distribution INL error results (Figures 5.c and 5.g)are resembling. The main difference isthat in Figure 5.g, vertical 1-D error distribution, the ratio between horizontal an vertical BSO is four times higher than in horizontal 1-D distribution (Figure 5.c) which corresponds to CLB array shape 8 x (32 x 2). Superior results are achieved for vertical selection-order Selected step order goes more frequently from one edge to the other vertically (8 steps) than horizontally (32 steps) which means that final solution will include best results if selections are distributed through all array area as frequently as possible. Simmilar results are presented in Figure 5.e. 3. Proposed solution - mixed selection-order To build more flexible BSO algorithm, it is possible to cover more complex parameters gradient over silicon as well as taking into account any CLB array shape. The BSO anal- Unit Mismatch [%] Poiilionxluml ""' 20( (a) f = 0 >100 00 Po5iliony(umj .^0" Position y (urn] (b) f = X UnitMisr natch [%) 1 .1 1:2 v M \ ■0.2 ■0..J -40 ] Position X (um] ■HOStjjoo (Of = x2 00 Position y [urn] UnitiMismatch [%] Unit Mismatch 1%] Posltionxluml '"^S-JJJ-^,^ (d) f = y (e) f =:: xy --<00 Position y (umj (f)f = x2y Unit Mismatch [%i _xrO0 Position y(ui (g) f = y' (h) f = xy2 (i) f = x2y2 Figure 3: E rror distribution through array area. ysis indicates that the most encauraging results can be achieved by mixing horizontal and vertical bits order. In our research, we proposed bits mixed selection-order (BMSO), as shown in Figure 4. ition y [um] Figure4: Mixed selection-order. Using this approach, it is therefore evident that the random parameter distributions are covered much better, even with only two unit cells building the MSB group.The results of INL errors from Figure 5 show that for most common errors (Figure 5c, 5g and 51), INL error is always below 0.05 LSB when average current error does not exceed 1% thermometric active area (Figure 3). 4. Conclusions Theoretical analysis supported by the predicted and realistic distribution of the process parameters over the silicon area was implemented on integrated digital to analog converter, costructed by the thermometric 8-bit subblock. After the measuring, results will determine resolution for the overall high resolution D/A. Through we can conclude that the complete converter can be covered only by thermometric subblocks, probably including a less complicated autocallibration block. hüilzonul order ----------- verliciil order mixod order (a) f = 0 (b) f = X (c)f = x2 50 100 ISO 200 250 JOO horizontal order ------ vetiical order ....... mixed order (d) f = y 50 !00 150 200 250 300 Code ^"verticil olde! • nnxod order (e) f = xy 250 300 horizomji order -ve.ticjl order • mued order 50 100 ISO 200 250 Code (f)f - x2y horizonwl order----- A mixed order . / \ " ! \ / \ \ / \ / \ \ / \J - (g) f = y' 50 too 150 200 250 300 Code hofizoiilal order -vertical ord^'r • mi