Original scientific paper 149 150 151 152 153 ISSN 0352-9045 Journal of Microelectronics, Electronic Components and Materials Vol. 51, No. 3(2021), September 2021 Revija za mikroelektroniko, elektronske sestavne dele in materiale letnik 51, številka 3(2021), September 2021 UDK 621.3:(53+54+621+66)(05)(497.1)=00 ISSN 0352-9045 Informacije MIDEM 3-2021 Journal of Microelectronics, Electronic Components and Materials VOLUME 51, NO. 3(179), LJUBLJANA, SEPTEMBER 2021 | LETNIK 51, NO. 3(179), LJUBLJANA, SEPTEMBER 2021 Published quarterly (March, June, September, December) by Society for Microelectronics, Electronic Components and Materials - MIDEM. Copyright © 2020. All rights reserved. | Revija izhaja trimesecno (marec, junij, september, december). Izdaja Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale – Društvo MIDEM. Copyright © 2020. Vse pravice pridržane. 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Prispevke iz revije zajema ISI® v naslednje svoje produkte: Sci Search®, Research Alert® in Materials Science Citation Index™. Design | Oblikovanje: Snežana Madic Lešnik; Printed by | tisk: Biro M, Ljubljana; Circulation | Naklada: 1000 issues | izvodov; Slovenia Taxe Percue | Poštnina placana pri pošti 1102 Ljubljana Journal of Microelectronics, Electronic Components and Materials vol. 51, No. 3(2021) Content | Vsebina 151 157 169 181 193 Izvirni znanstveni clanki Ö. Kasar, M. A. Gözel, M. Geçin: 3D natisnjena zasnova mikrovalovne sonde za zaznavanje nivoja vode v PVC ceveh A. Mraz, I. Vaskivskyi, R. Venturini, D. Svetin, Y. Chernolevska, D. Mihailovic: Spominska naprava na podlagi konfiguracije naboja (CCM) – nov pristop do spomina X. Xu, G. Bao, M. Ma, Y. Wang: Strategija upravljanja faznega premika z vec ciljn­imi optimizacijami za dvoaktivni izolirani mostic dvosmernega DC-DC pretvornika M. Nohtanipour, M. H. Maghami, M. Radmehr Metoda umešcanja in usmerjanja za generiranje postavitve operacijskih ojacevalnikov CMOS z uporabo vecciljnega evolucijskega algoritma na osnovi dekompozicije M. Nohtanipour, M. H. Maghami, M. Radmehr: Dolocanje velikosti analognih vezij z uporabo vecciljnega algoritma na osnovi dekompozicije Naslovnica: Formacija polarona, A. Mraz et al. Original scientific papers Ö. Kasar, M. A. Gözel, M. Geçin: 3D Printed Microwave Clamp Probe Design to Detect Water Level in PVC Pipes A. Mraz, I. Vaskivskyi, R. Venturini, D. Svetin, Y. Chernolevska, D. Mihailovic: Charge Configuration Memory (CCM) Device – A Novel Approach to Memory X. Xu, G. Bao, M. Ma, Y. Wang: Multi-Objective Optimization Phase-Shift Control Strategy for Dual-Active-Bridge Isolated Bidirectional DC-DC Converter M. Nohtanipour, M. H. Maghami, M. Radmehr A Placement and Routing Method for Layout Generation of CMOS Operational Amplifiers Using Multi-Objective Evolutionary Algorithm Based on Decomposition M. Nohtanipour, M. H. Maghami, M. Radmehr: Analog Circuits Sizing Using Multi-Objective Evolutionary Algorithm Based on Decomposition Front page: Formation of a polaron, A. Mraz et al. https://doi.org/10.33180/InfMIDEM2021.301 Journal of Microelectronics, Electronic Components and Materials Vol. 51, No. 3(2021), 151 – 155 3D Printed Microwave Clamp Probe Design to Detect Water Level in PVC Pipes Ömer KASAR1, Mahmut Ahmet Gözel2, Mustafa Geçin2 1Department of Electrical and Electronics Engineering, Artvin Çoruh University, Artvin, Turkey 2Department of Electrical and Electronics Engineering, Süleyman Demirel University, Isparta, Turkey Abstract: The permittivity of water is considerably larger than that of air. As the amount of water in PVC water pipes increases, the air will be replaced by water. This means that the electromagnetic environment properties inside the pipe will change. In this study, we proposed a microwave clamp probe designed with a 3D printer that can detect the percentage of water in 50 mm diameter PVC water pipes. The clamp probe allows measurement of return loss from a single port for determining the fill rate of water without any physical intervention from outside the pipe. The clamp, which is structurally similar to a loop antenna, operates at a frequency of 2.45 GHz. As a result of simulations and experimental measurements for different fill percentages of the pipe, the input impedance of the clamp was calculated. Then, an impedance-fill rate graph was created, showing the amount of water in the pipe section according to the impedance values obtained. The impedance seen from the clamp input indicated a linear increase between 40-100 O, according to the 0%, 20%, 50%, 80% and 100% of the water in the pipe. The clamp has a compact structure that can be used as a plug-and-play anywhere on the horizontal. Keywords: Microwave Clamp Probe; Impedance Analysis; PVC Water Pipe; Pipe Fill Rate; Loop Antenna Design 3D natisnjena zasnova mikrovalovne sonde za zaznavanje nivoja vode v PVC ceveh Izvlecek: Permisivnost vode je precej vecja od permisivnosti zraka. Ko se kolicina vode v PVC vodovodnih ceveh poveca, zrak nadomesti voda. To pomeni, da se bodo spremenile lastnosti elektromagnetnega okolja v cevi. V tej študiji smo predlagali mikrovalovno sondo s klešcami, zasnovano s 3D-tiskalnikom, ki lahko zazna odstotek vode v vodovodnih ceveh iz PVC s premerom 50 mm. Objemna sonda omogoca merjenje povratnih izgub iz ene same odprtine za dolocanje stopnje napolnjenosti z vodo brez fizicnega posega z zunanje strani cevi. Sponka, ki je strukturno podobna anteni z zanko, deluje pri frekvenci 2,45 GHz. Na podlagi simulacij in eksperimentalnih meritev za razlicne odstotke napolnjenosti cevi je bila izracunana vhodna impedanca objemke. Nato je bil izdelan graf impedance in stopnje napolnjenosti, ki prikazuje kolicino vode v delu cevi glede na dobljene vrednosti impedance. Impedanca na vhodu klešc je pokazala linearno povecanje med 40 in 100 O glede na 0 %, 20 %, 50 %, 80 % in 100 % vode v cevi. Sponka ima kompaktno strukturo, ki se lahko uporablja kot prikljucek „plug-and-play“ kjer koli na vodoravni površini. Kljucne besede: Mikrovalovna sonda s klešcami; impedancna analiza; PVC vodovodna cev; stopnja napolnjenosti cevi; zasnova antene z zanko * Corresponding Author’s e-mail: omerkasar@artvin.edu.tr 1 Introduction There are several ways to measure the amount of wa­ter in a polyvinyl chloride (PVC) water pipe without visual and physical contact. The technique proposed in this study is based on the “Microwave Measurement Method”. In terms of electromagnetic waves to pene­trate objects, microwave circuits can provide the more sensitivity than low frequency basic electronic circuits cannot reach. The distilled water has high permittivity at the micro­wave frequencies. By the means of this feature, water level detection in a PVC pipe is possible using micro­wave circuits. The permittivity of distilled water is about 80 times higher than air. This means that the level of the distilled water will change the electromagnetic properties of the medium inside the pipe. By selecting a suitable frequency, different input impedances can be determined by changing this water-air ratio. There are very few studies in the literature that aim to determine the amount of water from the outside. They generally reported attenuation in amplitude according to the change in the level of water by designing a kind of power transceiver system by placing an antenna on both sides of the water pipe [1]. In some studies, electro-acoustic circuit methods and capacitive sensor applications have been used [2-7]. In a further applica­tion, computational estimation methods with radio fre­quency circuits were used to determine the amount of different liquids in the plastic water pipe [8]. Few stud­ies such as these shows that methods that can measure the amount of water in PVC pipes with microwave cir­cuits are open to development. In this study, a clamp near field probe was designed. The amount of water in the pipe was tried to be deter­mined by measuring from outside without any physical intervention to a PVC water pipe of known dimensions. Return Loss (RL) obtained from the input of the clamp probe was determined according to the percentage change of water in the pipe. Then, impedance param­eters were analyzed. In the second part of the study, the 3D design of the clamp probe and the calculation of the fullness ratio were mentioned. In the third section, RL-frequency and impedance-frequency analyzes were performed ac­cording to the change in the amount of water in the pipe. Simulation and measurement results were com­pared. In the last section, the importance and original­ity of the study was emphasized. 2 Microwave clamp probe design The designed microwave near field probe is in the form of a clamp that will surround the pipe when installed. The edges of the clamp, which can be opened to both sides with the help of a hinge, overlap when the hinge is closed. Thus, discontinuity will not occur circularly. The clamp is similar to a loop antenna whose ground part is outside the probe and the antenna part is also inside. An SMA connector was connected to one side of the clamp to be measured RL. The clamp was designed for PVC water pipe with 50 mm outer diameter. The inner radius of the clamp is Rin = 26 mm and the outer radius is Rout = 38 mm. Ground and antenna consist of t = 0.1 mm thick copper strip. The width of the clamp is W2 = 17 mm and the width of the antenna is Wprobe = 5. The lengths of the hinge are W1 = 30 mm and L1 = 20 mm. The heights of the clamp are L2 = 93.5 mm and L3 = 76 mm. Figure 1a shows the design parameters of the clamp. The clamp was designed in CST MWS program and fabricated in 3D printer. In additive manufacturing for microwave circuits, fill density is a critical parameter in determining substrate dielectric coefficient. Here the density was selected as 90 %. Thus, according to [1], the permittivity is .clamp = 2.7 and tangential loss is tan d= 0.008. The design and manufacturing of the clamp was given in Figure 1b. a) b) Figure 1: a) Dimensions of Clamp Probe b) Design and Manufactured View of the Clamp Probe. The height of the water in the pipe, whose outer ra­dius is Rp = 25 mm and the inner radius, is RW = 23 mm and the dielectric coefficie is .PVC = 2.8 increases non-linearly with respect to the water fill percentage. In the simulation, “cylindrical tank filling problem” was used to calculate the water height over the cross-sectional area [9]. The area covered by the water was calculated according to Equation (1). (1) where, A is the cross-sectional area of the water in the pipe, RW is the inner radius of the pipe, and h is the height of the water in the pipe. According to 10 % changes of A, the water height was given in Table 1. Table 1: The water height according to fill ratio in pipe. Fill ratio (%) Height (mm) Fill Ratio (%) Height (mm) 10 7.16 60 26.59 20 11.67 70 30.33 30 15.60 80 34.92 40 19.40 90 38.83 50 23 100 46 The most decisive parameter for measuring the amount of water in the pipe using a single port clamp is the per­mittivity (.water = 79.4). As the amount of water increas­es, the air in the pipe (.air = 1) will be replaced by water. According to this displacement, the RL ( S11) seen from the connector of the clamp will increase or decrease. Therefore, the impedance seen from the input will also change. In Figure 2, it is seen that the clamp was ap­plied to the PVC pipe and the water change was mea­sured with Rohde Schwarz FSH6 Spectrum (network) analyzer. In order for the spectrum analyzer to perform network analysis, the device must have a tracking gen­erator. The reflected power must be transferred to the device input with directional coupler. Thus, the RL mea­surement can be made from the spectrum analyzer. 3 Simulations and experimental results The clamp was designed for the frequency of f0 = 2.45 GHz where it provides the inequality of |S11| < - 10 dB [10]. RL vs. frequency graph of the clamp was shown in Figure 3a. Also in Figure 3b, measured according to the change in the percentage of water in the pipe, |S11| graph is given. As seen in Figure 3b, magnitude of S11 for the clamp could not provide high selectivity in determining the amount of water in the pipe [11]. The complex S11 has been trans­formed to impedance (S11) parameter according to Equa­tion (2). Thus, significant range can be achieved between the impedance values of the pipe in different percentages. (2) Since the probe is designed according to Z0 = 50 + j0 . on the frequency f0, the impedance magnitude (|S11|) was calculated according to Equation (3). (3) In impedance calculation at f0, simulation and meas­urement values were close to Z0. In Figures 5a and 5b, it is seen that the magnitude of the |S11| changes accord­ing to different fullness percentages of the pipe. The intermediate occupancy percentages not shown here were not included in the graphic because they were very close to other values. The clamp provides linearity only for certain percentages given. The points marked on Figures 4a and 4b are at Fsim = fmeas = 2.442 GHz fre­quency at which the clamp operates. a) b) Figure 4: |Z11| vs. frequency graph for simulation (a) and measurement (b). The measurement and simulation results were com­bined in Figure 4 which is the graph of the impedance magnitude vs. fill ratio. As shown in the figure, when the occupancy rate is increased from 0% to 100%, |Z11| also increases linearly. The fact that the simulation and measurement were compatible with each other sup­ports this. The minor impedance difference between them consists of connector and path losses in the measurement. 4 Conclusion In this study, a near field probe was designed using a 3D printer to determine the amount of water in PVC water pipes. Thanks to the clamp-shaped design of the probe, measurements can be made from outside the pipe without any physical intervention to the pipe. The amount of water in the pipe can be determined with­out visual contact with the water in the pipe. The clamp resembles a loop antenna, the ground of which is outside the probe, and the antenna is inside. In determining the filling rate of the water in the pipe, the input impedance was calculated by measuring the return loss. By making use of the permittivity of the water approxi­mately 80 times more than that of the air, an imped­ance graph was created according to the filling rate of the water in the pipe. Thus, the amount of water in the pipe can be determined according to the impedance value obtained from the measurement. The clamp ex­hibits linear impedance increase between 40-100 O at 0%, 20%, 50%, 80% and 100% occupancy of the water in the pipe. Measurement and simulation results are very close to each other. The clamp is compact in such a way that it can be used anywhere in the pipe as plug-and-play. The proposed original clamp probe design can also be developed for pipes of different types and thicknesses. 5 Acknowledgement This work was supported by Artvin Çoruh University Scientific Research Projects Coordinator (BAP). Funding Number is 2019.F14.02.01 6 Conflict of interest No conflict of interest has been declared by the au­thors. 7 References 1. H. E. de Lima Ávila, D. J. Pagano, and F. R. de Sou­sa, “Improving the performance of an RF reso­nant cavity water-cut meter using an impedance matching network,” Flow Measurement and In­strumentation, vol. 43, pp. 14-22, 2015. https://doi.org/10.1016/j.flowmeasinst.2015.02.002 2. H. Truong et al., “Capband: Battery-free successive capacitance sensing wristband for hand gesture recognition,” in Proceedings of the 16th ACM Conference on Embedded Networked Sensor Systems, 2018, pp. 54-67. https://doi.org/0.1145/3274783.3274854) 3. R. Dell’ Acqua, “Sensors: A Great Chance for Micro­electronic Technologies”, Informacije MIDEM, 24 (1994) 4, Ljubljana (http://www.midem-drustvo.si/Journal%20papers/MIDEM_24(1994)4p248.pdf) 4. Kasar, Ö. (2020). “Determining The Water Level in Pvc Water Pipes With Micro-Strip Dipole Anten­nas.” Mühendislik Bilimleri ve Tasarim Dergisi, 8(4), 1165-1169. https://doi.org/10.21923/jesd.807389 5. Kasar, Ö, Geçin, M, Gözel, MA. Design and imple­mentation of a 3D printed RF power transceiver clamp to measure the water level in PVC water pipes. Int J RF Microw Comput Aided Eng. 2021; 31:e22644. https://doi.org/10.1002/mmce.22644 6. F. R. M. da Mota, D. J. Pagano, and M. E. Stasiak, “Wa­ter volume fraction estimation in two-phase flow based on electrical capacitance tomometry,” IEEE Sensors Journal, vol. 18, no. 16, pp. 6822-6835, 2018. https://doi.org/10.1109/JSEN.2018.2849684 7. M. Tayyab, M. S. Sharawi, and A. Al-Sarkhi, “A radio frequency sensor array for dielectric constant esti­mation of multiphase oil flow in pipelines,” IEEE Sen­sors Journal, vol. 17, no. 18, pp. 5900-5907, 2017. https://doi.org/10.1109/JSEN.2017.2732164 8. S. Zhang, C. C. Njoku, W. G. Whittow, and J. C. Vardaxoglou, “Novel 3D printed synthetic dielec­tric substrates,” Microwave and Optical Technol­ogy Letters, vol. 57, no. 10, pp. 2344-2346, 2015. https://doi.org/10.1002/mop.29324 9. E. W. Weisstein. “Quarter-Tank Problem.” https://mathworld.wolfram.com/Quarter-TankProblem.html (accessed 19.04.2020). 10 C. A. Balanis, Antenna theory, analysis and design, 3rd ed. New York, USA: Wiley, 2005. (ISBN: 978-605-133-617-6) 11. D. M. Pozar, Microwave Engineering, 3rd ed. New York, USA: Wiley, 2006. (ISBN: 978-0-470-63755-3) Arrived: 01. 01. 2021 Accepted: 27. 07. 2021 How to cite: Ö. Kasar et al., “3D Printed Microwave Clamp Probe Design to Detect Water Level in PVC Pipes”, Inf. Midem-J. Microelectron. Electron. Com­pon. Mater., Vol. 51, No. 3(2021), pp. 151–155 Ö. Kasar et al.; Informacije Midem, Vol. 51, No. 3(2021), 151 – 155 Ö. Kasar et al.; Informacije Midem, Vol. 51, No. 3(2021), 151 – 155 a) b) Figure 3: a) Return Loss of the clamp b) Return Loss ac­cording to amount of the water in pipe. Figure 2: Application of probe to PVC pipe and measurement of water change. Ö. Kasar et al.; Informacije Midem, Vol. 51, No. 3(2021), 151 – 155 Figure 5: The graph of impedance vs fill ratio. Ö. Kasar et al.; Informacije Midem, Vol. 51, No. 3(2021), 151 – 155 Copyright © 2021 by the Authors. This is an open access article dis­tributed under the Creative Com­mons Attribution (CC BY) License (https://creativecom­mons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. https://doi.org/10.33180/InfMIDEM2021.302 Journal of Microelectronics, Electronic Components and Materials Vol. 51, No. 3(2021), 157 – 167 Charge Configuration Memory (CCM) device – a novel approach to memory Anže Mraz1,3, Igor Vaskivskyi1,2, Rok Venturini1,4, Damjan Svetin1,2, Yelyzaveta Chernolevska1, Dragan Mihailovic1,2 1Jozef Stefan Institute, Ljubljana, Slovenia 2CENN Nanocenter, Ljubljana, lovenia 3Faculty for Electrical Engineering, University of Ljubljana, Ljubljana, Slovenia 4Faculty for Mathematics and Physics, University of Ljubljana, Ljubljana, Slovenia Abstract: Computer technologies have advanced unimaginably over the last 70 years, mainly due to scaling of electrical components down to the nanometre regime and their consequential increase in density, speed and performance. Decrease in dimensions also brings about many unwanted side effects, such as increased leakage, heat dissipation and increased cost of production. However, it seems that one of the biggest factors limiting further progress in high-performance computing is the increasing difference in performance between processors and memory units, a so-called processor-memory gap. To increase the efficiency of memory devices, emerging alternative non-volatile memory (NVM) technologies could be introduced, promising high operational speed, low power consumption and high density. This review focuses on a conceptually unique non-volatile Charge Configuration Memory (CCM) device, which is based on resistive switching between different electronic states in a 1T-TaS2 crystal. CCM demonstrates ultrafast switching speed <16 ps, very low switching energy (2.2 fJ/bit), very good endurance and a straightforward design. It operates at cryogenic temperatures, which makes it ideal for integration into emerging cryo-computing and other high-performance computing systems such as superconducting quantum computers. Keywords: Charge Configuration Memory (CCM); 1T-TaS2; Ultrafast devices; Charge density wave (CDW) Spominska naprava na podlagi konfiguracije naboja (CCM) – nov pristop do spomina Izvlecek: Racunalniške tehnologije so v zadnjih 70-tih letih neverjetno napredovale, predvsem zaradi pomanjševanja elektricnih komponent na nanometrske dimenzije in posledicnega povecanja gostote, hitrosti in zmogljivosti racunalniških vezij. Zmanjševanje dimenzij pa vodi tudi do nezaželenih stranskih ucinkov, kot so povecano tokovno pušcanje, visoka disipacija toplote in povecani stroški izdelave. Vendar eden najvecjih vzrokov, ki zavira napredek v visokozmogljivem racunalništvu, je vse vecja razlika v zmogljivosti med procesorji in spominskimi enotami, oz. t. i. procesorsko-spominska vrzel. Vpeljava novih alternativnih trajnih spominskih (NVM) tehnologij bi lahko povecala ucinkovitost, hitrost in gostoto spominskih naprav. Ta pregledni clanek opisuje konceptualno novo trajno spominsko napravo na podlagi konfiguracije naboja (CCM), ki temelji na uporovnem preklapljanju med razlicnimi elektronskimi stanji v kristalu 1T-TaS2. CCM naprava izraža ultra hitre preklopne case <16 ps, zelo nizko preklopno energijo (2.2 fJ/bit), zelo dobro vzdržljivost in preprost dizajn. Obratuje pri kriogenih temperaturah, kar jo naredi idealno za integracijo v uveljavljajoce podrocje krio-racunalništva in ostale visokozmogljive racunalniške sisteme, kot so npr. superprevodni kvantni racunalniki. Kljucne besede: Spomin na podlagi konfiguracije naboja (CCM); 1T-TaS2; Ultra hitre naprave; Val gostote naboja (CDW) * Corresponding Author’s e-mail: anze.mraz@ijs.si 1 Introduction Advances in computer technologies were made pos­sible due to enormous investments of money, time and man-power into research and development of sili­con semiconductor technology, which has been very successful with the constant upgrades despite all the problems it has been facing [1], [2]. However, to sustain this progress in high-performance computing in the long run, it seems that new alternative technologies have to be introduced to either complement the exist­ing ones or to develop new directions. Augmenting Si CMOS with two-dimensional or memristive materials could produce more efficient 2D transistors, sensors and interconnections [3] or even new technological concepts such as biologically inspired computing and on-chip memory and storage [4]. On the field of mem­ory technologies there is much room for improvement, especially when it comes to efficiency and power con­sumption. Standard dynamic random-access memo­ry (DRAM) circuits can use up to 30 % of total power consumption [5] of the whole computer system due to constant refreshing and even static random-access memory (SRAM) circuits suffer losses from leakage [6]. Introduction of non-volatility [7] with the combination of a high energy efficient information storing mecha­nism could result in a memory device of the future. Charge configuration memory (CCM) devices present­ed here rely on reconfiguration of electronic domains between the ground state and excited metastable hid­den (H) state that was recently discovered in a layered transition metal dichalcogenide 1T-TaS2 crystal [8]. Switching between different electronic states results in a big change of electrical resistance of the device. This review briefly explains the origin of the emergent met­astable H state in 1T-TaS2 and discusses its properties in the content of a novel non-volatile memory device based on reconfiguration of charge. 2 1T-TaS2 and the phase diagram The active element in the CCM device is a 1T-TaS2 crys­tal, which belongs to the group of transition metal di­chalcogenides (TMDs) with a chemical formula MX2, where M is a transition metal atom (Ta, Mo, W, Ti…) and X is a chalcogen atom (S, Se or Te). One layer of 1T-TaS2 is made from two triangular lattices of S atoms with a triangular lattice of Ta atoms in between. There are strong covalent bonds inside the layer and weak van der Waals bonds in between the layers. This leads to strong anisotropy of the material which shows in differ­ent mechanical, thermal and electrical characteristics. Pronounced quasi 2D characteristic gives birth to inter­esting new physics not observable in three-dimension­al materials [3], [9]. The phase diagram of 1T-TaS2 is very rich, exhibiting dif­ferent charge-density-wave (CDW) states, Mott transi­tion, polaronic ordering [10], metastable state [8] and even superconductivity at higher pressures [11]. At tem­peratures above 540 K, the material behaves as a simple metal, but when cooled down below that temperature it undergoes a phase transition into an incommensu­rate (IC) CDW due to a combination of Coulomb repul­sion [12] and Fermi surface nesting [13]. At this point the charge density inside the crystal is modulated and the crystal lattice is displaced, but the two of them are not aligned. Because of the frustration between the IC CDW and the underlying lattice, the state transforms into a nearly commensurate (NC) CDW at a temperature around 340 K. Electrical resistance of the material in NC state is several times higher than in the metallic state but it is still well conducting [11]. Steady state electri­cal resistance of the material is shown in Fig. 1a, where the black curve represents resistance upon cooling from room temperature. NC CDW state is made from a hex­agonal array of polaron clusters, separated with domain walls, as is sketched in Fig. 1f (inset to Fig. 1a). A polaron consists of a central electron localised on a Ta atom with 12 surrounding Ta atoms displaced toward the centre [14], [15], which forms a star formation (Fig. 1b). Upon slow cooling below 160-180 K, domain walls between polaron clusters disappear and a fully commensurate (C) CDW polaronic lattice forms. Fig. 1e (inset to Fig. 1a) shows a sketch of the C state and Fig. 1c shows an image of the C state using a scanning tunnelling microscope (STM). Each bright spot represents an individual polaron and the dark spots are impurities in the lattice. C CDW state is a Mott insulator with a gap of 0.1 eV [13]. This leads to a jump in electrical resistance of the sample at ~160-180 K, which further increases as the temperature is decreased to ~20 K, as can be seen on Fig. 1a (black curve). 20 K or lower is a typical working temperature for CCM devices. If the C state is heated up from 20 K to room temperature, the resistance curve backtracks to ~100 K but then follows the red curve and draws a hys­teresis until ~220 K. The material then transitions into a so-called stripped ordered triclinic (T) phase [14] before returning to the NC state at ~280 K. If the C state is excited by either an optical [8] or an electrical [16] pulse, the material switches to a meta­stable hidden (H) state, which is stable at low tempera­tures (<20 K). When this transition occurs, the electri­cal resistance of the sample drops sharply because the H state is metallic. Transition from the C to the H state is called a Write (W) process, which is denoted with a green arrow in Fig. 1a. The contrast in resistance be­tween the two states is dependent on the sample and on the geometries of the CCM device and can be up to three orders of magnitude big [8]. Upon heating the H state (red curve), the resistance remains approximately constant up to 50 K, at which point it starts to increase and merges with the virgin re­sistance curve (black) at ~100 K. If the sample is cooled down at that point, the resistance follows the virgin curve, meaning the H state is completely reversed into the C state. The transition from the H to the C state is called an Erase (E) process and is denoted in Fig. 1a with a blue curve. The H state can also be erased via Joule’s heating of the material using a train of optical pulses [8] or a longer electrical pulse [16], [17]. Examining the H state microscopically using an STM, a distinct patchy pattern can be observed with domains of polarons and domain walls separating them [18], as seen in Fig. 1d. Domain walls arise because the extra injected charge introduced by the external excitation (optical or electrical) is accommodated in the C CDW structure. The charge periodicity of the metastable state (which determines the domain size) originates from a free energy minimum which arises from the competition of Coulomb interaction between domain walls and the energy of the domain wall crossings in the CDW state [8]. The conduction mechanism of the metallic H state is not yet completely understood, but scanning tunnelling spectroscopy (STS) reveals that both polarons and domain walls are conducting [19]. This means that the conduction is not percolative as in typical memristors [20], but is collective in nature. By analysing the junctions between domain walls in the STM image (Fig. 1d) it is discovered that some of them act as non-trivial topological defects (NTTDs), which means they can only be annihilated by an antide­fect with equal and opposite winding number. These NTTDs contribute to the non-volatility of the LO state [17], [18] at low temperatures. The pattern of domain walls in the H state is also always different when switch­ing between the C and the H state. This is important for reproducibility and endurance of the devices, because it means that pinning by lattice defects or impurities does not play a significant role in the switching pro­cess. Endurance measurement shows that the devices are very durable and can survive well over 106 cycles of W and E with remarkable stability throughout [17]. During the transition from the C to the H state (W pro­cess) only the charges are reconfigured. This switching is therefore purely electronic and predicted to occur on an electronic timescale (~300 fs). The transition time of the W process was measured using coherent time-resolved femtosecond spectroscopy by Ravnik et al [21] in a pump-probe experiment at 160 K. At this temperature the lifetime of the H state is ~0.1 ms [22]. This allows for a stroboscopic measurement with 1 kHz repetition rate laser, which means that before each next laser pulse, the H state has completely relaxed back to the C state. It was determined that the transi­tion time of the W process is ~400 fs, which confirms the assumption. This shows that the W process is inher­ently extremely fast and is not the limiting factor when it comes to the speed of the CCM device. The E pro­cess on the other hand is predominantly thermal and slower and requires more effort and planning to reach optimal operation. 3 Operational properties of the CCM device 3.1 Current-voltage characteristics A typical CCM device is shown in Fig. 2a with a 1T-TaS2 flake on Si/SiO2 substrate and metal electrodes fabricated on top using electron-beam lithography. Current-voltage (I-V) characteristics of such a CCM de­vice is shown in Fig. 2b and c for both the Write and Erase process respectively, measured at 20 K. Since the C state is the insulating state, it is denoted as the high resistance state (HI) and H state is metallic, so it is called the low resistance state (LO). For a W process, CCM is originally in the HI state. As the current incrementally increases, the voltage follows the HI curve (black) in Fig. 2b. It is linear at first but becomes non-linear at higher currents. Non-linearity is fitted as (1) Voltage increases until a certain threshold of current is reached, at which point a switch to the LO state occurs, and the voltage drops. As the current is decreased back to zero, voltage follows a linear LO curve (red). E pro­cess is done similarly, only that the device starts from the LO state (Fig. 2c). As the current incrementally in­creases, the voltage follows a linear LO curve (red) until a certain threshold is reached, at which point a switch to the HI state occurs and the voltage jumps. As the current is decreased the voltage follows the non-linear HI curve back (black). The threshold values for W and E processes can vary slightly between devices but can be controlled with proper planning. Read operation (R) is straightforward, any read current can be used as long as it’s low enough to not trigger the W or E operation. The HI state shows clear non-linear behaviour which cannot be fitted with a tunnelling diode equation or attributed to CDW sliding behaviour [16], [23]. Steps or jumps in voltage in the HI state are case depend­ant and are attributed to complex tunnelling dynam­ics between polarons and slight rearrangements of the polaronic structure [16], [24] with similar resistance. However, the CCM device is not meant to be driven in this manner, but rather by using a single W and E pulse above the threshold value to switch between the HI and LO state. In devices that are well characterized, the potentially unknown region of the I-V characteristics can be easily avoided. 3.2 Writing process W process can be observed in real time with the use of an oscilloscope connected in parallel to a CCM element as shown on a scheme in Fig. 3a. The 1T-TaS2 flake used was 65 nm thick and 0.9 um wide, with Au electrodes fabricated over the flake and the gap between the elec­trodes ~280 nm. In Fig. 3b we see the time evolution of voltage across the CCM device when 50 ns long W pulses of varying amplitude are applied on the elec­trodes at 100 K. At low amplitudes the voltage remains constant over the entire duration of the pulse with the rise time tR~7.4 ns defined by the RC constant of the circuit. At a certain threshold (~0.55 V) the voltage across the CCM drops, which is a result of a W process from HI to LO state and remains there till the end of the pulse. If the area under the voltage curves (coloured in Fig. 3b) is integrated and the W energies are calculated using the equation , where t1 is the beginning of the pulse, t2 is the time where the volt­age drops and R is the resistance of the sample, it turns out that the energies for different amplitudes are not the same, meaning the switching does not occur due to cumulative heating. This is also confirmed in Fig. 3c where there is a clear decrease in W energy as the switching pulses are shortened from 400 ns to 9 ns. If switching was only due to heating, the W energy would be constant across all the pulse widths. The mechanism for W switching is not yet completely understood but it seems to be a combination of applied electric field and charge injection into the sample [8], [16], however heating might play a role to a certain degree. The same kind of switching dynamics as in Fig. 3b was also observed using longer W pulses [16]. It was shown that the range of possible W pulse width is very wide, from 100 ms down to 16 ps [16], [17]. For ultrafast puls­es the electrodes were fabricated in a transmission line configuration to ensure good transmission. W energy calculated with a 16 ps FWHM (rise time ~11 ps) pulse was EW = 2.2 fJ/bit [17], where the W voltage was 1 V and entire pulse width was used in the equation. One way to decrease the W energy is scaling of the CCM device. Scaling of dimensions directly affects the voltage needed to switch the state of the CCM device. If the dimensions of the device are smaller, there’s physi­cally less polarons or domain walls that are required to reconfigure, meaning less injected charge is needed plus the applied electric field is increased, assuming both are vital. W voltage scales linearly with the gap be­tween the electrodes fabricated on devices on a range of 4 µm – 60 nm, with the smallest W voltage achieved being 0.3 V [17]. 3.3 Erase process When considering a non-volatile memory device, the information stored has to remain unchanged for a long period of time, ideally indefinitely. HI state of the CCM device is not problematic since it is the ground state. The LO state however is a metastable state which oc­curs under non-equilibrium conditions, but it can still be extremely long lasting under right conditions. The switching of the LO state back into the HI state is pre­sumed to occur due to thermally activated domain re­configuration, meaning the lower the ambient temper­ature, the more stable the LO state is, or in other terms, the longer the lifetime of the LO state tLO is. LO state is completely stable or non-volatile at temperatures below 20 K, so E process is induced by applying an E pulse, which can be on a time scale of µs-ms with an amplitude <0.5 V [16], [17]. E pulse effectively heats up the CCM element, which than switches back into to the HI state. The E process can be greatly optimized with proper thermal management by including an extra heating element as was demonstrated in phase change memory (PCM) devices, where high heating is crucial for operation [25]. It is also presumed that in a bigger scale CCM device, E process would be done in blocks, meaning that slower E process would not pose such a disadvantage. At temperatures above 20 K, the LO state slowly relaxes back into the HI state by itself with a certain relaxation rate (r = 1/tLO) [22]. The relaxation dynamic was inves­tigated by switching a CCM device from HI to LO state and observing the time evolution of the electrical re­sistance at a fixed temperature, which is shown in Fig. 4a (experiment - dotted line, exponential fit – dashed line). Speed of relaxation increases quickly with in­creasing temperature and becomes comparable to the measurement time at temperatures above 60 K. At 150 K the relaxation rate is a few µs, which can be observed on the oscilloscope by adjusting the period of W pulse train and observing the voltage across the CCM (simi­larly to Fig. 3b). This means that the CCM device can be written to the LO state at any temperature bellow the NC-C transition (~160-180 K), however the stability of the LO state is heavily influenced by the tempera­ture. At 150 K it takes only a few µs for the LO state to completely relax back to the HI state after which the CCM device is ready to be written again. CCM device can thus also be used in the volatile regime (above 20 K), but have to be refreshed accordingly, much like dy­namic random-access memory (DRAM). To obtain relaxation dynamics in Fig. 4a electrical pulses were used. When using laser pulses to write the CCM’s state, the relaxation dynamic of the LO state looks simi­lar, however the comparison of the relaxation rate r be­tween the two cases shows quite a big difference. This can be seen when comparing the relaxation rate for op­tical (blue circles) and current (black squares) switching of a CCM device on a sapphire substrate in an Arrhenius plot in Fig. 4b. The r of the optical switching is much low­er than the r of the current switching at a certain tem­perature. This is most likely attributed to extra heating provided by the current pulse used for switching, which is 5 µs long, compared to a 35 fs laser pulse. This means that the effective temperature is higher in the current switching compared to the optical switching. Choice of sample substrate also affects the relaxation rate due to different expansion coefficients and conse­quential strain on the 1T-TaS2 sample [22] (Fig. 4b). The tested substrates were sapphire, MgO, quartz and Si/SiO2 with the imposed tensile strain De being 0.19 %, 0.13 % for sapphire and MgO respectively and 0.03 % for quartz and Si/SiO2 at 50 K. Even though De is quite small, the effect seems to be rather large when comparing the relaxation rate for the case of sapphire and quartz. When the lattice expands because of the tensile strain of the substrate, the CDW has to rearrange to maintain com­mensurability and that can lead to extra domain walls being introduced. And since the relaxation from the H to the C state involves annihilation of domain walls, a higher tensile strain leads to higher activation energies EA and consequentially to a lower relaxation rate. Ex­tracting the activation energy EA from fitting an Arrhe­nius law in Fig. 4b, the values are between EA = 280-2300 K, where the highest activation energy belongs to the substrate with the highest De (sapphire). But it appears that the EA also varies between different samples, implying that some other parameters such as nanofabricated electrodes, local defects and impurities affect the stability of the H state. By using a proper sub­strate, one could manipulate and tune the stability of the H state while ensuring a fast E process in an ultrafast non-volatile memory device. Different substrate strains may have an effect on the way multiple layers of 1T-TaS2 crystal stack inside a CCM de­vice. It is not yet clear how or to what extent the stacking of layers affects the switching dynamics. The measure­ments done on a device in a vertical/crossbar (out-of-plane) configuration show qualitatively similar behav­iour to a more typical planar (in-plane) device [26]. There is a big discrepancy in the resistivity and the switching threshold for electric field between the two cases, where the vertical device has ~1000 times higher resistivity and ~100 times higher electric field threshold. However, the threshold electrical current is almost the same for both configurations as well as the relaxation rate of the LO state with the extracted activation energy EA = 650±100 K [26] that matches with previous values for planar de­vices [22]. This points to the fact that switching between different electronic configurations inside the 1T-TaS2 crystal combines the effect of in-plane polaronic order reconfiguration as well as re-stacking between indi­vidual layers. In the case of typical planar devices [16], [17], [22] (Fig. 2a, 3b) the current is probably not being confined only to the top layer anyway, especially since the electrodes are fabricated over the edge of the crys­tal and make contact on the side as well. Therefore, both the in-plane and out-of-plane physics contribute to the electrical behaviour of the devices. Still, the CCM devices in crossbar configuration are very promising for larger scale integration since they allow for bigger density than the planar version. They are also easier to be scaled to lower dimensions, because the gap between the electrodes is determined only by the thickness of the 1T-TaS2 flake and is therefore not limited by the complicated lithographic procedure. However, very thin flakes (< 10 nm) do not neces­sarily exhibit the NC CDW – C CDW transition, which means they don’t develop the insulating behaviour at low temperatures (Fig. 1a, black curve) and cannot be used as a memory device. Instead their resistance follows a straight line into a so called supercooled NC CDW state as they are cooled down [27]. This problem can be mitigated by ensuring a very slow cooling rate [27] or with capping of the device to prevent oxidation, which could be responsible for pining of the CDW [28] and consequential suppression of the NC-C transition. 4 Conclusions and Outlook In summary, CCM devices show ultrafast (16 ps FWHM) [17], energy efficient operation (2.2 fJ/bit) [17], non-vol­atility at cryogenic temperatures [22] and very good en­durance (>106 cycles) [17], which is very important for electronic applications. The basic memory operation is provided through electronic switching between two distinct resistance states (HI and LO), but intermediate states are also available, potentially allowing one CCM element to be used as a multibit device [16], [26]. The overall structure of the device is also very simple, and it can be fabricated in a planar or vertical configuration to allow for easier integration into bigger systems. Erase process is currently the limiting factor when it comes to speed and energy consumption of the device, however with proper thermal management it can be improved significantly as demonstrated in PCM devices [25]. Role of heating in the switching operation is also not yet un­derstood completely. Among conventional CMOS memory technologies the most widely spread are the SRAM and DRAM technolo­gies with write times on the nanosecond timescale and write energies from 100 fJ/bit to 1 pj/bit respectively [29]. They have very good endurance and very high level of integration, however their memory operation is still volatile, which makes them inherently more dissi­pative and less economical. Among non-volatile mem­ory devices, the most popular are the solid state drives (SSD), which usually rely on NAND Flash technology for memory operation, but at this point they are not fast nor durable enough to replace SRAM or DRAM yet [30]. CCM devices are able to achieve faster write times (16 ps) and more energy efficient operation (2.2 fJ/bit)[17] compared to the SRAM or DRAM devices, while also having the advantage of non-volatility. However, CCM devices are currently still in the prototype stage and the level of integration and device density is still much lower compared to conventional CMOS devices. There are many alternative non-volatile memory tech­nologies besides the CCM, such as Magnetoelectric RAM (MeRAM), Spin-Transfer Torque RAM (STT-RAM) and Phase Change Memory (PCM) devices, among which the lowest energy per bit is reported in electric-field-controlled switching in magnetic tunnel junctions (MeRAM) with EW = 30 – 40 fj/bit [31], followed closely by the spin-tranfer torque switching in CoFeB free lay­ers (STT-RAM) with EW = 44 fJ/bit [32]. PCM devices have higher switching energies (>2.5 pJ) and also slower op­erational speed (~500 ps) [25], because they rely on relatively slow ionic recrystallization of their active ma­terial. Thus, compared to others, CCM seems to be well under way for such a young technology. Since CCM devices operate extremely well at cryogenic temperatures, they are very attractive to be used in cryocomputer systems such as superconducting Rap­id Single-Flux-Quantum (RSFQ) [33], [34] systems and quantum processors, which are lacking an ultrafast and energy-efficient cryogenic memory device [35]. Inte­gration of CCM into RSFQ logic is possible using a super­conducting element called a nanocryotron (nTron) [36] that is sensitive enough to be triggered by extremely small SFQ pulses (~2 mVps) yet can still produce up to 8 V of output voltage in only ~100 ps [36], [37], which is more than sufficient to drive a CCM device. Integrat­ing SRAM or DRAM into superconducting circuits was also reported, but in order to drive CMOS logic, multi­ple Josephson junction stacks and amplification stages have to be used, which increases power dissipation and can negatively affect cryocomputer’s operation [38], [39]. By replacing the typical voltage amplifiers in such hybrid Josephson-CMOS circuits with nTron drivers, the power consumption can be reduced by an order of magnitude [40], however the non-volatility of the memory is still not realized with this approach, while on the other hand it could be solved using CCM devic­es. Superconducting computer systems are considered as the solution to the power consumption problem current computers are facing and CCM devices could present a boost in their development. 5 Methods 5.1 Synthesis of 1T-TaS2 Chemical vapour transport (CVT) method [41] is mostly used to grow high quality bulk 1T-TaS2 and other TMD crystals. This is done in an evacuated and sealed quartz ampule which is inserted into a furnace with a temper­ature gradient from T2~850 K to T1~750 K (Fig 5a) [41]. For 1T-TaS2, a mixture of solid sulphur, tantalum and iodine is inserted into the ampule. Iodine serves as a transport agent that forms complexes with the evapo­rated materials and transports them to the colder side of the ampule, where the crystal grows. The ampule is quenched after the growth in order to freeze the 1T polytype of TaS2 which otherwise isn’t stable at room temperature. The result of CVT growth are millimetre big high-quality crystals (Fig. 5b) which have to be me­chanically exfoliated in order to acquire thin films used in CCM devices. After that, laser or electron beam (e-beam) lithography is performed to fabricate metallic contacts. A more scalable and integrable approach to growing TaS2 for device applications is by the Molecular Beam Epitaxy (MBE) method, which is schematically pre­sented in Fig. 5c [42]. MBE method is used for epitaxial thin-film deposition and is widely used in the fabrica­tion process of semiconductor devices. In the case of 1T-TaS2, Ta and S source is needed in an ultrahigh vacuum chamber. The LSAT substrate is preheated to ~1000 K to ensure the growth of 1T polytype and the thickness is monitored in situ. After the growth of the sample is complete, the sample is quenched to freeze the 1T polytype. Result of the growth is a thin 1T-TaS2 film (10-30 nm) fairly uniform over the entire substrate. Atomic force microscope (AFM) image of the MBE grown film is shown in Fig. 5d. To produce CCM devices, the MBE grown films would have to be patterned accordingly using etching and metal contacts would have to be fabricated using laser or e-beam lithography. 6 Acknowledgment. This project has received funding from the the EU-H2020 research and innovation programme under grant agreement No 654360 having benefited from the access provided by Paul Scherrer Institute in Villigen, Switzerland within the framework of the NFFA-Europe Transnational Access Activity. We thank for the support from the Slovenian Research Agency (P1-0040, A.M. to PR-08972, R.V. to No. PR-10496, D.S. to I0-0005), Slo­vene Ministry of Science (Raziskovalci-2.1-IJS-952005), ERC AdG (GA320602) and ERC PoC (GA7677176). We thank the CENN Nanocenter for the use of an AFM, LDI and MBE. 7 Conflicts of interest. The authors declare no conflict of interest. 8 References 1. H. Radamson et al., ‘The Challenges of Advanced CMOS Process from 2D to 3D’, Applied Sciences, vol. 7, no. 10, p. 1047, Oct. 2017, https://doi.org/10.3390/app7101047. 2. N. Z. Haron and S. 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Yoshikawa, ‘Josephson-CMOS Hybrid Memory With Nanocryotrons’, IEEE Trans. Appl. Su­percond., vol. 27, no. 4, pp. 1–4, Jun. 2017, https://doi.org/10.1109/TASC.2016.2646929. 41. P. Schmidt, M. Binnewies, R. Glaum, and M. Schmidt, ‘Chemical Vapor Transport Reactions–Methods, Materials, Modeling’, in Advanced Topics on Crystal Growth, S. Ferreira, Ed. InTech, 2013. https://doi.org/10.5772/55547. 42. S. Tardif, ‘Nanocolonnes de GeMn : propriétés magnétiques et structurales ŕ la lumičre du synchrotron’, https://tel.archives-ouvertes.fr/tel-00585130/. Arrived: 05. 05. 2021 Accepted: 27. 07. 2021 How to cite: A. Mraz et al., “Charge Configuration Memory (CCM) device – a novel approach to memory”, Inf. Midem-J. Microelectron. Electron. Com­pon. Mater., Vol. 51, No. 3(2021), pp. 157–167 A. Mraz et al.; Informacije Midem, Vol. 51, No. 3(2021), 157 – 167 Figure 1: Phase diagram of 1T-TaS2. a) Plot of resistance versus temperature. Black curve represents cooling of the CCM device and red curve represents heating after switching to the H state. Write (W) process is denoted with a green arrow, erase (E) process is denoted with a blue arrow. b) Formation of a polaron. 12 surround­ing Ta atoms are slightly displaced toward the middle one. c) An STM image of the C state with an ordered polaronic structure. d) An STM image of the H state with patches of polarons seperated with domain walls. e) Sketch of the C state. f) Sketch of the NC state. A. Mraz et al.; Informacije Midem, Vol. 51, No. 3(2021), 157 – 167 A. Mraz et al.; Informacije Midem, Vol. 51, No. 3(2021), 157 – 167 Figure 2: a) Typical CCM device. 1T-TaS2 crystal on Si/SiO2 substrate with golden electrodes fabricated on top. b and c) I-V characteristics of the W and E process respectively. A. Mraz et al.; Informacije Midem, Vol. 51, No. 3(2021), 157 – 167 Figure 3: a) Schematic of the experiment with a pulse generator on one side of the CCM device and an os­ciloscope in parallel. b) Voltage across the CCM device observed during electrical pulsing. The drop in voltage occurs because the CCM device switches from HI to LO state. Shaded area was used in the W energy calcula­tion. c) Scaling of the W energy as a function of applied pulse width. A. Mraz et al.; Informacije Midem, Vol. 51, No. 3(2021), 157 – 167 Figure 4: a) Plot of resistance versus time, showing re­laxation of the LO state at different temperatures, from which the lifetimes are extracted. The relaxation time at 40 K is ~10 minutes, while at 55 K it’s ~2 minutes. Dotted line is the experimental data, dashed line is the exponential fit. b) Arrhenius plot of relaxation rate for different substrates and different excitation methods (optical or electrical). A. Mraz et al.; Informacije Midem, Vol. 51, No. 3(2021), 157 – 167 A. Mraz et al.; Informacije Midem, Vol. 51, No. 3(2021), 157 – 167 Figure 5: Growth of TaS2. a) Chemical vapour transport (CVT) reaction in an ampule. Adopted from ref.[41] b) Image of a milimetre big TaS2 crystal grown by CVT. c) Molecular beam epitaxy reaction in a vacuum cham­ber. Adopted from ref.[42] d) Atomic force microscope image of TaS2 surface, grown in an MBE machine. A. Mraz et al.; Informacije Midem, Vol. 51, No. 3(2021), 157 – 167 A. Mraz et al.; Informacije Midem, Vol. 51, No. 3(2021), 157 – 167 A. Mraz et al.; Informacije Midem, Vol. 51, No. 3(2021), 157 – 167 Copyright © 2021 by the Authors. This is an open access article dis­tributed under the Creative Com­mons Attribution (CC BY) License (https://creativecom­mons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. https://doi.org/10.33180/InfMIDEM2021.303 Journal of Microelectronics, Electronic Components and Materials Vol. 51, No. 3(2021), 169 – 179 Multi-Objective Optimization Phase-Shift Control Strategy for Dual-Active-Bridge Isolated Bidirectional DC-DC Converter Xiaodong Xu1, Guangqing Bao1, Ming Ma2, Yuewu Wang3 1College of Electrical and Information Engineering, Lanzhou University of Technology, Lanzhou, China 2Wind Power Technology Center, State Grid Gansu Electric Power Corporation, Lanzhou, China 3School of Electrical Engineering and Automation, Harbin Institute of Technology, Harbin, China Abstract: The dual-active-bridge isolated bidirectional DC-DC converter (DAB-IBDC) is a crucial device for galvanic isolation, voltage conversion, power transfer, and bus connection in the DC power conversion systems. Phase-shift modulation is an effective method to improve DAB-IBDC performance. However, the phase-shift control strategies in the previous literatures mainly focus on optimizing the characteristic of DAB-IBDC in a single aspect. In this paper, to optimize high-frequency-link (HFL) reactive power, current stress, and efficiency simultaneously, a new multi-objective optimization strategy based on dual-phase-shift (DPS) control is proposed. The power characterization, current stress, and power loss of the DAB-IBDC are analyzed. Besides, both the control principle and framework of the proposed control strategy are described in detail. Finally, the experiment results obtained from an established DAB-IBDC prototype are presented to verify the correctness and superiority of the proposed strategy. Keywords: dual-active-bridge; multi-objective optimization; DPS control strategy; electrical performance Strategija upravljanja faznega premika z vec ciljnimi optimizacijami za dvoaktivni izolirani mostic dvosmernega DC-DC pretvornika Izvlecek: Izolirani dvosmerni DC-DC (DAB-IBDC) pretvornik z dvoaktivnim mosticem je kljucna naprava za galvansko izolacijo, pretvorbo napetosti, prenos moci in povezavo vodila v sistemih za pretvorbo enosmerne energije. Modulacija s faznim zamikom je ucinkovita metoda za izboljšanje delovanja DAB-IBDC. Vendar se strategije nadzora s faznim zamikom v dosedanji literaturi osredotocajo predvsem na optimizacijo znacilnosti DAB-IBDC z enega vidika. V tem clanku je za hkratno optimizacijo jalove moci, tokovne napetosti in ucinkovitosti visokofrekvencne povezave (HFL) predlagana nova vecpredmetna strategija optimizacije, ki temelji na nadzoru z dvojnim faznim zamikom (DPS). Analizirane so znacilnosti moci, tokovne obremenitve in izgube moci DAB-IBDC. Poleg tega sta podrobno opisana tako nacelo krmiljenja kot tudi okvir predlagane strategije krmiljenja. Na koncu so predstavljeni rezultati poskusov, pridobljeni iz vzpostavljenega prototipa DAB-IBDC, s katerimi sta preverjeni pravilnost in superiornost predlagane strategije. Kljucne besede: dvojni aktivni mostic; vecnamenska optimizacija; strategija krmiljenja DPS; elektricna zmogljivost * Corresponding Author’s e-mail: gqbao@lut.cn 1 Introduction With the wide application of direct-current (DC) renew­able power sources, DC loads, and storage equipment, DC power conversion systems (PCS) have considerable potential for engineering applications [1-4]. With the development of power electronics, isolated bidirec­tional DC-DC converters (IBDCs) have become popular for galvanic isolation, voltage conversion, and power transfer in DC PCS [5-6]. Among various IBDCs, the du­al-active-bridge (DAB) IBDC with merits of symmetric topology and control structure, the convenience of im­plement zero voltage switching for switches, bidirec­tional power transmission, and cascaded modularity, has been studied and applied in the DC PCS. Thanks to the development of novel power devices and technol­ogies, the DAB-IBDC performance is greatly improved under the great efforts of researchers and engineers. The improvements in DAB-IBDC also promote the de­velopment of PCS, so bringing lots of technical advan­tages [7-10]. The improvements of DAB-IBDC in the previous litera­tures mainly focus on the topology design and opti­mization, mathematical model derivation, phase-shift modulation strategies, converter control schemes, and soft-switching realization [11-15]. Particularly, the phase-shift control is an effective method to optimize the DAB-IBDC performance [16]. The phase-shift con­trol strategies can be categorized into single-phase-shift (SPS), extended-phase-shift (EPS), dual-phase-shift (DPS), and triple-phase-shift (TPS). With DAB configurations each full bridge is driven with specific phase-shift. While these phase-shifts can differ in DPS they are equal and referred as inner phase-shift, and phase-shift between each full bridge is the outer phase-shift [7]. The SPS has one degree of freedom with outer phase-shift, and the EPS and DPS have two degrees of freedom with inner phase-shift and outer phase-shift, while the TPS has three degrees of freedom with two different inner phase-shifts and an outer phase-shift. In [17], an improved asymmetric modulation for both-side of DAB-IBDC is proposed, enabling the smooth transac­tion during steady-state operation and minimizing the transient time regardless of equivalent resistance of in­ductor. In [18], optimized phase-shift modulations are proposed to accelerate the transient response and sup­press the DC bias during transient process. In [19-20], a mathematical model of current stress for DAB-IBDC is established, and the minimum current stresses are achieved under DPS and TPS control strategies, respec­tively. In [21-22], the DAB-IBDCs with soft-switching operation during whole operating range are analyzed, expanding the zero-voltage switching (ZVS) range and promoting efficiency. In [23-24], the power loss and efficiency models are established, and the efficiency optimized modulation schemes based on phase-shift control are developed. Other phase-shift modulation strategies are also proposed in [25-28] to eliminate re­active power, reduce the peak and root-mean-square (RMS) values of HFL current, and enhance light-load performance for DAB-IBDC, respectively. Moreover, the phase-shift strategies with quasi-square-wave, trian­gle-wave and sine-wave modulation are investigated for improving performance under varied modulation methods [29-30]. Besides, the TPS control strategy is an efficient method to improve the performance of DAB [31-33]. The phase-shift control strategies in the previous lit­eratures have improved the performance of DAB-IBDC effectively. However, most existing phase-shift control strategies only realize the performance optimization in a single aspect (e.g., current stress, reactive power elimination, ZVS behavior, or efficiency performance of DAB-IBDC). The phase-shift control strategy for multi-objective optimization, i.e., simultaneously optimizes various characteristics of DAB-IBDC, has not been considered and discussed yet. Besides, some phase-shift control strategies with optimal phase-shift angle contain lots of electrical parameters, nonlinear equa­tions, or trigonometric calculation, leading to a high computational burden, a complicated process, and a poor real-time characteristic in practical application. In this paper, to address the above problems and achieve the comprehensive optimization for DAB-IBDC, a multi-objective optimization strategy with DPS control is pro­posed. The proposed strategy can reduce current stress, improve transmission power, and minimize power loss simultaneously. Consequently, the proposed strategy can achieve high efficiency and improve adaptability and practicality for DAB-IBDC, which promotes the ap­plication of DAB-IBDC and also accelerates the devel­opment of DC PCS. This paper is organized as follows. The topology, switching behavior based on DPS control, and the per­formance characteristics including the high-frequency-link (HFL) current stress, power factor, and power loss of the DAB-IBDC are investigated in Section 2. On this basis, a multi-objective optimization based on DPS control is proposed in Section 3. Then, Section 4 pro­vides the experimental results obtained from a built DAB-IBDC prototype to verify the proposed strategy. 2 Performance characteristics of DAB-IBDC under DPS control The topology of the DAB-IBDC is presented in Fig. 1. The DAB-IBDC is consisted of active full-bridges H1 and H2 , two DC capacitors C1 and C2 , an auxiliary inductor LT and an high-frequency-link (HFL) transformer with a conversion ratio n. S1 ~ S4 and D1 ~ D4 are switches and diodes in H1, respectively, and Q1 ~ Q4 and M1 ~ M4 are switches and diodes in H2 , respectively. V1 and V2 are DC voltages on two sides of DAB-IBDC, respectively. The energy transfer could be equivalent to the trans­mission of energy between two modulated voltage sources through equivalent inductor L. iL is HFL current flowing through the equivalent inductor. vP is the HFL voltage on the primary side. vS is the HFL voltage on the secondary side, which is generated by secondary terminate and equivalent to the primary-side voltage. Figure 1: Topology configuration of DAB-IBDC. Figure 2: The operation principle, HFL voltages, and currents under DPS control. Generally, the DPS control has two working modes: the inner phase-shift ratio is larger or smaller than the out­er phase-shift ratio, which is determined by the trans­ferred power [7]. Different from EPS and TPS, the inner phase-shift ratios under DPS strategy in active full-bridges on both sides are the same. Ts is the switching period. To avoid the analysis complexity brought from the traditional time-domain segmentation function, the unified model form based on the Fourier series is applied in the analysis and control design. According to the topology of DAB-IBDC, the operation principle, HFL voltages, and currents under DPS control are pre­sented in Fig. 2, where ß is the outer phase-shift angle between vp and vs, and a1 = a2 = a is the inner phase-shift angle. According to Fourier series, the primary and secondary side HFL voltages vp and vs, shown in Fig. 2, are: (1) Since the average inductor current is equal to zero dur­ing steady-state, the HFL current iL in every switching period can be express as: (2) From (1) - (2), the following equations can be obtained: (3) Thus, the root-mean-square (RMS) value of iL is: (4) 2.1 Transmission power characterization The average transmission power P can be obtained as: (5) Substituting (1) - (3) into (5), the average transmission power P can be further calculated as: (6) Besides, the reactive power Q can be obtained: (7) From (6) - (7), the apparent power S is calculated as: (8) Finally, the HFL power factor . can be obtained as: (9) Based on (6) - (9), Fig. 3 shows the HFL power factors under conventional control strategy. In Fig. 3, the HFL power factor . is influenced by phase-shift angles, and the HFL power factors under DPS are higher. Besides, under DPS (DPS1 50 dB 2 UGBW >350 MHz 3 SR >400 V/µs 4 PM 55o