ISSN 0352-9045 Journal of Microelectronics, Electronic Components and Materials Vol. 50, No. 4(2020), December 2020 Revija za mikroelektroniko, elektronske sestavne dele in materiale letnik 50, številka 4(2020), December 2020 UDK 621.3:(53+54+621+66)(05)(497.1)=00 ISSN 0352-9045 Informacije MIDEM 4-2020 Journal of Microelectronics, Electronic Components and Materials VOLUME 50, NO. 4(176), LJUBLJANA, DECEMBER 2020 | LETNIK 50, NO. 4(176), LJUBLJANA, DECEMBER 2020 Published quarterly (March, June, September, December) by Society for Microelectronics, Electronic Components and Materials - MIDEM. Copyright © 2020. All rights reserved. | Revija izhaja trimesečno (marec, junij, september, december). Izdaja Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale – Društvo MIDEM. Copyright © 2020. Vse pravice pridržane. Editor in Chief | Glavni in odgovorni urednik Marko Topič, University of Ljubljana (UL), Faculty of Electrical Engineering, Slovenia Editor of Electronic Edition | Urednik elektronske izdaje Kristijan Brecl, UL, Faculty of Electrical Engineering, Slovenia Associate Editors | Odgovorni področni uredniki Vanja Ambrožič, UL, Faculty of Electrical Engineering, Slovenia Arpad Bürmen, UL, Faculty of Electrical Engineering, Slovenia Danjela Kuščer Hrovatin, Jožef Stefan Institute, Slovenia Matija Pirc, UL, Faculty of Electrical Engineering, Slovenia Franc Smole, UL, Faculty of Electrical Engineering, Slovenia Matjaž Vidmar, UL, Faculty of Electrical Engineering, Slovenia Editorial Board | Uredniški odbor Mohamed Akil, ESIEE PARIS, France Giuseppe Buja, University of Padova, Italy Gian-Franco Dalla Betta, University of Trento, Italy Martyn Fice, University College London, United Kingdom Ciprian Iliescu, Institute of Bioengineering and Nanotechnology, A*STAR, Singapore Marc Lethiecq, University of Tours, France Teresa Orlowska-Kowalska, Wroclaw University of Technology, Poland Luca Palmieri, University of Padova, Italy Goran Stojanović, University of Novi Sad, Serbia International Advisory Board | Časopisni svet Janez Trontelj, UL, Faculty of Electrical Engineering, Slovenia - Chairman Cor Claeys, IMEC, Leuven, Belgium Denis Đonlagić, University of Maribor, Faculty of Elec. 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Prispevke iz revije zajema ISI® v naslednje svoje produkte: Sci Search®, Research Alert® in Materials Science Citation Index™. Design | Oblikovanje: Snežana Madić Lešnik; Printed by | tisk: Biro M, Ljubljana; Circulation | Naklada: 1000 issues | izvodov; Slovenia Taxe Percue | Poštnina plačana pri pošti 1102 Ljubljana Electronic Components and Materials vol. 50, No. 4(2020) Content | Vsebina Original scientific papers Izvirni znanstveni članki I. Mamatov, Y. Özçelep, F. Kaçar: Voltage Diff erencing Transconductance Amplifi er based Ultra-Low Power, Universal Filters and Oscillators using 32 nm Carbon Nanotube Field Effect Transistor Technology 233 I. Mamatov, Y. Özçelep, F. Kaçar: Univerzalni filtri in oscilatorji na osnovi napetostnega transkonduktančnega ojačevalnika v tehnologiji 32 nm poljskega tranzistorja z ogljikovimi nanocevkami E. Erdem, A. M. Garipcan: Hardware Implementation of Chaotic Zigzag Map Based Bitwise Dynamical Pseudo Random Number Generator on Field-Programmable Gate Array 243 E. Erdem, A. M. Garipcan: Strojna implementacija bitnega dinamičnega psevdo-random generatorja števil v FPGA na osnovi kaotične zigzag karte L. F. Rahman, L. Alam, M. Marufuzzaman: Design of a Low Power and High-Efficiency Charge Pump Circuit for RFID Transponder EEPROM 255 L. F. Rahman, L. Alam, M. Marufuzzaman: Zasnova vezja črpalke naboja z majhno močjo in visoko učinkovitostjo za RFID transponder EEPROM A. Bijari, H. Khosravi, M. Ebrahimipour: A Concurrent Dual-Band Inverter-Based Low Noise Amplifier (LNA) for WLAN Applications 263 A. Bijari, H. Khosravi, M. Ebrahimipour: Sočasni dvopasovni ojačevalnik z nizkim šumom (LNA) za aplikacije WLAN A. Chaabane, O. Mahri, D. Aissaoui, N. Guebgoub: Multiband Stepped Antenna for Wireless Communication Applications 275 A. Chaabane, O. Mahri, D. Aissaoui, N. Guebgoub: Večpasovna stopničasta antena za brezžične komunikacijske aplikacije K. Palanichamy, P. Poornachari, G. Madhan M: Performance Analysis of Dispersion Compensation Schemes with Delay Line Filter 285 K. Palanichamy, P. Poornachari, G. Madhan M: Analiza učinkovitosti disperzijskih kompenzacijskih načrtov z linijskim kasnilnim sitom Slovene Science Awards 2020 293 Najvišje nagrade v slovenski znanosti v letu 2020 Front page: 3-D view of typical TG CNTFET (I. Mamatov et al.) Naslovnica: 3-D pogled na tipičen TG CNTFET (I. Mamatov et al.) Original scientific paper https://doi.org/10.33180/InfMIDEM2020.401 Electronic Components and Materials Vol. 50, No. 4(2020), 233 – 241 Voltage Differencing Transconductance Amplifier based Ultra-Low Power, Universal Filters and Oscillators using 32 nm Carbon Nanotube Field Effect Transistor Technology Islombek Mamatov, Yasin Özçelep, Firat Kaçar Istanbul University- Cerrahpasa, Department of Electrical and Electronics Engineering, Istanbul, Turkey Abstract: Carbon nanotube field-effect transistor (CNTFET) is a strong candidate to replace existing silicon-based transistors. The ballistic transport of electrons in the CNTFET channel leads to ultra-low-power and high-frequency devices. Although a lot of digital applications of CNTTFET were presented, less work was done in analog applications of CNTFETs. This paper presents analog applications of CNTFET and its implementation of voltage differencing transconductance amplifier (VDTA). The CNTFET VDTA based filters and oscillators were proposed. The VDTA circuits are resistorless and can be tuned electronically only by changing transconductance. The proposed CNTFET VDTA shows power consumption of 4000 times less than compared to silicon CMOS technology and a significant reduction in chip area. All simulations were performed using SPICE and MATLAB simulation tools. Keywords: Carbon Nanotube (CNT); Carbon Nanotube Field Eff ect Transistors(CNTFET); Voltage diff erencing Transconductance Amplifiers (VDTA); MOSFETS Univerzalni filtri in oscilatorji na osnovi napetostnega transkonduktančnega ojačevalnika v tehnologiji 32 nm poljskega tranzistorja z ogljikovimi nanocevkami Izvleček: Poljski transistor z ogljikovimi nanocevkami (CNTFET) je močen kandidat za zamenjavo obstoječih silicijevih tranzistorjev. Balističen prenos elektronov v CNTFET kanalu omogoča nizko porabo moči in visoke frekvence. Kljub številnim digitalnim aplikacijam CNTFETov, je na analognem področju zelo malo objav. Članek opisuje uporabo CNTFET v analognem vezju napetostno diferencialnega transkonduktančnega ojačevalnika (VDTA). Vezja so brez uporov in elektronsko nastavljiva s spreminjanjem transkonduktance. Predlagano vezje ima 4000 krat nižjo porabo moči kot ekvivalentna izvedba v silicijevi CMOS tehnologiji. Simulacije so izvedenev SPICE in MATLAB okolju. Ključne besede: Ogljikove nanocevke (CNT); poljski transistor z ogljikovimi nanocevkami (CNTFET); napetostno diferencalni transkonduktančni ojačevalnik (VDTA); MOSFET * Corresponding Author’s e-mail: islombek90@gmail.com path (MFP), looks to overcome the limitations of con­ 1 Introduction ventional silicon-based MOSFETs due to its unique electronic and mechanical properties. These proper-Silicon-based MOSFETs have already reached their ties come from their strong atom-to-atom bonds, bal-limits in scaling. CNTFET, with its ultra-long mean free listic or near ballistic transport, and quasi 1D features I. Mamatov et al.; Informacije Midem, Vol. 50, No. 4(2020), 233 – 241 of the CNT channel. Besides, by changing the chirality of the CNT its material properties can be changed from semiconducting to metallic. Many attempts at building CNTFET models have been reported in the literature [1-9]. Two major geometries are available for CNTFET de­sign, which are planar and gate-all-around. Sanchez et al. have compared all available architectures and their performances [1]. Dokania et al. have proposed gate-all-around (GAA) or also known as wrap gate, analytical SPICE model [2]. The gate capacitance and drain current in the channel should be accurately designed to predict the precise performance of CNTFETs. Ahmed et al. pro­posed a model of the gate capacitance in which CNTs are arranged arbitrarily, unlike other models in which CNTs are placed at a fixed distance [3]. The authors of [3] have reported a 3% error with numerical simulations. Ballistic or near ballistic transport models for the drain current are proposed in [4-9]. These models are SPICE compat­ible, which means that the model can be easily compiled and integrated with any other circuit. The model used in this paper is from the articles [8-9]. Nizamuddin et. al proposed CNTFET and CMOS-based three-stage, hybrid operational transconductance am­plifiers (OTA) [7]. Marani et al. reported improvement in DC gain by 17%, 40% less power consumption, and a decrease in output resistance by 90% in comparison to CMOS OTA [7]. Low power mixed-mode active fi lter using 12 CNT and 2 capacitors was presented by Zan-jani et al. [14]. Jooq et al. designed CNTFET based ring oscillators suitable for the internet of things (IoT) appli­cations [17]. Low power CNTFET based RF oscillator is reported in [18]. Digital applications of CNTFET, such as adders and multipliers can be found in papers [19-21]. Most of the CNTFET studies are limited to simulations only since commercially CNTFETs are not available. Mindy et al. have proposed a method for the produc­tion of CNTFETS in commercial silicon manufacturing facilities and reported experimental measurements of CNTFETs fabricated in two diff erent manufacturing facilities [22]. Besides, the authors have improved the speed of the fabrication process 1100 times, by de­creasing the deposition of CNT on the wafer from 48 hours to 150 seconds. Rebecca et al. have reported the first experimental data for CNTFET CMOS analog cir­cuitry [23]. They have successfully fabricated 2 stages CTNFET CMOS op-amp with the channel length of 3 µm, which achieves the gain > 700. Thus, the basics of CNTFET technology is CMOS too. Even so, when we write CMOS, we refer to silicon-based CMOS in this pa­per. The fi rst Voltage diff erencing transconductance amplifier (VDTA) was introduced by D. Biolek as an active element for analog signal processing[10]. However, any author did not perform the circuit implementation and application until the authors of proposed the realization of CMOS fi lters using VDTA [11]. The miniaturizations of electronic gadgets are becoming mainstream in today’s technology. It will get harder and harder to integrate passive inductors into nano level circuits. VDTAs can be used to simulate inductors in signal processing circuits. This work is organized as follows: Section 2 and 3 present the fundamentals of CNTFETSs and VDTAs respectively. The simulations’ results and discussion of CNTFET VDTA including its comparison with CMOS VDTA are presented in section 4. In section 5,the application example of VDTA is presented. The universal fi lter realization is presented in section 5.1. The simulation results of CNTFET VDTA based oscillators are presented in section 5.2. Finally, in section 6 the conclusion of this paper is presented. 2 Carbon nanotube field-effect transistors fundamentals Carbon nanotubes can be classified as single-walled and multi-walled. CNTFETs presented in this paper are made from single-walled CNTS as shown in Fig. 1. The chirality of CNT is the key parameter that determines whether a material is metal or semiconducting. There are two parameters of chirality, n and m (in some books or papers also referred to as n1 and n2). The values of these chirality parameters vary according to the rolling up method of CNT. The CNT is metallic if the diff erence of n and m is a multiple of 3. Otherwise, if the difference of n and m is not a multiple of 3 then the CNT is semiconducting [12-13]. The CNTFET presented in this paper is designed with semiconducting CNT. Figure 1: Rolled up Graphene sheet (Carbon Nanotube). The bandgap is another key parameter which can be calculated from [12]: I. Mamatov et al.; Informacije Midem, Vol. 50, No. 4(2020), 233 – 241 2 at 0.8 eV . (1) EG = cc 2 dd Where, tight binging energy t is 3.0eV (also referred to as C-C bonding energy) and C-C bonding distance acc of the nearest neighbor is 1.42Ao. Whereas, equations for CNT diameter CNTFET threshold are given as [13]­[14]: n 2 + m 2 + mn (2) DCNT = a . aV . VT . (3) 3e D Figure 3: CNT Diameter vs bandgap. CNT Here, a (C-C unit vector length) is 0.246 nm. From (a) equations, it is obvious that both bandgap and threshold voltages are dependent on the diameter of CNT. The width of CNTFET can be calculated from the parameters like the number of tubes, the distance between tubes, and the diameter of CNT. W =( N - 1) S +D (4) CNT Numerical simulations of equations (1) and (3) were performed via MATLAB tool and the results are shown in (b) Fig. 2 and Fig. 3. The exponential proportional dependency of CNT diameter for both bandgap and threshold voltage was observed. Both, threshold and band gap values increase as the CNT diameter value decreases. The CNTFET model used in this research is shown in Fig. 4 [8-9;14]. The CNTs are placed under the gate separated by high-k (high dielectric constant) material. The CNT extension regions between S/D and gate are heavily doped. Default parameter values provided by authors of the model [8-9;24] are shown in Table 1. (c) Figure 4: MSOFET-like CNTFET, a)1-D side view Figure 2: CNT Diameter vs V threshold. b) top view, c) 3-D view of typical TG CNTFET [8-9]. I. Mamatov et al.; Informacije Midem, Vol. 50, No. 4(2020), 233 – 241 3 VDTA The proposed VDTA’s circuit symbol and its circuit architecture at CNTFET level are shown in Fig. 5 and Fig. 6 respectively. The VDTA is an active element with high impedance input terminals VP, VN, and high impedance output terminals Z, X+, and X-. The relationship between I/O terminals of an ideal VDTA can be expressed as follow [11]: . I .. g - g 0.. V . Zm 1 m 1 VP ... .. . I = 00 gV (5) x + m 2 VN ... .. . . I .. 00 - g .. V . . x -. . m 2 .. VZ . Figure 5: The Circuit Symbol of VDTA. Figure 6: CNTFET implementation of VDTA. Where gm1 is the transconductance of the fi rst stage and gm2 is the transconductance of the second stage. The voltage difference at the input terminals P and N transforms into output currents at terminal Z by gm1. Then the voltage at the terminal Z is converted to output currents by gm2 at the output terminals x+ and x- [15]. VDTA can be tuned electronically by adjusting the values of gm of the first stage or second stage. 4 Simulations, results, and Discussions All simulations were performed using HSPICE software. The parameters of CNT transistors used to get DC and AC characteristics of CNTFET VDTA are shown in Table 2. Supply voltages are fi xed to VDD = –VSS = 0.3V and biasing currents are –considered as I = I = I = B1B2B3 1µA. DC varying between –0.3V and 0.3V was applied first to the P and N terminals to measure the output current and to the Z terminal. Then DC changing between –0.3V and 0.3V was applied Z terminal of VDTA to measure output currents at terminals +X and -X. The results of DC transfer characteristics for ideal current sources are shown in Fig. 7 and Fig. 8 in two steps. As expected, the output current increases as the CNT diameter increases. Because the I of CNTFET on increases as diameter increases due to an increase in carrier mobility and velocity [25]. For instance, in Fig. 7, the output current of CNTFET VDTA for 0.1V with CNT (7,0) is around 0,85µA, CNT (13,0) is around 0,89µA, CNT (19,0) and CNT (34,0) is 0,90 µA. Table 1: Design parameters and defi nitions [24]. Parameter Defi nition Value Lch Length of channel 32nm Lss, Ldd The length of the doped CNT source/drain extension region. 32nm Pitch The distance between the centers of two adjacent CNTs within the same device 20nm Dcnt The diameter of Carbon Nanotubes 1.5nm Tox The thickness of the high-k top gate dielectric material 4nm Parameter Defi nition Value Kox The dielectric constant of a high-k gate oxide material. 16 Tubes The number of tubes in the device. 3 (n1, n2) The chirality of tube (19, 0) Table 2: Transistor dimension of Proposed CNFET VDTA FCS. Transistors W(nm) L(nm) Chirality DCNT(nm) Tubes M1,M2,M5,M6 41.5 32 19,0 1.5 3 M3,M4,M7,M8 221.5 32 19,0 1.5 12 The AC response of CNTFET VDTA for diff erent CNT parameters is shown in Fig. 9 and Fig. 10. The same supply voltage and bias currents as in the previous section were used. Similar to DC simulations, two-step simulation and measurement was done to get the AC response of VDTA. In the first step, the input AC voltage of 1V was applied at one of the input terminals P or N, and the gain at the output terminal Z was measured. In the second step, both input terminals were grounded and the input AC voltage of 1V was applied to the Z I. Mamatov et al.; Informacije Midem, Vol. 50, No. 4(2020), 233 – 241 P and VN vs I z. = V vs I and I . zx+x- terminal. The output gain was measured from the X+ terminal. Both steps of DC/AC simulations show the same results which prove that CNTFET VDTA is operating properly. Table 3: Comparison of CNFET and CMOS technologies. VDTA Structure Supply voltage Biasing current Power consumption Transistor dimension N-type (channel WxL) Transistor dimension P type (channel WxL) CMOS 18µm ±0.3 1mA 12mW 1.296 µm2 5.99904 µm2 CMOS 32nm ±0.3 400 µA 4.8mW 0,00132 µm2 0,00708 µm2 CNTFET 32nm ±0.3 1µA 1.2 µW 0,00132 µm2 0,00708 µm2 Comparison of CMOS 0.18um, CMOS 32nm node technology VDTA, and CNFET 32 nm technology VDTA is shown in Table 3. All three architecture is designed to meet the same frequency response (fc . 3.5 GHz). For the case of CMOS 32 nm VDTA, the DC characteristics degrade a little bit, the maximum output current does not reach the supplied ideal current source. Where CMOS 0.18 µm maximum current reaches and CNTFET VDTA maximum current reaches. Besides, even if the same dimensions (channel WxL) as for CNTFET VDTA are used for CMOS 32nm VDTA, the biasing current of 400µA is needed for CMOS 32nm technology to meet the same frequency response of CNTFET. As we can see from graphs in DC simulations (Fig. 7-8) there is no much difference between CNT (7,0), (13,0), (19,0), and (34,0). However, the Vth of (7,0) is much higher compared to (34,0).In AC simulations of VDTA (Fig. 9-10), we can observe a significant increase in gain with the change of CNT chirality from (7,0) to (19,0). Between (19,0) and (34,0) there is no much diff erence in gain but the diameter changes from 1.5 nm to 2.6 nm which will drastically increase the transistor dimension as well. Hence, we have selected CNT (19,0) for our further simulations. Another reason for selecting CNT (19,0) is to compare our simulation results with other references. Because all other works also used (19,0) CNT, including the authors of the original model from [24]. Figure 9: AC Characteristics of CNTFET VDTA. Step1 Vin = V vs I /V PzP. 5 Application example VDTA has a wide range of applications in the analog signal processing field. One of them is a spectrum analyzer shown in Fig. 11. This spectrum analyzer uses low pass filters, bandpass filters, local oscillators, and mixers to get the final intermediate frequency (IF). I. Mamatov et al.; Informacije Midem, Vol. 50, No. 4(2020), 233 – 241 inzx+z As an application example, this paper presents four filters and three local oscillators used in the spectrum analyzer. 5.1 Filters VDTA can be categorized as voltage mode and current mode. This paper presents voltage mode CNTFET VDTA. The realization of CNTFET voltage mode VDTA derived from ref [11] is shown in Fig. 6. Further, the universal filter topology of CNTFET VDTA is proposed as shown in Fig. 12. The presented CNTFET VDTA filter can operate as LP and BP fi lter. The transfer function of the filter is as follow: If 1= then VVIN V sCg O 11m 1 BP ›= (6) 2 V sCC + sC g +gg IN 1 2 1 m 2 m 1 m 2 V O 2 gm 1 gm 2 LP ›= (7) 2 V sCC + sC g + gg m 1 2 IN 1 2 1 2 mm And the expressions for Quality factor and natural frequency are given below: Figure 12: Application of proposed CNTFET VDTA fi lter. gg m 1 m 2 w = (8) CC 12 Cg 2 m 1 Q = (9) Cg 1 m 2 The filter blocks from Fig. 11 have been realized using proposed CNTFET VDTA from Fig.12 and the results are plotted in Fig. 13. The parameters of CNT transistors used for filter applications are shown in Table 2. The values of capacitors used for the filter application of CNTFET VDTA are shown in Table 4. The same supply voltage and bias currents as in the previous section were used. CNT (19,0) was selected for further applications of VDTA. There is no much difference between (7,0) and (19,0) CNT when the biasing current is set to 1µA. As biasing current increases, the center frequency of fi lters also increases due to an increase in transconductance. I. Mamatov et al.; Informacije Midem, Vol. 50, No. 4(2020), 233 – 241 Table 4: Capacitor values selected CNFET VDTA fi lters. Table 5: Transistor dimension of proposed CNFET VDTA oscillator. Filters C1 C2 Chirality n,m 3.6 GHz LP 80.5fF 80.5fF 19,0 5.122 GHz BP 0.4334fF 0.4334fF 19,0 322.5 MHz BP 22.5 MHz BP 74.5pF 10.72pF 74.5pF 10.72pF 19,0 19,0 Transistors W(nm) L(nm) Chirality D(nm) CNT Tubes M1,M2,M5,M6 221.5 32 19,0 1.5 12 M3,M4,M7,M8 1121.5 32 19,0 1.5 57 5.2 Oscillator The oscillator is a DC to AC converter, which converts DC input signals to AC output signals such as sinusoidal waves. Local oscillators are used to change the frequency of the signal as in a spectrum analyzer from Fig. 11 and along with mixers, they improve the performance of receivers in electronic circuits. The circuit symbol of the CNTFET VDTA oscillator is shown in Fig. 14. The oscillator blocks from Fig. 11 have been realized using the proposed oscillator structure. The circuit analysis of the second-order characteristical equation can be represented as: 2 Cg + gg =0 (10) sCC + s( - g ) 12 2 m 3 m 4 m 12 m g = g (11) m 3 m 4 gg m 1 m 2 = (12) . 0 CC 12 Where gm3 = gm4 is the condition for oscillation and .o is oscillation frequency. The parameters of CNT transistors used for oscillators applications are shown in Table 5. Supply voltages are fi xed to VDD = –VSS = 0.3V and biasing currents are considered as I = I = I = B1B2B3 1µA. The simulation results are plotted through Fig. 15­Fig. 17. Figure 15: 5.1 GHz VDTA Based Oscillator C1=C2 =0.068fF. 6 Conclusion Ultra-low-power CNTFET based VDTA fi lters and oscillators were presented. As shown in Table 3. CNTFET 32 nm based VDTAs consume the power of 4000 times less than CMOS 32nm based VDTAs. Also, n-type CNTFETS occupy approximately 989 times less than space in the chip area (only considering eff ective channel WxL) compared to n-type MOSFET transistors while p-type CNTFETS occupy approximately 848 times less space(only considering eff ective channel WxL) I. Mamatov et al.; Informacije Midem, Vol. 50, No. 4(2020), 233 – 241 compared to p-type 0.18µm technology node MOSFETS used in typical VDTAs. Higher biasing current or capacitors may be adjusted to change the center frequency of CNTFET filters. CNTFET VDTA based filters and fi rst-ever CNTFET VDTA based oscillators for spectrum analyzer are presented as an application example. 7 Conflict of interest The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper. 8 References 1. A. Pacheco-Sanchez, F. Fuchs, S. Mothes, A. Zienert, J. Schuster, S. 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This is an open access article dis­tributed under the Creative Com­mons Attribution (CC BY) License (https://creativecom-mons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Arrived: 16. 07. 2020 Accepted: 13. 11. 2020 Original scientific paper https://doi.org/10.33180/InfMIDEM2020.402 Electronic Components and Materials Vol. 50, No. 4(2020), 243 – 253 Hardware Implementation of Chaotic Zigzag Map Based Bitwise Dynamical Pseudo Random Number Generator on Field-Programmable Gate Array Ebubekir Erdem, Ali Murat Garipcan Firat University , Computer Engineering Department, Elazig, Turkey Abstract: In this study, successful real-time hardware implementation of discrete-time chaotic zigzag map as a random number generator (RNG) on field-programmable gate array (FPGA) environment is presented. For the hardware modelling of the application, ready-to-use modules defined on 32-bit floating-point numbers and hardware description language (VHDL) are used. In the study, the non-linear dynamic behaviour of the chaotic generator synthesized on the Altera Cyclone IV GX FPGA chip is examined in terms of critical cryptographic competences such as system reliability and statistical randomness quality. The random numbers with poor statistical quality in the system are obtained by passing 32-bit chaotic trajectory outputs through a simple comparison circuit. In order to improve the statistical sufficiency of these numbers, the H function post-processing technique is used. In addition, statistical verification and hardware performance analysis of the generator through NIST 800-22 tests and FPGA chip statistics are presented in the study. The obtained successful results show that the zigzag map can be used in different chaos-based engineering applications, including embedded cryptographic applications. In addition, the low area-energy requirement of PRNG in terms of modelling technique facilitates its practical applicability on resource-restricted applications and architectures. Keywords: FPGA; pseudo-random number generator; chaotic zigzag map; H function Strojna implementacija bitnega dinamičnega psevdo-random generatorja števil v FPGA na osnovi kaotične zigzag karte Izvleček: Članek predstavlja strojno implementacijo časovno disktretne kaotične zigzag karte kot generator naključnih števil v FPGA okolju. Za strojno modeliranje aplikacije je uporabljen VHDL skriptni jezik. V smislu kvalitete naključnosti in zanesljivost je raziskano nelinearno dinamično obnašanje kaotičnega generatorja na Altera Cyclone IV GX FPGA čipu. Naključna števila s slabo statistično kvaliteto so dobljena s posredovanjem 32-bitne kaotične trajektorije v enostavno primerjalno vezje. Za izboljšpanje njihove kvalitete je uporabljena tehnika post procesiranja s H funkcijo. Dodatno je statistična verifikacija preverjena z NIST 800-22 testi in statistiko FPGA čipa. Rezultati nakazujejo možnost uporabe zigzag kart v različnih kaotičnih aplikacijah vključno s kriptografijo. Ključne besede: FPGA; pseudo naključen generator števil; kaotična zigzag karta; H funkcija * Corresponding Author’s e-mail: aberdem@firat.edu.tr 1 Introduction like other fields, corresponds to randomly distributed In addition to cryptography, randomness is a common bit-level random numbers acquired from a specific en-statistical concept for many areas such as game theory, tropy source in cryptography are not reproducible and simulation, statistic, quantum mechanics, program-predictable. In cryptography, random numbers can be ming and entertainment. This common concept, un-obtained from two different design classes, namely E. Erdem et al.; Informacije Midem, Vol. 50, No. 4(2020), 243 – 253 True Random Number Generators (TRNG) using physi­cal noise sources and Pseudo Random Number Gen­erators (PRNG) with deterministic structure. Although their output is unpredictable, TRNGs are susceptible to environmental changes and mostly offer hardware-dependent, slow and costly solutions [1-3]. Despite fulfilling an important cryptographic require­ment such as unpredictability in terms of system secu­rity, statistical weakness is the most obvious deficiency of a physical TRNG. For PRNGs where random num­bers with good statistical properties can be obtained at low cost, determinism and periodicity are the most important shortcomings of this design class. PRNGs are preferred due to their practical structure to obtain random numbers within cryptographic applications. However, due to the nature of determinism, the initial conditions and system parameters are decisive in the development of future states of PRNGs, unlike random­ness. This case leading to predictability, limits the use of PRNGs for sensitive cryptographic applications. Fur­thermore, knowing the initial conditions (parameters) that contain all the entropy of the deterministic system, can completely remove the cryptographic confidenti­ality required for PRNGs [4-5]. Chaos theory is an important concept that has found application in many different disciplines such as biol­ogy, philosophy, meteorology, physics and sociology as well as different branches of engineering [4]. Chaos can be roughly defined as an irregular and unpredict­able random behavior pattern observed in non-linear deterministic systems that are exponentially sensitive to initial conditions. The deterministic characteristic of chaotic systems is the most prominent feature dis­tinguishing them from noise-based non-deterministic systems preferred for sensitive cryptographic applica­tions. Due to their deterministic properties, the future states of chaotic systems can be predicted theoreti­cally if the initial states are known exactly. However, in these systems characterized by a strong exponential dependence on the initial conditions, a very small error in the initial conditions due to the positive Lyapunov exponential can cause large deviations, also known as the butterfly effect, in the system trajectories evolving in time. Therefore, this divergent character can provide sufficient level of cryptographic secrecy by making the long-term estimation of dynamic system outputs in chaos state impossible [6-7]. Chaotic systems are divided into discrete and con­tinuous time chaotic systems according to their math­ematical modeling. In continuous chaotic systems, the evolution of the system is given by ordinary dif­ferential equations. It depends on the rate of change of the system's state variables. In discrete time, where the evolution of the system depends on the values of state variables, chaotic systems are expressed by sim­ple non-linear equations [3, 8]. For both chaotic system models, exponential sensitivity to the initial conditions and the ability to produce long-term non-periodic os­cillations are the basic characteristics of these systems coinciding with the pattern of random behavior. These basic characteristics of chaos, which are similar to the confusion and diffusion properties, also known as Shannon principles, are used for different purposes in cryptography such as video [9], audio [10], image [11] encryption schemes, stream cipher [12], s-box design [13], post-processing techniques [14] and secure ad­ditional input [2]. Random number generation is an­other important use of chaos theory in cryptography. Chaotic systems can often be used as entropy source in hardware-based PRNG and TRNG designs, especially because they eliminate the need for difficult and com­plex processes, such as obtaining and processing noise signals based on physical randomness. In practice, the prediction of the future state informa­tion of the chaotic system is limited by the measure­ment sensitivity of the initial state information. Where­as, the lack of infinite measurement sensitivity from the circuit nodes depending on the presence of electrical noise makes it almost impossible to accurately deter­mine the initial conditions of the chaotic system for hardware implementations. Therefore, hardware mod­eled chaotic systems alone can provide the reliability (security) and unpredictability needed cryptographi­cally, unlike a simple deterministic PRNG [8]. In the literature, there are different chaos-based PRNG and TRNG paradigms implemented with FPGA chips offering important facilities such as flexibility, ease of modelling, low power consumption, parallel process­ing and speed. Some of these studies can be summa­rized as follows: Özkaynak [7] proposed an easily ap­plicable RNG model on FPGA chips, which could be an alternative to discrete time chaotic systems using the fractional order Chua system. Tuna et al. [15] modelled the autonomous Lü-Chen chaotic system on Xilinx Vir­tex-6 FPGA chip using the Heun numerical method and presented a high-speed chaotic oscillator design that can be used for embedded cryptographic applications. In another study, Tuna [16] presented a real-time im­plementation of a PRNG using an artificial neural net­work (ANN) based 2D chaotic oscillator on Xilinx Virtex 6 FPGA chip in four different scenarios. Koyuncu and Özcerit [17] modeled the continuous-time Sundara­pandian – Pehlivan chaotic system using the Range-Kutta (RK4) numerical analysis method as RNG on the same FPGA chip. De la Fraga et al. [18] presented the hardware modeling of a PRNG based on four different discrete time chaotic system scenarios in their study E. Erdem et al.; Informacije Midem, Vol. 50, No. 4(2020), 243 – 253 used Xilinx FPGA Spartan 3E FPGA chip. Koyuncu et al. [19] proposed the use of a new chaos-RO based dual entropy core TRNG architecture using the Xilinx Virtex-6 FPGA chip. A new three-dimensional continuous-time autonomous chaotic oscillator (P3DS) has been used as the deterministic component of TRNG. In another study, Meranza-Castillón et al. [20] provided the hard­ware implementation of a chaotic enhanced Hénon map (EHM) based PRNG that can be used for image and video ecryption systems on the Altera DE2-115 FPGA chip. Garcia Bosque et al. [21] presented a logistic map based PRNG implementation on Xilinx Virtex 7 chip in which chaotic system parameters change dynamically to prevent the system to fall into short period orbits as well as increasing the statistical randomness quality. Kanzadi et al. [22] proposed a double entropy sourced PRNG architecture on the Xilinx Spartan 3 FPGA chip, combining the tent and logistic map outputs with the exclusive-OR (XOR) gate. In [23], another logistic map based study Tuncer proposed physical unclonable functions based on ring oscillator (RO-PUF) and logistic map to generate pseudorandom numbers. The gen­erator was implemented in Altera Cyclone II FPGA chip with VHDL language. Çiçek et al. [24] proposed a TRNG architecture using a discrete time double entropy re­source to overcome the intrinsic limited entropy prob­lem of conventional single entropy core architectures by using hardware redundancy. In this study, hardware implementation and perfor­mance evaluation of an FPGA-based PRNG using cha­otic zigzag map as entropy source is given. The statis­tical and spectral properties of the chaotic time series obtained from the implemented system are analyzed cryptographically. The NIST 800-22 randomness test is used for statistical verification of random numbers ob­tained from chaotic time series. The presented study is important in terms of demonstrating the applicabil­ity of the modeled chaotic system for different chaos-based cryptographic purposes such as secure com­munication, video and image encryption and s-box design in addition to random number generation. Fur­thermore, chaotic PRNG can be easily used in resource-restricted architectures and cryptographic applications due to its low area-energy consumption. The rest of the paper is organized as follows: In Chap­ter 2, theoretical details of the chaotic system are giv­en. Details of the digital implementation of proposed PRNG on FPGA environment are presented in Chapter 3. In Chapters 4 the hardware performance and statis­tical success of chaos-based RNG have been analyzed cryptographically, respectively. The study is concluded by interpreting the results obtained in Chapter 5. 2 Chaotic zigzag map The discrete-time one-dimensional chaotic zigzag map whose mathematical definition is given in Eq. 1, is proposed by Nejati and Beirami in [5]. In Eq. 1, m is the state variable of the chaotic system and changes in the (- 3,3) closed interval. The zigzag map can display stable or chaotic behavior for different m values in the defined interval. The bifurcation diagram given in Fig. 1 can be used to identify the chaotic behavior of the system for these changes. In Fig. 1, for |m| < 1 values its behavior is stable, while for intervals m . (2,1), (1,2), [3,2) and (2,3] its behavior is chaotic. Especially for m . [3,2) and (2,3] intervals, the xn output values of the system in chaos state occur with a large irregularity in the [-1,1] interval. For the same intervals, the xn output values of the chaotic system tend to infinity for large n values representing the iteration step. For |m| = 2, the map converges to 0 [5, 18]. (1) In Eq. 1, the xn output values oscillating in the [-1,1] in­terval for the zigzag map are 32-bit floating-point (real number) format. Eq. 2 is used to obtain one-bit random numbers from these 32-bit numbers in each iteration. In Eq. 2, the xn output values normalized to the [0,1] in­terval, are compared with the threshold value and ran­dom bit sequences are attained. 1, | xn | 0.5 .> b =. (2) n + 1 0, | x | 0.5 < .n 3 Implementation details of FPGA-based real-time chaotic zigzag map The chaotic system in accordance with the 32-bit IEEE 754 floating-point number standard is designed to be operated on FPGA chips. The Quartus Prime Lite Edi­tion 17.1 design software and the Altera Cyclone IV EP­C4GX150 FPGA chip are used together for synthesis and placement during the hardware implementation phase. In the chaotic system, Intel FPGA Intellectual Property (IP) cores library with ready-to-use circuit elements de­ E. Erdem et al.; Informacije Midem, Vol. 50, No. 4(2020), 243 – 253 fined on floating-point numbers is used for multiplica­tion, division, addition, subtraction and comparison operations. In addition to this, all other definitions and circuit elements needed in the system are designed by VHDL dataflow and behavioral coding technique. The top-level block representation of the PRNG created by schematic and dataflow design techniques is shown in Fig. 2. The operating logic of the system given in Fig. 2 can be briefly described as follows: In Fig. 2, 32-bit x0 and xn values represent the seed and output values of the chaotic system, respectively. When the chaotic system starts to work, the seed value x0 is applied as input to the system and after a certain calculation time, the output value x1 is obtained. This case is the initial position for the chaotic system and the output of the system is constant at value x1, in this position. In order to obtain random numbers from the chaotic system, starting from x1 value, the generated all xn values should be applied as input to the system, respectively. This case is called the feedback position for the chaotic system. Figure 3: Hardware modeling of zigzag map in Quartus environment. In figure (A) is the common 2/|m| constant for Equation 1. (B) is the 0 (zero) constant used to ensure synchronization in the modeling phase. (C) and (D) are dataflow designed multi-mode control and post-processing circuit elements, respectively E. Erdem et al.; Informacije Midem, Vol. 50, No. 4(2020), 243 – 253 (a) (b) Figure 4: Real time simulation results of the zigzag map for (a) initial and (b) feedback positions from the initial position. A triggering signal (sel) ob­tained from the physical ambiance is used as the selec­tion pin of the mux at the input of the chaotic system to enable the transition between these positions. In order to obtain bit-level random oscillations (numbers) at the output of the PRNG, the 32-bit chaotic xn random numbers are passed through the digitization and post-processing blocks, respectively. Quartus modeling of PRNG whose schematic structure is given in Fig. 2 as in Fig. 3. Real-time simulation of 32-bit hexadecimal random outputs representing the chaotic trajectory for the modeled zigzag map is as in Fig. 4. For the mathematical operations, two addition (fp_ add), one subtraction (fp_substract), one multiplica­tion (fp_multiplication), and one absolute value (fp_ abs), ready-to-use IP core modules which are able to do calculations with floating-point numbers are used in Fig. 3. In addition to these ready-to-use circuit mod­ules, two dataflow designed block circuit elements (multimod_control_block & post_processing_block) are used in Fig. 3 (C) and (D). In the initial position, the input values of the chaotic system x0 and m are 0.4898 and 2.5, respectively. The parameter is the common factor of the three different equalities in Eq. 1. For this reason, instead of calculating the common (2/|m|) expression for the first and third equalities in Eq. 1 in each iteration, the mathematical equivalent of this expression is defined as constant (constant_1) as in Figure 3 (A). Therefore, the hardware equivalent of the equalities in Eq. 1 is (-m(xn + con­stant)), (m(xn + 0)) and (m(xn - constant)) respectively in Fig. 3. In the system, it is important that the calculation time is the same for all three equalities in terms of syn­chronization. For this purpose, for the second equality consisting of only multiplication, the addition with 0 (zero) constant is made as in Fig. 3 (B). Thus, the calcula­tion times of the parallel connected (xn + constant), (xn + 0) and (xn - constant) expressions were equalized in 7 clock pulses. The calculated results at each 7 clock puls­es are simultaneously applied to c1, c2 and c3 inputs of the multimode control circuit in Fig. 3 (C), respectively. The outputs of the control circuit whose hardware modelling details are given in Fig. 5 are connected to the inputs of the multiplication circuit. The mathemati­cal definition of the zigzag map consists of three differ­ent equations. Which equality will be used in the sys­tem is decided by looking at interval of the xn values. The main task of the multimode control circuit in Fig. 5 is to determine which equality result should be used by checking the xn interval and whether the common factor is positive or negative. For this, the dataflow de­signed circuit element (output_controller) in Figure 5 (A) is used. The task of this component is to determine the interval of xn by checking the c1 input to which the (xn + 0) addition result is connected. The multimode control circuit in Fig. 5 has two 32-bit vectorial outputs, out0 and m_value. The out0 output is switched to one of the input values c1, c2 and c3 in accordance with the xn interval. When out0 output is switched to c1 input, m_ value output takes +m, in other cases (c0, c2) -m values. culation time required to obtain a 32-bit xn random number in any iteration from the chaotic system is 12 clock pulses in total. The 32-bit random numbers whose absolute value is taken after the multiplication are applied as an input to the comparison circuit (fp_ comparator) in Fig.3. The calculation time of the com­parison circuit is 1 clock pulse and performs bit-level transformations according to Eq. 2. However, the sta­ E. Erdem et al.; Informacije Midem, Vol. 50, No. 4(2020), 243 – 253 tistical randomness quality of the random numbers ob­tained for the threshold value, selected as 0.5 in Eq. 2, is cryptographically insufficient. Random numbers ob­tained from the chaotic system are applied to the input of the post processing block in Fig. 3 (D) to remove this shortcoming. The hardware modeling details of this block circuit, in which H function [25] post-processing technique is used, are as in Fig. 6. Figure 6: Hardware modelling of post-processing block The post-processing technique in Fig. 6. consists of two combiner circuits (pp_combiner1 & pp_combiner_2), used to obtain the desired bit-level logic vectorial in­puts and outputs, in (A) and (B) and the H function in (C). The H function post-processing technique based on Quasigroup transformation needs 16-bit vectorial input obtained from chaotic system trajectory to pro­duce 8-bit vectorial random output in each iteration. The task of the first combiner circuit (pp_combiner_1) in Fig. 6 (A) is to combine one-bit random numbers generated in every 13 clock pulses and to obtain 16­bit logic vector inputs needed for the post-processing technique. Then, the random numbers passed through the XOR based H function block in Fig. 6 (C) are finally applied as an input to the other combiner circuit (pp_ combiner_2) in Fig. 6 (B). The 8-bit combined outputs of this circuit are also the hexadecimal outputs of PRNG. The frequency of the clock signal applied to the input of the chaotic system is 200 MHz. The time to gener­ate a 1-bit random sign / number for PRNG is 13 clock pulses depending on the calculation time of the cha­otic system. In other words, for a 200 MHz clock sign with a period of 5 ns, the chaotic system produces a one-bit random number every 65 (13x5) ns. Hence, the output bit rate of PRNG is 200/13 = 15.4 Mbit/s with­out post-processing technique. However, the post-pro­cessing technique reduces the output bit rate of the chaos-based generator by 1/2. For this reason, the final output bit rate of chaotic PRNG drops to 15.4/2 = 7.7 Mbit/s after the post-processing technique is applied. The time to obtain 16 bit-length random number se­quences for the post-processing technique in the system is 208 (13x16) clock pulses. The 8-bit random numbers generated by PRNG every 208 clock pulses, and the 32-bit outputs of the zigzag map are recorded in two different memory architectures for testing pur­poses, as in Fig. 7 (A) and (B). Column widths of these memory architectures consisting of 65.536 rows are 8 and 32 bits, respectively. In both memory architectures, 16-bit counters are used for addressing. The memory architecture in Fig. 7 (A) is used for statistical analysis, while the memory architecture in (B) is used to verify the existence of chaos in the system for time series de­rived from the zigzag map. The frequencies of the clock signal applied to the input of the counter and memory architectures are 960 KHz (200/208) and 16.7 (200/12) MHz, respectively. Figure 7: Memory architectures used for testing in the system 4 Experimental validation Experimental analysis of the study is carried out in three stages. In the first stage, the existence of chaos in the system for zigzag map and exponential sensitivity of PRNG to initial conditions are analysed. In the second stage, statistical analysis of bit-level numbers obtained from chaotic time series is performed. In the last stage, the hardware design criteria of the proposed PRNG are examined and its performance based on these criteria is compared with other studies in the literature. 4.1 Lyapunov exponent analysis The most distinctive feature distinguishing chaotic sys­tems from other nonlinear systems is the exponential sensitivity to initial conditions, also known as the But­terfly Effect. The Lyapunov exponent is one of the fre­quently used method for analysing chaos in nonlinear systems and demonstrating the sensitive dependence of the system on initial conditions. The . can be defined as the quantitative measurement of the amount of di­vergence and convergence in the phase space of two trajectories starting at very close points to each other. The existence of chaos in a nonlinear deterministic sys­ E. Erdem et al.; Informacije Midem, Vol. 50, No. 4(2020), 243 – 253 tem can be determined by looking at the sign of the . value calculated as in the Eq. 3 of at least one trajectory. For at least one Lyapunov exponent greater than zero, the behaviour of the analysed system is defined as cha­otic [18, 26]. The Lyapunov spectrum of the time series of the zigzag map obtained from the memory compo­nent in Fig. 7 (B) and the distributions of these series for the range [-1, 1] are as in Fig. 8 and 9 respectively. n - 1 . 1 ' (| = lim .ln | f xi (3) n ›. n i = 0 Figure 8: Lyapunov spectrum of the zigzag map Figure 9: Distribution of time series obtained from cha­otic system The positive Lyapunov exponent in Fig. 8 confirms that the zigzag map for x0 and m input values is in chaos and the system display a random-like behaviour. This case also shows that the chaotic system exhibits non-periodic behaviour and that orbital outputs are unpre­dictable in long-term. This also shows that the orbital outputs of the chaotic system exhibiting non-periodic behaviour are unpredictable in the long-term and in this case, cryptographically reliable random numbers can be obtained from PRNG. 4.2 Statistical randomness analysis In the presented study, NIST SP 800-22 statistical ran­domness test suite [27] is used to verify the statistical sufficiency of PRNG. The test technique consists of 15 separate subtest criteria and calculates the . and p-value parameters for each test criterion. The p-value pa­rameter, which is the probability random numbers are generated from an ideal RNG, varies in the range [0-1]. If p-value equals 1 for a test criterion, the sequence of numbers for the relevant test criterion is considered to be perfectly random. Otherwise, there is no random­ness for the relevant test criterion. The . parameter, corresponding to the typical significance level, is in the [0.001– 0.01]. range. For . = 0.01, TRNG is considered to correctly produce 99 out of every 100 random number sequences. For the numbers testing, the p-value pa­rameter for each test criterion must be greater than the . parameter [3, 28]. The sample length of each random number sequence tested is equivalent to the memory capacity in Fig. 7 (A). In other words, a random number sequence obtained from the PRNG for testing purposes at once time, consists of 524.288 (65.536x8) bits. The measured NIST 800-22 test results for PRNG are given in Table 1. Table 1: NIST 800-22 test results Test Name p value Result Frequency test 0.703 Success Frequency test within a block 0.728 Success Run test 0.594 Success Test for the longest run of ones in a block 0.512 Success Binary matrix rank 0.679 Success Discrete Fourier transform 0.912 Success Non-Overlapping template matching 0.500 Success The overlapping template matching test 0.490 Success Maurer’ s universal statistical test 0.338 Success Linear complexity test 0.697 0.415 Success Serial test 0.793 Success Approximate entropy test 0.654 Success Cumulative sums 0.871 Success In order for the outputs of any PRNG or TRNG to be used directly in cryptography, the randomness quality of the generator must be verified by statistical testing tools. In Table 1, the p-value > . condition has been fulfilled in all of the test criteria for the post-processed random E. Erdem et al.; Informacije Midem, Vol. 50, No. 4(2020), 243 – 253 numbers. In this case, where the test criteria are consid­ered successful, it can be said that the proposed zigzag map-based generator fulfils cryptographic require­ments in terms of statistical randomness. The obtained results are important in terms of showing that the zig­zag map can be used for different cryptographic pur­poses, especially random number generation methods. 4.3 Hardware performance analysis The area-energy requirement of any cryptographic RNG is important in terms of evaluating the applicabil­ity of the generator on today's cryptographic applica­tions and devices, where area-energy consumption is a major problem [3, 14]. Despite having statistically impressive results, solutions with high structural com­plexity applied for security requirement can often make an RNG dysfunctional. Therefore, hardware cost analy­sis of any RNG is important in respect to evaluating the practical usefulness of the generator. For this reason, it is important for an RNG to fulfil the security-related statistical requirements with minimum hardware cost in terms of the efficiency of the cryptographic applica­tions they are used. Although based on simple mathematical definitions, the fact that chaotic orbital outputs consist of three different equalities increases the complexity of the zigzag map in terms of hardware implementation. However, besides the ready IP modules, the dataflow designed circuit el­ements in Fig. 3 (C) and (D) reduce this complexity as much as possible in terms of hardware. Especially since the (m . xn) factor is common in all three equalities, only one multiplication circuit is used with the help of the control circuit in Fig. 3 (C) instead of three different mul­tiplication circuits. In addition, in Eq.1, 2/|m| expression is common for the first and third equalities. For any initial value of the system parameter m, the value of this ex­pression will not change during the running time of the PRNG. Therefore, instead of using extra division and ab­solute value circuits to calculate the value of this expres­sion in the implementation phase, the mathematical equivalent of this expression is defined as constant cir­cuit element as in Fig. 3 (A). This also simplifies the imple­mentation of the chaotic generator as well as reducing the area-energy demand. The area-energy consumption parameters of the proposed zigzag map-based genera­tor after the place-routing process is performed on FPGA chip are shown in Table 2. Table 3: Comparison of the main characteristics of different chaos-based RNG proposals in the literature Ref. Chaotic System Hardware Characteristic Test Tool Frequency (MHz) Post-Processing Throughput (Mbps) [8] Logistic, Bernoulli and Tent Map CMOS (0.25 µm) NIST 800-22 - - - [20] Enhanced Henon Map FPGA NIST 800-22 50 3.9 [21] Logistic map FPGA NIST 800-22 - - 1.0 [24] Bernoulli Map FPGA NIST 800-22 50 - 1.5 [29] Chua circuit CMOS (0.18 µm) FIPS 140-1 - 6-bit LFSR 2.02 [30] Coupled chaotic oscillator CMOS (0.35 µm) FIPS 140-1 NIST 800-22 1.24 Von Neumann 2.0 [31] 3D chaotic system FPGA FIPS 140-1 NIST 800-22 373 XOR 4.59 [32] Tent Map CMOS (0.18 µm) NIST 800-22 250 (KHz) 8-bit LFSR 0.25 [33] Sprott 94 G chaotic system FPGA NIST 800-22 339 - - [34] Logistic and Henon map FPGA - 190 - 1.0 [35] Piecewise-Affine Markov maps FPGA FIPS 140-1 24 XOR 60 (Kpbs) [36] Lorenz and Lü chaotic systems FPGA NIST 800-22 78 - - [37] Memristive Canonical Chua oscillator and logistic map FPGA NIST 800-22 59 XOR 0,1.25 [38] Time-delay chaotic system FPGA NIST 800-2 FIPS 140-2 120 - 4.0 [39] Sinusoidal iterator FPGA NIST 800-22 200 - 4.77 This study Zigzag map FPGA NIST 800-22 200 H function 7.7 E. Erdem et al.; Informacije Midem, Vol. 50, No. 4(2020), 243 – 253 Table 2: The FPGA chip statistics of the Zigzag map RNG Parameters (Altera Cyclone IV GX EP4CGX150DF31C8) Total FPGA Unit % Used for Zigzag Map PRNG Total Logic Elements 149.760 2.160 (1 % ) Total combinational functions 149.760 2.093 (<1 % ) Total dedicated registers 149.760 1.100 (1 % ) Total memory bits 6.635.520 93 (< 1 % ) Embedded Multipliers 9-bit 720 7 (1 %) Total pins 508 10 (2 % ) Total PLLs 8 1 (13 %) Power Dissipation (mW) Dynamic - 10.84 Static - 105.17 IO - 11.01 Total - 127.02 The results given in Table 2 show that besides its good statistical properties, PRNG can be used easily in resource-restricted embedded cryptographic applications. PRNG architecture, based on general principles in terms of mod-elling technique, is a device independent generator mod­el with low area-energy consumption, so it can be easily applied on resource restricted architectures. In addition, the generator's being based on digital design techniques and easy re-configurability feature are other important advantages in terms of hardware implementation. The output bit rate performance of the proposed zig­zag map based PRNG has been compared with other hardware based chaotic RNGs in the literature. Com­parison results are as in Table 3. When the results in Table 3 are examined, it can be seen that PRNG offers a higher output bit rate compared to other studies, al­though the output bitrate decreases by 1/2 due to the post processing technique. 5 Conclusion In this study, the hardware implementation of a new PRNG using the chaotic Zigzag map as entropy source on FPGA environment is presented. The bit-level ran­dom outputs of PRNG are obtained from the trajec­tory produced by the chaotic zigzag map for the initial value of x0. The outputs representing the 32-bit chaotic orbit in the system are transformed into bit-level ran­dom numbers / signs with the help of a simple com­parison circuit and subjected to post-processing tech­nique. While the Zigzag map is in chaos state, PRNG's post-processed outputs successfully pass the NIST 800-22 tests. Statistical randomness results confirm that the chaotic system modelled can be used for dif­ferent cryptographic purposes as well as random num­ber generation methods. In addition, the low hardware resource requirement makes PRNG easily applicable in resource-constrained hardware architectures and ap­plications. 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Arrived: 29. 05. 2020 Accepted: 27. 11. 2020 Original scientific paper https://doi.org/10.33180/InfMIDEM2020.403 Electronic Components and Materials Vol. 50, No. 4(2020), 255 – 261 Design of a Low Power and High-Efficiency Charge Pump Circuit for RFID Transponder EEPROM Labonnah Farzana Rahman1, Lubna Alam1, Mohammad Marufuzzaman2 1Universiti Kebangsaan Malaysia, Institute for Environment and Development, Bangi, Malaysia 2Universiti Tenaga Nasional, Institute of Energy and Infrastructure, Kajang, Selangor, Malaysia Abstract: The charge pump (CP) circuit is an essential part of a radio frequency identification electrically-erasable-programmable-read-only memory (RFID-EEPROM). A CP circuit generates a boosted output voltage that is greater than the power supply voltage. However, the performance of the diode configured CP circuits is strongly affected by the extra power dissipation and the parasitic capacitance. The parasitic capacitors of the CP circuit are also responsible for increased power consumption. In this research, an improved CP circuit is designed for achieving higher output voltage gain by reducing the parasitic capacitances. Moreover, the proposed course consumes less power, which makes it more suitable for low power applications like RFID transponder. The proposed CP circuit is using the internal boosted voltage for backward control where active controls are applied to the charge transfer switch (CTS) to eradicate the reverse charge sharing trends. Simulated results showed that by using 1 pF pumping capacitor to drive the capacitive output load, the proposed circuit generates 9.56 V under 1.2 V power supply. In comparison with other research, works, this CP circuit consumes less power (only 15.26 µW), which is lower than previous research works. Moreover, the proposed CTS CP circuit can operate with the efficiency of 79.3%, which is found higher compared to other research works. Thus, the proposed design will be an essential module for low power applications like RFID transponder EEPROM. Keywords: charge pump; charge transfer switch; non-volatile memory; transponder; RFID Zasnova vezja črpalke naboja z majhno močjo in visoko učinkovitostjo za RFID transponder EEPROM Izvleček: Vezje črpalke naboja (CP) je bistveni del radijsko frekvenčne identifikacije električno izbrisljivega programabilnega pomnilnika samo za branje (RFID-EEPROM). CP vezje generira višjo izhodno napetost od napajalne. Kljub temu na delovanje CP vezij močno vpliva dodatna disipacija moči in parazitska kapacitivnost. Parazitski kondenzatorji vezja CP so prav tako odgovorni za povečano porabo energije. V tej raziskavi je predstavljeno izboljšano vezje CP, ki je zasnovano za doseganje višjega ojačenja izhodne napetosti z zmanjšanjem parazitskih kapacitivnosti. Poleg tega se predlagano vezje porabi manj moči, zaradi česar je bolj primerno za aplikacije z nizko porabo, kot je RFID transponder. Predlagano vezje CP uporablja notranjo ojačano napetost za povraten nadzor, kjer je uporabljena aktivna kontrola stikala za prenos naboja (CTS) za izkoreninjenje trendov delitve povratnega naboja. Simulirani rezultati so pokazali, da predlagano vezje z uporabo črpalnega kondenzatorja 1 pF generira napetost 9,56 V pri vhodni napajalni napetosti 1,2 V. V primerjavi z drugimi raziskavami to CP vezje porabi le 15,26 µW moči. Poleg tega ima predlagano vezje CTS CP učinkovitost 79,3%. Predlagana zasnova bo tako bistveni modul za aplikacije z nizko porabo energije, kot je npr. RFID transponder EEPROM. Ključne besede: črpalka naboja; stikalo za prenos naboja; trajni spomin; transponder; RFID * Corresponding Author’s e-mail: labonnah.deep@gmail.com, lubna@ukm.edu.my L. F. Rahman et al.; Informacije Midem, Vol. 50, No. 4(2020), 255 – 261 1 Introduction A typical RFID transponder is known as data carry­ing devices in RFID systems. RFID transponder can be embedded in objects like electronic devices, luggage, pets, or human being for identification. The RFID tran­sponder is a chip or small circuit board coupled to an antenna [1]. A typical RFID chip contains mainly three blocks, such as analogue, logic, and memory blocks. To store information in the readerless RFID transpond­er, a small amount of NVM should be embedded [2] Transponder memory can contain read-only memory (ROM), Random Access Memory (RAM), non-volatile memory as EEPROM, flash memory, etc. and data buff­ers subjected to the device functionality [3]-[4]. Different types of memories exist in the market. Among them embedded NVM such as EEPROM is mostly used as tag memory in RFID, SoC, and FPGA systems. Howev­er, the prerequisites, additional masks, and fabrication steps made EEPROM and Flash memory highly expen­sive compared to a standard CMOS logic process. Many researchers wanted to develop EEPROM in a traditional CMOS logic process as it has the advantages of low cost and low power [5]-[8]. However, the maintenance and endurance features are inadequate due to the NMOS tunnelling junction or the single-ended memory cell architecture with a too-thin oxide [5]-[6]. It has a large area/bit and consumes much power as each bit cell contains its high voltage switch [7]-[8]. To generate the high voltages, an internal high-voltage generator circuit such as voltage doublers or CP circuit is required [9]. Currently, low-voltage and small size DC-DC converters are widely required for mixed-mode circuit schemes. To transform an input voltage from low to high with either a positive or reverse polarity, the CP circuit can be the vital element to encounter the demands [10]. In the CP circuit, capacitors are needed to store the energy of any devices instead of magnetic constituents. The capacitors required by the CP circuit can be small enough to be fabricated in IC. For low-power designs, CP circuits are needed to generate dc voltages higher than the power supply (VDD) or lower than the ground voltage (GND) of the memory chip. With the features of high-energy effi­ciency, small space, low power dissipation, and low cur­rent drivability, the CP circuit is chosen by the researcher as the compulsory module in EEPROM. Commonly, it is applied to the EEPROM in RFID transponder, DC-DC con­verters, and power supervision chips to write or to erase the floating-gate devices [11-13]. Dickson established the most widespread CP circuit in 1976, where the CP circuit used the diode-connected NMOS arrangement as a charge transfer device instead of switches [14] (Dickson, 1976). However, power effi­ciency and voltage gain in each stage are very low in the diode-connected CP circuit due to the body effect. Several types of research have been made to enhance the performance of the CP circuit [15-16]. Yan et al. have considered a CP with additional devices, which suffered from more power consumption for a lower current load [15]. Liu et al. proposed a CP with charge transfer switches (CTS) and parasitic capacitors to solve the problem of body effect. Besides, the CP circuit used the next pumping voltages to switch each CTSs [16]. However, the enlarged parasitic capacitance at every pumping stage decreases the pumping efficiency or the voltage gain. In 2009, Wang et al. also designed a CP circuit with the backward. They forwarded the CTS controlling method to recover the efficiency, to eradi­cate the body effect, and to escalate the voltage gain [17]. Nevertheless, the pumping efficiency or voltage gain is still lower with the PMOS switch in the output stage. In this research, an improved CP circuit using CTS with reduced parasitic capacitance is described. The designed CP circuit is capable of reducing power con­sumption and increased voltage efficiency, which is compatible with the RFID transponder EEPROM. Silter­ra 0.13 µm CMOS process is utilized to design and verify the enhanced CP circuit. The comparative study proves that the proposed design decreased the parasitic ca­pacitance, increased the pumping efficiency, and cut down the power consumption compared Liu et al. and Wang et al.’s CP circuit. 2 Materials and methods In this research, CTS is the most widely used CP design method, which has been used by many researchers in their study. In this scheme, the dynamic charge trans­fer scheme in each step is the key to enhancing the boosted charge from the lower supply voltage. Most of the previous researchers included both the NMOS and PMOS transistors to implement the diode configura­tion in CMOS, where PMOS transistors created a large substrate current in each step of the charge transfer process, which eventually increased the power dissipa­tion of the overall design. Therefore, in this research, a novel CTS-based CP circuit is proposed, where all the PMOS transistors are excluded, and NMOS transistors are utilized in all stages. This reduces the substrate cur­rent or in another term, the power dissipation of the overall circuit. The schematic diagram of the proposed CTS CP circuit is shown in Figure 1. In this research, Silterra 0.13 µm CMOS process is used to design the L. F. Rahman et al.; Informacije Midem, Vol. 50, No. 4(2020), 255 – 261 schematic of the proposed CP circuit. From Figure 1, it is shown that one diode-configured MOSFET MD1 is utilized in this design to initiate the voltage from the supply voltage VDD to start the charge transfer process from one stage to another, whereas, another MOSFET MD2 is connected with the output stage of the circuit. On the other hand, transistors (MS1–MS9) are required to control the CTS and to transmit the boosted charges from the first stage to last using the backward charge transfer scheme. As all the CTS switches from MS1–MS9 does not entirely turn “OFF” during this transfer pro­cess, additional controlling transistors MN1 to MN9 and MP1 to MP9 are added in this design. Figure 1: Schematic diagram of the proposed CTS based CP circuit. In this research, when the clock signal CLK is in a high state, and the anti-phase clock signal CLKB is in a low condition, the gate of transistor MS2 is turned ON at the time of the charge pump process, which holds the amplitude of VDD as the pass transistor MN2 is switched OFF and MP2 is switched ON. Therefore, tran­sistor MS2 has the value of VDD to node 2. On the other hand, when CLK is in a low state, and CLKB is in a high condition, the pass transistor MN2 is turned ON, and MP2 is turned OFF. Therefore, the gate voltage of MS2 becomes zero, which turns OFF the MS2 transistor en­tirely and the entire CP circuit feedbacks the charges from stage one to the next. In this design process, the total performance of the circuit closely depends on the sizing of the transistors. In this topology, zero Vth MOS-FETs help to overcome the threshold voltage drop at each stage, which helps to boost the pumping process of this scheme. Usually, the amplitude of the Vclk is same as VDD, in this scheme. Thus, the voltage variation and the voltage fluctuation of each pumping node can be expressed as, .. (1) VV =V CLK DD Cpump I o .= VV - (2) CLK C + Cf .( C +C ) pump par pump par where VCLK is the voltage amplitude of the clock signals, is the pumping capacitance, C is the parasitic pumppar capacitance of each pumping node, Io is output cur­rent, and f is the clock frequency. If Io is small enough, and C is large enough, Ican be ignored from equa­ pumpo tion (2). Hence, the output voltage of the N-stage CP circuit can be expressed as Vout = N. ( VDD -VD ) (3) where VD is the cut-in voltage of the pn-junction diode and N is the number of the stages taking part in pump­ing. The ripple voltage is defined as: Iout Vripple= (4) f Cout where, Cout is the load capacitance, which is ignored to calculate the ripple voltage of the proposed CP circuit. The number of stages determines the power efficiency because of Vout and VDD, which are determined by the specific CMOS process [18]. Die layout of the proposed CP circuit with I/O padded structure is shown in Figure 2, where the CP circuit without I/O pad occupies only a small area of 224.2 µm × 73.2 µm. During the design process, all transistors and capacitors are placed in a manner that reduces the mismatch and parasitic capacitance. Figure 2 shows the chip layout of the proposed CP circuit with I/O pads. Figure 2: Die layout of the proposed CP circuit with I/O pads. 3 Results and discussions The operating temperature was set to 27o C for the CTS CP circuit and the ELDOSPICE simulator (Mentor Graph­ics) was used within Silterra 0.13 µm CMOS process. VDD for simulating the outputs is set to 1.2 V. The sim­ulated behaviour of the CTS CP circuit is illustrated in Figure 3. Figure 3 shows the simulated output voltage waveform of the proposed eight-stage CP circuit with L. F. Rahman et al.; Informacije Midem, Vol. 50, No. 4(2020), 255 – 261 2pF pumping capacitors. Ideally, the output voltage of the designed eight-stage CP circuit with power supply voltage VDD= 1.2 V should be as high as 9.6 V (1.2 x 8 = 9.6 V). However, the output voltage of the proposed CP circuit is decreased due to some parasitic capacitances at every pumping node and the loading of the output current. Therefore, the simulated output voltage of the proposed CP circuit is achieved Vout= 9.56 V. Figure 3: The simulated waveform of the proposed CTS CP circuit. In this proposed design, both the clock signals (CLK and CLKB) amplitude is set to 1.2 V as same as the supply volt­age. The circuit is simulated using 10.2 MHz clock frequen­cy to observe the pumping performance of the proposed CP circuit. If the clock frequency is increased, the charge is transferred over a fixed time interval from one step to an­other in a faster way, which also increases the output volt­age. At 50 MHz clock frequency, the proposed CP circuit exhibited the best performance. In this proposed design, increasing the clock frequency raises the output voltage gain, but incomplete charge transferring occurs if the cir­cuit operates above 50 MHz clock frequency. On the other hand, the proposed CP circuit is simulated for all 45 corners. In this research, 3 Vcc (1.1 V, 1.2 V, and 1.3 V), three temperatures (-400C, 270C and 1250C), and five corners are examined, as shown in Figure 4. This corner analysis and process variation tests ensure the proposed CTS based CP circuit function correctly with­in manufacturing tolerances, which is compulsory in CMOS design. The corner test results revealed that the proposed CP circuit could function properly at different corners of VDD and temperature. The proposed design of the CP circuit achieved output voltage Vout = 9.56 V, which is higher than recently pub­lished research works, as shown in Figure 5. The simu­lated results discovered that [16] and [19] CP circuits achieved poor Vout due to threshold voltage loss and high parasitic capacitances in every node of the pump­ing stages. Conversely, to compare the simulated re­sults with recently published research works, this pro­posed design is tested with different supply voltages, which is shown in Figure 5. From this comparison, it is evident that this novel CP circuit performed better than other research works for all the supply voltage values from 1.2 V to 2.4 V. Figure 5: Comparison of output voltages against sup­ply voltages among [16],[19] and this work under 1.2 .>ZL2 for alleviating the load­ing effect of the second stage. By neglecting the gate-to-drain capacitance (Cgd), the input impedance of the second stage (ZIN2) in case of .<<.T is obtained as fol­lows: LC s 2 + 1 4 gs 3 Zs = (1) 2 () IN ( C +C ) s gs 3 gs 4 (a) (b) Figure 3: Schematic of the modified inverter-based LNA. Higher gain is achieved by a second inverter-based LNA, which is connected in series with the first stage. However, the impedance mismatch between stages can result in ripples in the passbands, but using the stagger tuning technique results in flat gain over low frequency to 5.2-GHz. Figure 4 shows the proposed two-stage wideband LNA. Figure 4: Schematic of the proposed wideband LNA. The small-signal equivalent circuit of the proposed wideband LNA is shown in Figure 5. As can be seen, the feedback resistors of R1 and R2 are placed in parallel with the gate to drain capacitances (Cgd) to provide the wideband input matching. At the frequencies of inter­est, the impedances of the gate to drain capacitances Figure 5: The small-signal equivalent circuit of the LNA (a) second stage and (b) first stage of the wideband LNA. The overall voltage gain of the proposed wideband LNA is given by: A , = Av 1 ×A (2) vT v 2 where, Av1 and Av2 are the voltage gain of the first and the second stages, respectively. Based on the small-sig­nal analysis, Av1 can be expressed as below: LC g s 2 + g 3 gs 1 m 2 mT 1 As ) (3) ()=- ( RZ Z LC s +1 3 gs 1 where gm represents the transconductance of the MOS transistor, and g=g+g is the overall transcon­ mT1 m1m2 ductance of the first stage. Similarly, Av2 is obtained as follows: LC gs 2 + g 4 gs 3 m 4 mT 2 A () s =- ( RZ ) (4) V 22 2 L 2 LC s +1 4 gs 3 where g=g+g is the overall transconductance of mT2 m3m4 the second stage. By assuming a small value for R1 and high value for R2 and regarding (2), Av,T is given as fol­lows: A. Bijari et al.; Informacije Midem, Vol. 50, No. 4(2020), 263 – 274 . g . m 22 LC s + 1 . 3 gs 1 . . gmT 1 . A () s . gg RZ × , mT 1 mT 21 vT L 2 LC s 2 + 1 ( 3 gs 1 ) (5) . g 2 . LC s + 1 . 4 gs 3 m 4 . . gmT 2 . LC s 2 + RC + Cs +1 ( 4 gs 31 ( gs 3 gs 4 )) By assuming R/L>5.2 GHz, Acan be simplified as: 14v,T 22 . s .. s . 1 + 21 + 2 ... . . ... .. z 1 z 2 As . gg RZ , () mT 1 mT 21 22 (6) VT L 2 ... . ss 1 + 1 + . 2 .. 2 . .. . p 1 .. p 2 . From (5) it can be seen that Av,T has four resonant fre­quencies .and ., that expressed by: p1,2 z1,2 .= 1 (7) p 1 LC 3 gs 1 p 2 LC .=1 (8) 4 gs 3 . z 1 = 1 g (9) m 2 LC 3 gs 1 g .= 1 mT 1 z 2 g (10) m 4 LC 4 gs 3 g mT 2 From equation (6), it can be seen that the overall volt­age gain is proportional to g, and R (Zcan be affect­ mTi1L2 ed by load resistance). Since the input matching, power dissipation, and bandwidth limit the values of gmT1 and R1, the gain of the proposed wideband LNA can be ad­justed by gmT2. Moreover, the high band of the DB-LNA can be shaped by tuning .p1 around 5.2-GHz. Figure 6 shows the overall frequency response of the proposed wideband LNA along with the frequency responses of the first and second stage. As can be seen, the proper roll-off in the upper-frequency response is achieved by setting . close to . z1p1. 2.2 Input impedance Impedance matching over a wide band is one of the most challenging tasks in wideband LNA design. The input matching condition of the inverter-based LNA can be improved by applying the shunt-shunt resistive Figure 6: The frequency response (|Av,T|) of the pro­posed wideband LNA. feedback and inserting an inductor in series with the gate of the NMOS transistor. According to equation (1) and assuming R1/L4>5.2-GHz, the input impedance of the proposed wideband LNA in case of .<<.T is ex­pressed by: 1 + RC + Cs 1 + LC s 2 ( 1 ( gs 3 gs 4 ) )( 3 gs 1 ) Z () (11) s = IN g 1 +LC s 2 mT 1 ( 4 gs 3 ) As mentioned earlier, by assuming .p1 around 5.2-GHz, ZIN(s) can be simplified as follows: 1 + jRC .( gs 3 + C ) 1 gs 4 IN .. g 1 -LC . 2 Z () (12) mT 1 ( 4 gs 3 ) As can be seen, the input impedance is proportional to g, and L, thereby the trade-off between the gain mT1, R14 and input matching can be reduced by only employing gmT1 for satisfying the input matching condition. 2.3 Noise figure The noise performance of the wideband LNA is evalu­ated by assuming the thermal noise of the transistors and the resistors as the dominant noise sources, and the flicker noise is neglected. The loss of inductors is Figure 7: The simplified circuit of the wideband LNA for noise analysis. A. Bijari et al.; Informacije Midem, Vol. 50, No. 4(2020), 263 – 274 neglected, and it is also assumed L3 and L4 resonate with the total capacitance at the input node of the first and the second stage, respectively. According to the mentioned conditions, the simplified circuit for noise calculation is derived, as shown in Figure 7. The noise figure (NF) of the wideband LNA is given by: 2 1 vno NF =, ut (13) Avs 24 KTR s where A is the voltage gain from v to v, and regard- vsSOUT ing RIN.R1/2, it can be expressed by: R 1 A () s =( gRg R ) (14) o 22 Vs 1 mT 11 mT o R 1 +2 Rs where Ro1 and Ro2 represent the output resistance seen at the output nodes of the first and the second stage, respectively and they are given as: Rs + R 1 R .Z (15) o 1 L 1 gR mT 1 s gRR + R mT 12 s 1 Ro 2 . ZL 2 (16) gR + g ( R +R ) mT 1 s mT 21 2 According to Figure 7, the total output noise is ex­pressed as: (17) Figure 8: The contours of NF for ID3=2 mA, R2=5 k., and V=V=0.2 V. eff1 eff3 where . represents the ratio of gm to the zero-bias drain conductance gd0, and . is the MOS transistor thermal noise coefficient. Figure 8 shows the contours of NF(g) in the case of I=2 mA, R=5 k. and mT1, R1D32 V=V=0.2 V. As shown in Figure 8, there is a trade­ eff1 eff3 off between R1 and gmT1 at a specific NF, and the proper NF can be achieved by choosing higher values for R1 and g. Additionally, R and g are limited by input mT11mT1 matching, and thereby, a lower NF can be achieved re­garding proper input matching and power dissipation. 2.4 LC network As mentioned earlier, the circuit design starts with the design of a wideband LNA that exhibits a high flat gain over the low frequency to f2=5.2-GHz. It should be not­ed f2 is defined by fp1. It is assumed that the receiver receives two frequency bands concurrently without us­ing switches. Therefore, concurrent DB-LNA is a devel­opment based on a multiband theory to achieve dual-band characteristics. For this purpose, an LC network is inserted in the LNA output to achieve the require­ments with minimum effect on the gain, NF, and input matching. The proposed LC network determines the low band of the concurrent DB-LNA and enhances the spurious frequency rejection at the low frequency. Fig­ure 9 shows the proposed LC network. As can be seen the low band of f1=2.4-GHz and the notch frequency of f3=3.5-GHz are realized by L1, L2, and C2 as follows: 1 f = 12 . ( LLC +) (18) 1 22 1 f = (19) 32 . LC 22 Figure 9: The proposed LC network used at the DB-LNA output. Additionally, the frequency calibration method can be realized by using a varactor to tune the frequency shift due to the process variation. Figure 10 shows the fre­quency response of the proposed DB-LNA determined by the LC network. A. Bijari et al.; Informacije Midem, Vol. 50, No. 4(2020), 263 – 274 As shown, the proposed concurrent DB-LNA exhibits the operating frequencies of f1=2.4-GHz and f2=5.2­GHz. 3 Simulation results The proposed concurrent DB-LNA is designed and simulated using Cadence Spectre-RF with 0.18 µm CMOS technology. The post-layout simulation results are reported in the paper, which take into account lay­out parasitic capacitances. The power supply of 1.5 V is used, and the minimum channel length is considered for all transistors. The first stage is designed to achieve moderate gain, low NF, and proper input matching over the lower frequencies to 5.2-GHz. Transistors M1 and M2 have the same width of 165 µm, while M1 is biased at gate-source voltage (v) of 0.64 V, thereby g= 60 gs1m1 mA/V and g=25 mA/V. A higher g value reduces the m2mT1 NF, but increases the power dissipation and degrades the input matching. According to (7) and (9), the .z1 is located at about 1.85.p1, thereby providing a proper roll-off at the upper-frequency band. The second stage enhances the gain and obtains a flat gain over a wide frequency band. For this purpose, the transistors M3 and M are designed to have g=90 mA/V and g=10 4m3m4 mA/V, while M3 is biased at vgs3=0.54 V with the total width of 310 µm, and M4 has the width of 50 µm. The transistor dimensions chosen above and, according to (11) and (13), lead to L3=4.2 nH, L4= 2 nH, R1=135 ., and R2=1.5 k.. Figure 11 shows the simulated power gains of the two separate stages and the proposed wideband LNA operating over the low frequencies to 5.2-GHz. As shown in Figure 6, if the resonant frequencies of Aand A are properly optimized, such as placing . v1 v2p2 at approximately 4-GHz and .p1 at 5-GHz while keep­ing reasonable input-matching, a wideband flat pow­er gain is expected. The dual-band gain response is achieved when the LC network is inserted at the output of the wideband LNA. Resonating at 3.8-GHz, L2 and C2 result in a very low output impedance. C2 is chosen to be about 1.4 pF, while L2 is adjusted about 1.5 nH. From (21), it can be seen that the low band operation of f1=2.4-GHz is achieved with L1=1.6 nH. Table 1 lists the optimized component values of the concurrent DB­LNA and the bias current of transistors. Table 1: Parameters and their values. Component Symbol Value Current (mA) Transistor (Finger×W(µm)× L(µm)) M1 (34×4.8×0.18) 5 M2 (50×3.2×0.18) 5 M3 (46×6.8×0.18) 2.2 M4 (25×1.8×0.18) 2.2 Inductance (nH) L1 1.6 L2 1.5 L3 4.2 L4 2 Capacitance (pF) C2 1.4 CC 5 Resistance(.) R1 135 R2 1500 Bias (V) VDD 1.5 Figure 12 shows the layout of the proposed DB-LNA, occupying 0.55 mm×0.48 mm chip area, excluding the pads. The post-layout simulated power gain (S21) and input return loss (S11) of the concurrent DB-LNA are shown in Figure 13 and Figure 14, respectively. As shown in Fig­ure 13, the balanced amplitude of the gain at the oper­ A. Bijari et al.; Informacije Midem, Vol. 50, No. 4(2020), 263 – 274 ating frequencies of 2.4-GHz and 5.2-GHz is achieved by choosing L1=1.6 nH and L2=1.5 nH. Figure 14 shows the value of gmT1 that determines the input matching range. As shown in Figure 14, the simultaneous dual-band input matching smaller than -10 dB is achieved by choosing the gmT1 smaller than 85 mA/V. However, the smaller values of gmT1 can potentially achieve a higher noise figure up to 2 dB and yield a substantially lower gain. Noise analysis for the concurrent DB-LNA is carried out for R1=135 ., as shown in Figure 15, in which the NF is 4.2 and 4.6 dB at the operating frequencies of 2.4-GHz and 5.2-GHz, respectively. The effect of R1 on the noise performance of the proposed DB-LNA is also evaluated Figure 14: The simulated S11 of the concurrent DB-LNA in Figure 15 by varying the value of R1. As shown in Fig­ure 15, higher R1 results in lower NF for both frequency bands. However, higher values of R1 cause substantial peaking at the low band of the proposed DB-LNA. Figure 15: The simulated NF of the concurrent DB-LNA. Figure 16 shows the third-order intermodulation inter­cept point (IIP3) simulations of the concurrent DB-LNA. The IIP3 is carried out by applying a two-tone test with 4-MHz frequency spacing. As shown in Figure 16, the post-simulated IIP3s are -6 dBm and -11 dBm at 2.4­GHz and 5.2-GHz, respectively. Figure 17 shows the stability factors based on the S-parameters to consider the stability of the proposed DB-LNA. The necessary and sufficient conditions for unconditional stability are expressed as follows: 2 - 2 + 1 - SS - SS S 11 S 22 1122 1221 >1 (20) K = 2 12 SS 21 <1 (21) . = SS 12 SS 11 22 - 21 A. Bijari et al.; Informacije Midem, Vol. 50, No. 4(2020), 263 – 274 As shown in Figure 17, the concurrent DB-LNA satisfies the conditions for unconditional stability at both fre­quency bands. Monte Carlo analysis is carried out on the proposed DB­LNA to evaluate the effects of components mismatches on performance parameters such as S21, NF, and S11. In Monte Carlo simulation with 1000 iterations, a 2% mis­match with Gaussian distribution for all circuit compo­nents is considered. As shown in Figures 18 and 19, the mean S21 of 13.97/14.11 dB (nominally 13.73/14.11 dB) with a standard deviation of 0.21/0.45 are obtained at the operating frequencies of 2.4/5.2-GHz. The results show a mean NF of 4.18/4.72 dB (nominally 4.25/4.67 dB) with a standard deviation of 0.06/0.13 at the op­erating frequencies of 2.4/5.2-GHz. In addition, mean S11 of -12/-13.35 dB (nominally -12.95/-14.64 dB) with a standard deviation of 0.28/0.88 is obtained at the oper­ating frequencies of 2.4/5.2-GHz. (a) (b) (c) 2111. As seen in Figures 18 and 19, the Monte Carlo simula­tion results confirm the low sensitivity of the proposed DB-LNA to process variations at both frequency bands. The process corner cases and temperature variation are simulated at the operating frequencies, and the results are listed in Table 2. The proposed DB-LNA is also simu­lated over the power supply variation, and the results are listed in Table 3. Table 4 has compares the performance of the proposed DB-LNA with similar reported works. A figure of merit (FoM) in both bands, which allows comparison be­tween the concurrent DB-LNAs, is defined as follows: A. Bijari et al.; Informacije Midem, Vol. 50, No. 4(2020), 263 – 274 (a) (b) (c) 2111. S dB . 10 × f × f . 21 () . 20 12 . (22) FoM = 10 log 11 dB . NF dB () S () . . 10 20 . 10 × 10 × ()× Size mm ( PW ) . 2 . where f1 and f2 represent the centre frequencies of the low band and the high band of the concurrent DB-LNA, respectively. According to Table 4, the DB-LNA in (Roo­bert & Rani [25]) presents a high power gain and low NF at both bands. However, its operating frequencies are lower than those of the proposed DB-LNA. Moreover, (Neihart et al.,[26]) achieves a low power DB-LNA. How­ever, it suffers from the unbalanced amplitude of the gain at the operating frequencies. As seen in Table 4, the proposed circuit exhibits high and balanced ampli­tude of the gain and excellent input matching, moder­ate linearity, and power dissipation. 4 Conclusion This paper proposed and analytically investigated an inverter-based concurrent dual-band LNA (DB-LNA) operating at 2.4/5.2-GHz. By inserting an LC network at the wideband LNA output, the dual-band operation is achieved. Analytical expressions for the gain, input matching, and noise figure are presented. In addition, the trade-off between the noise figure, and the input matching is detailed. The post-layout simulated circuit exhibits 13.7 dB/14.1 dB power gain and 4.2 dB/4.6 dB noise figure at 2.4 and 5.2 GHz, respectively. Moreover, it draws a current of 7.2-mA from 1.5 V supply. Com­pared to other DB-LNAs, the proposed LNA presents a high balanced gain, proper roll-off, and good input matching. The proposed concurrent DB-LNA could thus be a good choice for multiband receivers. Table 2: The performance of the proposed DB-LNA for different process corners and temperature Parameter S21 (dB) NF (dB) S11 (dB) PC (mW) IIP3 (dBm) FF@-40 °C 19.3/22.9 2.9/3.4 -8.9/-17.1 16.6 -7/-8.5 TT@27 °C 13.7/14.1 4.2/4.6 -12.9/­14.6 10.8 -6/-11 SS@85 °C 7.9/6.4 5.9/6 -21.7/-12 7.4 -6.5/-8 Table 3: The performance of the proposed DB-LNA for power supply variation VDD (V) ±10% S21 (dB) NF (dB) S11 (dB) PC (mW) IIP3 (dBm) 1.35 9.3/8.4 4.8/4.7 -17.8/-13.6 5.6 -10/-12.4 1.8 13.7/14.1 4.2/4.6 -12.9/-14.6 10.8 -6/-11 1.65 16.6/17.9 3.9/4.7 -11.2/-13.4 18.1 -2/-8.5 5 Conflict of interest The authors have no affiliation with any organization with a direct or indirect financial interest in the subject matter discussed in the manuscript. A. Bijari et al.; Informacije Midem, Vol. 50, No. 4(2020), 263 – 274 Table 4: The performance summary of the proposed concurrent DB-LNA and comparison with state-of-the-art con­current DB-LNAs Ref. Tech. (nm) f0 (GHz) S21 (dB) NF (dB) S11 (dB) IIP3 (dBm) VDD (V) Power (mW) Size* (mm2) FoM [20] 130 2.4 19.3 3.2 -16.8 -20.1 1.2 2.4 - - 5.2 17.5 3.3 -19.4 -18.1 - [21] 130 2.05 14.9 4 -8.6 -2 1.2 12 0.44 5.8 5.65 14.9 4.8 -32.4 -4.2 16.9 [25] 180 0.9 15 1.9 -10 -6 1.2 12 0.58 3.8 2.4 16 2 -15 -2 6.7 [26] 180 2.4 14.2 4.4 -14 3.4 1.8 7.2 0.61 8.7 5.2 14.6 3.7 -13.5 -2.7 9.4 [27] 180 2.4 10.8 3.25 -15 4.5 1.8 11.7 0.85 5 5 8 4.1 -11 3 0.9 [28] 90 0.9 22 2 -21 -5.5 0.5 5.2 0.091 24.3 2.3 24 2.7 -15 -6.65 21.6 [29] SISL Avago ATF36163 2.45 28.4 0.7 -13 -6.6 1 36 - - 5.25 28.8 1.1 -20 -5.1 - [30] 130 2.45 9.4 2.8 -12.6 -4.3 1.2 2.79 0.36 14 6 18.9 3.8 -21 -5.6 21.9 [31] 180 1.217 13 1.58 -10.6 - 1.8 11.6 0.14 9.5 1.568 11.5 3.1 -10.7 - 7.3 [32] 180 2.4 20 6.6 -7 - 1.8 15 0.225 7.1 5.25 8 6.6 -12 - 3.6 [33] 150 PHEMT 2.4 20 2.2 -19 -8.5 3 37.8 1.15 6.3 5 15 2 -13 -4 1 This work 180 2.4 13.7 4.2 -12.9 -6 1.5 10.8 0.265 10 5.2 14.1 4.6 -14.6 -11 10.6 *Excluding Pads 6 References 1. M. K. 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Arrived: 14. 08. 2020 Accepted: 28. 12. 2020 Original scientific paper https://doi.org/10.33180/InfMIDEM2020.405 Electronic Components and Materials Vol. 50, No. 4(2020), 275 – 283 Multiband Stepped Antenna for Wireless Communication Applications Abdelhalim Chaabane1, Omar Mahri1,2, Djelloul Aissaoui3,4, Nassima Guebgoub1 1Université 8 Mai 1945 Guelma, Laboratoire des Télécommunications-LT, Département d’Electronique et Télécommunications, Faculté des Sciences et de la Technologie, Guelma, Algeria 2University of Brothers Mentouri Constantine 1, Faculty of Science and Technology, Constantine, Algeria 3University of Djelfa, Faculty of Science and Technology, Djelfa, Algeria 4University of Tlemcen, Telecommunication Laboratory, Faculty of Technology, Chetouane, Tlemcen, Algeria Abstract: In this paper, a novel design of a coplanar waveguide fed (CPW) triple-band antenna is introduced. An ultra-wideband (UWB) characteristic is achieved by the initial design through the cut of a stepped shape from the lower part of the initial radiating patch and through the use of a truncated ground plan. To avoid the effects of the electromagnetic interferences with some co­existing wireless communication systems, a transition from the UWB to multiband function is assured by etching a simple circular ring inside the radiating patch. The antenna is printed on the low-cost FR4-substrate having a compact size of 0.162.0×0.123.0×0.008.0 at 1.57 GHz. The design and the analysis of the antenna were done using the commercially software CST Microwave StudioTM while the fabricated prototype was tested and measured by using a R&S®ZNB Vector Network Analyzer. The measurements show that the fabricated prototype resonates between 1.57-2.33 GHz (38.97%), 5.84-6.41 GHz (9.31%), and 7.93-10.88 GHz (31.37%). Besides, the proposed antenna has consistent measured radiation pattern characteristics and it also reveals an acceptable realized gain and a high efficiency over the working ranges. Hence, the designed antenna can be a good candidate for many wireless communication systems. Keywords: Multiband antenna; slot antenna; triple-band antenna; coplanar waveguide fed; wireless communication systems Večpasovna stopničasta antena za brezžične komunikacijske aplikacije Izvleček: V prispevku je predstavljena nova zasnova troplastne antene s koplanarnim valovodom (CPW). Karakteristiko ultraširokega pasu (UWB) dosežemo z rezom stopničaste oblike osnovne zasnove spodnjega dela začetne sevalne krpice in z uporabo zmanjšane talne ravnine. Da bi se izognili učinkom elektromagnetnih motenj nekaterih soobstoječih brezžičnih komunikacijskih sistemov, je zagotovljen prehod z UWB na večpasovno funkcijo z jedkanjem preprostega obroča znotraj sevalne krpice. Antena je natisnjena na poceni substrat FR4 z velikostjo 0,162.0 × 0,123.0 × 0,008.0 pri 1,57 GHz. Načrtovanje in analiza antene sta bila narejena s komercialno programsko opremo CST Microwave StudioTM, medtem ko je bil izdelani prototip testiran in izmerjen z uporabo R&S®ZNB Vector Network analizatorjem. Meritve kažejo, da izdelani prototip resonira med 1,57–2,33 GHz (38,97%), 5,84–6,41 GHz (9,31%) in 7,93–10,88 GHz (31,37%). Poleg tega ima predlagana antena dosledno izmerjene karakteristike vzorcev sevanja in razkriva sprejemljivo ojačenje in visoko učinkovitost v delovnih območjih. Zasnovana antena je lahko dober kandidat za številne brezžične komunikacijske sisteme. Ključne besede: večpasovna antena; režna antena; tropasovna antena; napajan koplanarni valovod; brezžični komunikacijski sistemi * Corresponding Author’s e-mail: chaabaneabdelhalim1979@gmail.com, abdelhalim.chaabane@univ-guelma.dz A. Chaabane et al.; Informacije Midem, Vol. 50, No. 4(2020), 275 – 283 1 Introduction Nowadays, the wireless communication field is one of the important technologies due to many services that offers for our daily life [1]. The Ultra-Wideband (UWB) technologies have acquired an impressive and vast appreciation in the wireless world owing to their ad­vantages. Due to the prompt and vigorous develop­ment in the wireless domain, the UWB systems can easily interfered with other co-existing narrowband systems. To avoid potential interferences, the develop­ment of multiband antennas has received widespread concentration in recent years for designing efficient compact multi-functional devices [2-4]. Thus, there are strong demands to design multipurpose antennas which should ensure a multiband operation with suit­able characteristics, such as: compact structure, low manufacturing cost, low-profile, easy integrating cir­cuit boards and good radiation performances over the working bands [5-6]. Until now, with the use of a vari­ety of techniques, various types of multiband antennas have been presented in the literature for many wireless communication systems application such as those pro­posed in [5-14]. Among of usual employed techniques to produce multiband function in broadband anten­nas included the technologies: fractals [7-9], multi­layer [10-11], meta-materials [12], stubs loaded [13], slot-etched [14], loading the matching network [15], and radiators coupling [16]. Complex Sierpenski Gas­ket slots have been introduced in [7] for the produc­tion of multiband function. In [8], a multiband antenna has been proposed for IMT2000, GSM1800/1900 and LTE applications; its drawbacks are its large size which is about of 58×40×1.6 mm3, and its very complicated wheel-like fractal structure. In [9], a multiband antenna for mobile terminals application has been proposed; it has large dimensions and uses a complicated binary tree fractal bionic structure to produce only a dual-band function. Whilst, a complex multilayer design constructed by periodic structures has been reported in [10] for dual-band application; its big size is another main drawback. A very selective antenna has been pro­posed in [11] for LTE-R and 5G lower frequency opera­tions. In addition to the enormous size that presents of about 180×60×3.2mm3 it has a complicated structure and very sharp working bands. By the incorporation of split ring resonator meta-material loads, a volumi­nous less efficient antenna which has sharp and close working bands has been proposed in [12]. The same problem of a weak separation between the different bands has been obtained by the designed antenna in [13]. In [14], two thin U-shaped inverted slits etched on a pentagon patch have been presented for WiMAX and WLAN applications where the presented design has good performances but it is large in size. In [15 ], a triple-band ground radiation antenna excited through a Balun has been designed where the voluminous size of the designed structure is about 70×26×0.8mm3. As well in [16], a multiband antenna has been proposed for many wireless communication systems, but this structure has a large physical size and sharp working bands. Thereby, the antennas mentioned above have complex structures and/or large sizes. Thus, there is a strong need to design simple antennas with reduced size for multi-systems application. A simple compact CPW-fed triple-band antenna for wireless communica­tion systems application is presented in this paper. The triple-band operation is achieved by etching a simple split-shaped circular ring on the radiating element. The designed antenna was firstly calculated and optimized using the commercially software simulator CST Micro­wave StudioTM. To justify the calculated results, a proto­type for the proposed design was realized and meas­ured by R&S®ZNB Vector Network Analyzer and it also was tested and measured in an anechoic chamber. The main antenna parameters such as current density dis­tributions, voltage standing wave ratio, antenna gain and efficiency are explored. 2 Antenna geometry and results The front view and the dimensions of the proposed multiband antenna are presented in the Figure 1. Its main structure includes a stepped rectangular radia­tor and a constricted ground plane. To mitigate the effects of the electromagnetic interferences between the UWB systems and some narrow bands co-existing wireless communication systems (Bluetooth, LTE2600, WiMAX, WLAN, and X-band downlink satellite system), Figure 1: Configuration of the proposed multiband an­tenna. A. Chaabane et al.; Informacije Midem, Vol. 50, No. 4(2020), 275 – 283 a multiband function is introduced by etching a split-shaped circular ring on the radiating patch. The anten­na is designed on a shipper substrate FR4-Epoxy hav­ing a relative dielectric constant of 4.4 and an overall size of 0.162.0×0.123.0×0.008.0 at 1.57 GHz. Figure 2 depicts the designed antenna with and without the split-shaped circular ring. All the physical dimensions of the designed CPW-fed multiband stepped antenna were adjusted and op­timized individually, by the use of the commercially software CST Microwave StudioTM, to attain good per­formances especially in terms of working bandwidths, radiation patterns, and gain. The detailed dimensions of the proposed multiband antenna are listed in Table 1. Table 1: Optimized dimensions of the proposed multi-band antenna. (a) (b) Figure 2: Antenna before and after etching the split-shaped circular ring, (a) First antenna, (b) Final antenna. In order to understand the role of the etched split-shaped circular ring, the antenna is simulated before and after its introduction and the obtained results are illustrated in Figure 3. It can be clearly shown that the split-shaped circular ring permits the transition from UWB to multiband function. The proposed radiating patch has a stepped shape that is created by cutting the metal from its low­er part characterized by a high current distribution. The purpose of this cut is to affect the mutual and the ca­pacitive coupling between the radiating patch and the truncated ground plane. In results, a good adaptation and a larger impedance bandwidth are achieved. Like­wise, a lighter weight can be obtained; that is essen­tially wanted from the miniaturization viewpoint. Be­sides, more level of flexibility in the design and possibly minimized conductor losses are achieved. Based on the other published works like [17], the lower resonant fre­quency fr (in GHz) of conventional printed monopole antennas can be evaluated by the equation (1). 7.2 fr = (1) LW /2 .+ + s Here, L and W are the length and the width of the mon­opole; s is the gap separating the ground plane and the lower part of the radiator. The dimensions L, W, and s are taken in cm. Parameters Dimensions (mm) w1 23.5 w2 2.19 w3 1.98 w4 0.77 w5 3.83 w6 8.84 w7 2.8 w8 21 L1 17 L2 1.98 L3 4.29 L4 1.77 L5 1.5 R1 9 R2 8.5 Figure 3 indicates that by etching the split-shaped cir­cular ring on the stepped radiating element, a transi­tion from the UWB to multiband operation is produced. Figure 3: Role of the etched split-shaped circular ring on the VSWR characteristic of the proposed antenna. The real and the imaginary parts of the impedance are depicted in Figure 4. Except around the notched bands, A. Chaabane et al.; Informacije Midem, Vol. 50, No. 4(2020), 275 – 283 the real impedance is about the input impedance of the excitation port value (50 .) over the operating bands. Beside, the imaginary part is almost vacillating around zero line throughout the operating bands. The Figure 5 reveals a collection of powers at the input and the output of the antenna. A good concordance can be shown between the accepted power and the radiated one which confirms a well adaptation of the antenna. Since the efficiency parameter is evaluated from the ratio of the radiated power to the accepted one, thus high level values of efficiency can be predicted at the working bands. Besides, very low power outgoing the port (i.e. power reflected back out of the input port) around the working bands is revealed, and is nearly equal to the accepted one around the rejected bands. The current distribution on the surface of the de­signed antenna at the resonant frequencies of the two rejected bands is shown in Figure 6. It can be shown that at the two rejected resonant frequencies the cur­rent distribution is mightily concentrated on the split-shaped circular ring. A feeble current flowed along the rest parts of the radiating element is observed upholds the full contribution of the etched split-shaped circular ring on the rejection of the two bands and for the pro­duction of the triple-band operation. Figure 7 shows a photo of the fabricated prototypes (UWB and multi-band antennas) that are graved, by using a laser printer (LPKF S103), on the FR4-substrate with a whole size of 0.162.0×0.123.0×0.008.0 at 1.57 GHz. (a) (b) Figure 6: Surface current distribution on the surface of the antenna at two frequencies (a) 3.5 GHz, (b) 7 GHz. To check the antennas operating frequencies, the volt­age standing wave of the fabricated antennas was measured using an R&S®ZNB Vector Network Analyzer. Good agreements between the simulation and experi­mental results are achieved and the multiband char­ A. Chaabane et al.; Informacije Midem, Vol. 50, No. 4(2020), 275 – 283 (a) acteristic of the antenna is demonstrated after etch­ing the split-shaped circular ring. The small mismatch between the simulated results and the measured ones may be attributed to the intolerance in the fabrication and measurement processes, losses in port connec­tion, and to inadmissible effects of the soldering that can affect the current distributions by creating para­sitic inductance and capacitance links, and may be also due to the external disturbances which were not taken into account in the simulations. From the experimental results (Figure 8), the VSWR of the antenna covers the bands 1.57-2.33 GHz (38.97%), 5.84-6.41 GHz (9.31%), and 7.93-10.88 GHz (31.37%) covering the bands allo­cated to GSM1800, GSM1900, UMTS, GPS, GLONASS, DCS, PCS, TD-SCDMA, WCDMA, CDMA2000, DSRC, ITU8, and X band radar. It is evidently perceived that the introduction of the simple split-shaped circular ring on the patch of the designed antenna is responsible for the transition from the UWB to the multiband purpose and for the genera­tion of the triple-band operation. The radiation patterns were measured in an isolated anechoic chamber by using two antennas which are a double ridged horn antenna- model AH-118 (1-18) GHz and the fabricated antenna. Figure 9 and 10 show, respectively, the normalized co-polarization and cross polarization radiation patterns in both orthogonal planes at three different frequencies from the operat­ing ranges: 1.99 GHz, 6.2 GHz, and 10.33 GHz. (a) (b) Figure 9: Measured normalized co-polarization radia­tion patterns at three frequencies, (a) xz-plane, (b) yz-plane. We can see that the co-polarization radiation pat­terns are practically omnidirectional in xz-plane (H-plane) and bidirectional shape in yz-plane (E-plane). It is noted that the measured radiation patterns exhibit expected stable patterns along the working bands. Besides, with augmenting the frequency, the number and the impact of side-lobes and nulls strengthen and A. Chaabane et al.; Informacije Midem, Vol. 50, No. 4(2020), 275 – 283 (a) conserve their omnidirectional features over the three working bands. Figure 11 depicts the simulated real­ized gain and efficiency. Except at the notched bands, a reasonable and an acceptable increasing realized gain is obtained over the operating ranges; the simulated realized gain is better than the one calculated in [20]. (b) proposed antenna. Within the two notched ranges, the lowest values of the realized gain are located at around the two reso­nating frequencies of the split-shaped circular ring for -4.09dBi and -1.35dBi which at once validates the utility of the inserted split-shaped circular ring to pro­duce the multiband function. As well, except at the two rejected bands, the simulated antenna efficiency is steady which is almost over than 80% along the work-the measured antenna tends to provide bidirectional ing ranges; with two lowest values located of the two patterns in the xz-plane. Besides, analogous to the ob-resonance frequencies of the etched split-shaped circu­tained results in [18-19], the cross-polarized patterns Table 2: Proposed antenna’s comparative analysis with other recent reported antennas. References Substrates Sizes (mm3) Bandwidths [22] Rogers 4003 40 × 50× 0.812 2.39–2.59 GHz (8.03%), 3.1–3.57 GHz (14.09%), 5.45– 6.5 GHz (17.57%) [23] Rogers 6010LM 50 × 50 ×2.54 0.7–0.96 GHz (31.32%), 1.18–3 GHz (87.08%) [24] FR4 61× 41× 1.6 1.379–1.564 GHz (12.57%), 2.947–3.075 GHz (4.25%) [25] FR4 125×108×1.6 1.53–1.97 GHz (25.14%), 2.22–2.56 GHz (14.23%), 3.31–4 GHz (18.88%) [26] FR4 60×60×1.56 2.31–2.89 GHz (22.3%), 4.15–4.27 GHz (2.85%), 4.64– 4.74 GHz (2.13%) [27] FR4 40 × 40 × 1.6 2.88–3.92 GHz (30.59%), 5.26–6.28 GHz (17.68%) [28] FR4 50 × 50 × 1.6 2.56–3.63 GHz (34.57%), 9.35–12.25 GHz (26.85%) [29] FR4 60 ×60 ×1 2.51–3.72 GHz (38.84%), 4.83–6.37 GHz (27.5%) [30] FR4 60 ×60 ×1.59 1.96–2.33 GHz (17.25%), 3.74–10.4 GHz (94.20%) [31] FR4 50 ×35 ×1.6 2.35–3.22 GHz (34.52%), 4.78–5.79 GHz (18.39%) Fabricated FR4 23.5×31×1.5 1.57–2.33 GHz (38.97%), 5.84–6.41 GHz (9.31%), 7.93– 10.88 GHz (31.37%). A. Chaabane et al.; Informacije Midem, Vol. 50, No. 4(2020), 275 – 283 lar ring of about 15.71% and 22.22%. It is revealed that the obtained efficiency surpass the one attained by some recently published papers like in [21]. Addition­ally, in order to show the importance of the proposed antenna, a comparative review has been established in Table 2. It is clear that the designed antenna has a small size compared to some recently published structures. 3 Conclusion A simple compact printed CPW-fed triple-band an­tenna has been successfully designed, fabricated, and experimentally assessed for the integration with mul­tiple wireless communication systems. The multiband function has been introduced by etching of a split-shaped circular ring on the radiating patch and explor­ing its effect on the initial designed UWB antenna. The advantage of the introduced concept is the simplic­ity of the transition from the UWB to multiband func­tion. The measured working impedance bandwidths extends from 1.57-2.33 GHz (38.97%), 5.84-6.41 GHz (9.31%), and 7.93-10.88 GHz (31.37%), covering the spectrum reserved to GSM1800, GSM1900, UMTS, GPS, GLONASS, DCS, PCS, TD-SCDMA, WCDMA, CDMA2000, DSRC, ITU8, and X band radar. The proposed antenna reveals consistent measured radiation patterns with ac­ceptable realized gain and high efficiency over the op­erating bands. The simple geometry and the compact structure of the designed antenna meets the require­ment of many wireless communication systems. 4 Acknowledgments This work was supported by the Directorate General for Scientific Research and Technological Development (DG-RSDT) of Algeria. The authors would like to thank Pr. Tayeb A. Denidni, INRS Canada, for his kind help for the antenna radiation patterns measurements. 5 Conflict of interest The authors declare no conflict of interest. 6 References 1. F. B. Zarrabi, A. M. Shire, M. Rahimi, N. P. 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Arrived: 16. 09. 2020 Accepted: 29. 12. 2020 Original scientific paper https://doi.org/10.33180/InfMIDEM2020.406 Performance Analysis of Dispersion Compensation Schemes with Delay Line Filter Kasthuri Palanichamy, Prakash Poornachari, Ganesh Madhan M Anna University, MIT Campus, Department of Electronics Engineering, Chennai, Tamilnadu, India Abstract: Optical communication is an effective system to achieve the high-speed data transmission for long distance. The main factor that affects the optical communication is dispersion. Dispersion leads to reduction of the system performance and Q-factor. Dispersion can be compensated using various techniques. Major techniques are compensation using Dispersion Compensating Fiber (DCF), Fiber grating technique, and Delay Line Filter (DLF). Analysis has been performed on the Bit Error Rate (BER) and Quality Factor (Q-Factor) of various schemes based on Eye Opening Penalty (EOP) with BER analyzer for dispersion compensation. It has been concluded that Impulse Invariant Response (IIR) based DLF at average results in 50% of better compensation when compared Fiber Bragg Grating and DCF based compensation techniques. The power of the received signal when transmitted at 0 dBm for 120 kms is –12.325 dBm which is the optimum power in which the signal can be received without distortion. Keywords: Delay line Filter, BER, Q factor, Dispersion Compensation Analiza učinkovitosti disperzijskih kompenzacijskih načrtov z linijskim kasnilnim sitom Izvleček: Optične komunikacije so učinkovit sistem za hiter prenos podatkov na dolge razdalje. Glavni dejavnik, ki vpliva na optične komunikacije je razpršitev (disperzija). Razpršitev vodi v zmanjšanje sistemskih zmogljivosti in faktorja Q. Razpršitev je mogoče kompenzirati z različnimi tehnikami. Glavne kompenzacijske tehnike so kompenzacija z uporabo vlaken za kompenzacijo disperzije, tehnike vlakenske periodične strukture in linijskim kasnilnim sitom. Opravljena je bila analiza pogostosti bitne napake in faktorja kvalitete (faktor Q) različnih načrtov kompenzacije disperzije, ki temelji na odprtosti očesnega diagrama z analizatorjem pogostosti bitnih napak. Ugotovljeno je bilo, da linijsko kasnilno sito z neskončnim impulznim odzivom v povprečju doseže 50% boljšo kompenzacijo v primerjavi s kompenzacijskima tehnikama vlakenske Braggove periodične strukture in vlakna za kompenzacijo disperzije. Pri oddajni moči 0 dBm je moč sprejetega signala po 120 kilometrih –12.325 dBm , kar je optimalna moč pri kateri je mogoče signal sprejeti brez popačenja. Ključne besede: linijsko kasnilno sito, BER, factor Q, kompenzacija razpršitve * Corresponding Author’s e-mail: prakashp79@gmail.com, prakashp_mit@annauniv.edu 1 Introduction formation passes through the optical fiber experiences Optical communication is the methodology that al-dispersion and attenuation which is the main factor lows light through an optical fiber for transmitting in-that affects the communication. Mostly the lightwave formation from one place to another. The three basic system uses optical fibers as the communication chan-components for optical transmission systems are fiber nel. The reason is that silica fiber can transmit light with medium, light source and light detector. The commu-very few losses. Even then, optical power reduces to nication channel must allow the optical signal to reach only 1% after 100 km. Hence, fiber losses are always the receiver without any distortion by the channel. In-an important design issue. This can be reduced by the K.Palanichamy et al.; Informacije Midem, Vol. 50, No. 4(2020), 285 – 292 use of a repeater or amplifier. Fiber dispersion is also an important issue which should be taken care during the fiber designing. The transmitted signal will be degrad­ed if optical pulses spread significantly outside their allocated bit slot. It becomes difficult to recover the original signal with high accuracy [1]. The optical sig­nal in the fiber experiences various non-linear effects like Raman scattering and Kerr Effect. They both limit the received signal in fibers. Also, the signal experi­ences various dispersion like chromatic dispersion and polarization mode dispersion, which makes fibers not practical for long distance communication [2]. Recent­ly, research in dispersion compensation of fibers have gained momentum with increase in demand for high bandwidth communication systems. With increase in need for high capacity and high speed communica­tion systems for future, dispersion compensation tech­niques for long distance fiber communication is now necessary [3]. Fiber-Optic dispersion compensation on optical transmission systems is studied using vari­ous techniques. In order to improve the overall system efficiency and to reduce the dispersion which leads to transmission degradation, several dispersion compen­sation techniques were proposed [4]. The techniques which act as the solution for dispersion compensation is broadly classified as: Dispersion Compensation Fib­ers (DCFs), High-Order Mode (HOM) Fiber, Fiber Bragg Gratings (FBG), and delay line filter. Li.,L. et.al discussed about the use of ring resonators acting as passband microwave photonic filter in order to perform disper­sion compensation [5]. Poornachari, P. et.al discussed about using Side Couple Integrated Space Sequence of Resonator (SCISSOR) acting as delay line based All Pass Filter for dispersion compensation [6]. Also, Disper­sion is compensated at the receiver end using Digital Signal Processing techniques. K. Zhong et.al discusses the application of signal processing at receiver end for dispersion compensation in short Optical communi­cations [7]. Kakkar, A et.al discusses the application of digital signal processing at both receiver end and at transmitter side for dispersion compensation [8]. Dis­persion is also compensated in electronics means by pre-processing the signal and compensating it for dis­persion at the transmitter end by substituting the sig­nal using 2n bit look up table [9]. Also  M. A. Ilgaz, et al., discussed a flexible approach to combating chromatic dispersion in a centralized 5G network which will be fo­cused in the future work of this paper [10]. In this paper, we have designed a novel DLF IIR filter and the performance of IIR based DLF for dispersion compensation is compared with Dispersion Compen­sation Fiber and Fiber Bragg grating. The above men­tioned techniques under goes various disadvantages like manufacturing cost, complex design, reduced flex­ibility, mainly length of the fiber. The distance of 120 kms can be covered using DLF IIR filter. Also it increases the speed of execution. The computational complexity is greatly reduced by this method and improves the performance of the interlever. The main advantage of this method is that it can be used to design the band pass filter without specifying the transition regions. 2 Dispersion compensation techniques In an optical medium Dispersion Compensating Fiber (DCF) provides a large negative value of chromatic dis­persion at the operating wavelength. Depending on the placement location of dispersion compensation fiber it is classified as pre, post and mix compensation. Dispersion compensation fiber is used to achieve the perfect compensation. The condition for perfect dis­persion compensation is [11]: D =LD (1) SMF DCF DCF Where LSMF the length of the Single Mode Fiber (SMF) in the link, LDCF -the length of the DCF is used to obtain dispersion compensation, while DSMF and DDCF gives the dispersion values for the single mode fiber and dispersion compensation fiber respectively. The pulse spread due to chromatic dispersion is given [11] in the equation (2). tLD()... (2) .= Where, t is Pulse Spread (ps); L defines Fiber Length (km); D(.) denotes Chromatic Dispersion factor (ps/ nm-km); . represents Operating Wavelength (nm); .. is Spectral Width of the transmitter output (nm) 2.1 Pre-compensation Technique In pre compensation technique the single mode fiber is placed after the dispersion compensation fiber. The dispersion compensation fiber experiences the posi­tive dispersion and while single mode fiber which al­ready has negative dispersion when they connect to­gether the dispersion gets compensated. So that the data in the receiver experience no distortion [12-15]. 2.2 Post-compensation Technique In post compensation technique the single mode fiber is placed before the dispersion compensation fiber. The single mode fiber produces the negative dispersion whereas dispersion compensation fiber which already has positive dispersion when connected together gets compensated and reaches the receiver without any dis­tortion. The post compensation technique consists of a K.Palanichamy et al.; Informacije Midem, Vol. 50, No. 4(2020), 285 – 292 receiver with pin diode and BER analyzer, and transmit­ter with laser source. The transmission channel has sin­gle mode fiber followed by DCF. In the post compen­sation technique the dispersion is compensated at the receiver end [16-17]. 2.3 Mix compensation Technique Mix compensation is a technique in which dispersion is compensated in both transmitter and receiver side where the dispersion compensation fiber is placed be­fore and after the single mode fiber which results in increases performance compared with other compen­sation technique [20-22]. Figure 1 shows the block dia­gram of Mix Compensation technique as pre and post compensation can be achieved by modifying mix com­pensation. By considering the various types of nonlin­ear effects based on optical transmission, the Erbium Doped Fiber Amplifier (EDFA) system is utilized. Ac­cording to the placement of DCF and SMF, dispersion compensation using compensation fiber is analyzed. 2.4 Fiber Bragg Grating A FBG is one of the methods of distributed Bragg re­flector to reflect back the particular wavelength of light and transmit remaining. This is achieved by creating periodic variation in the refractive index of the fiber core [23]. Figure 1: Block Diagram of Mix Compensation Tech­nique At each periodic refraction there is change in a small amount of reflected light. At a particular wavelength all the reflected light signals combine uniformly to one large reflection. This is referred to as the Bragg condi­tion, and the wavelength at which the reflection oc­curs is known as the Bragg wavelength. The non-phase matched wavelengths are transparent fiber Bragg grat­ing The grating equation is [24], . ( sinsin .- sin . )=n . (3) in di Where .in and .di are incident and diffracted angles. The imprinted grating [24] can be represented as .. 2 . z . nz = n + n 1 cos (4) () .+ .. c .. where, nc is refractive index of core, . n is photo induced change in index The reflection wavelength is given as . = 2.n and Braggeff the peak reflectivity for the grating length of L and the coupling coefficient x is given by, R =2 () (5) maxtanh xL The full bandwidth in which the reflectivity [24] can have is . 21 Bragg 2 22 .=. .() xL +. . (6) .. . nL eff 2.5 Delay Line Filter Chromatic dispersion can be compensated using the optical filter in fiber communication. Optical commu­nication is a way of transmitting the information by modulating the light signal with the information signal. The mathematical operation on a sampled, discrete-time signal to reduce or enhance certain conditions of that signal is performed in the digital filter. Two types of digital filters are recursive filter and non-recursive filters [25]. Delay line recursive filter is analyzed here. These filters are realized in the optical domain which comprises unit delay, weight element and adders. The input field is splitted into M+1 different elements in turn will be delayed separately by multiples of unit delays. Filter order can be determined by the highest delay. The multiple copies of the input field are recom­bined in the final stage. The input field, () jt (7) Ei =Eo t e . The output field composite of jT . jT 12 E = bE + be E +be . (8) o oi 1 i 2 Thus, the filter transfer function will be . Ni j . jT o He ( ) =be . (9) i = 0 0 ZejT. Setting = , transform of the filter will be i HZ =bZ- (10) ().N i i = 0 K.Palanichamy et al.; Informacije Midem, Vol. 50, No. 4(2020), 285 – 292 The DLF with the source of 1550nm is proposed in Fig­ure 2 [26]. Figure 2: Optical link for system simulation 3 Implementation of DCF Various Dispersion Compensation Modules (DCM) are implemented using Optisystem. Optisystem is a rapidly evolving software design tool that enables the user to design, test, and simulate the optical communication systems comprised of all optical components and also helps us to visualize the analysis for the optical link. Im­plementing realistic modeling of fiber-optic communi­cation systems is more complex in which optisystem can offer a system level simulator for the design for the transmitter, channel, amplifier, and receiver models of the optical system. Initially compensation with disper­sion compensation fiber is performed. Fiber-Optic dis­persion compensation on optical transmission systems is studied using various techniques. In order to improve the overall system efficiency and to reduce the disper­sion which leads to transmission degradation, several dispersion compensation techniques were proposed. Depending upon the placement of the dispersion compensation fiber the dispersion can be compensat­ed pre, post and mix compensation method. The mix compensation portion is blocked in the layout. Trans­mitter system consists of the laser source, Non-Return­to-Zero (NRZ) waveform and Mach Zehnder modulator. NRZ waveform is generated from the binary values of Pseudo Random Binary Sequence (PRBS) at length of 128 bits, is provided to the Mach Zehnder modulator at a data rate of 10 Gbps. The communication system can be divided into three parts they are transmitter, re­ceiver and channel. Figure 3: Simulation Layout of mix-Compensation Technique The channel is the main area for the occurrence of the dispersion hence the compensation is mainly per­formed in the communication channel. As like the pre compensation technique the post compensation per­forms the same operation where the placement of the dispersion compensation fiber is after the SMF. Figure 3 shows the simulation layout of the mix com­pensation technique. The mix compensation technique can be used for long distance communication. Since the dispersion is compensated in both the transmitter and the receiver side. This technique shows better per­formance compared to the pre and post compensation technique. Simulation layout shown in Figure 4 which clearly gives the arrangement of FBG. The simulation of the DLF using IIR filter is given in Fig­ure 5. Transmitter system consist of the laser source, NRZ waveform is generated from the binary values of PRBS at length of 128 bits, is provided to the Mach Zehnder modulator at a data rate of 10 Gbps. Figure 4: Simulation Layout of Fiber Bragg Grating In which the BER and Q-factor can be analyzed us­ing a BER analyzer. In this technique the dispersion is compensated using the delay line filter. The post com­pensation technique used in the DLF dispersion com­pensation, where the placement of delay line filters is followed by the single mode fiber. The simulation of the DLF using IIR filter is given in Figure 5 from which the BER and Q-factor can be analyzed using the BER analyzer. In this technique the dispersion is com­pensated using the DLF. The post compensation tech­nique used in the DLF dispersion compensation, where the placement of DLF is followed by the single mode fiber. Figure 5: Simulation Layout of Delay line IIR Filter K.Palanichamy et al.; Informacije Midem, Vol. 50, No. 4(2020), 285 – 292 the result that the delay line IIR filter gives better per­ 4 Simulation results formance. The simulations of each technique are shown in this Table 2: Comparison of Q-Factor and Minimum BER session. 0 dBm power is used for the transmission link. values The results are analyzed at the receiver part which consist of a photo detector, electrical filter and BER analyzer where the eye pattern is analyzed. The inputs given to the BER analyzer are from PBRS at the length of 128 bits, NRZ and the output from low pass Bessel filter. Table 1 gives the BER pattern comparison of pre-compensation, post-compensation and mix-compen­sation. The Q-Factor and minimum BER for the com­pensation techniques are analyzed using BER analyzer. The Eye pattern for the simulation of pre, post and mix compensation techniques are given in Table 1. Table 2 shows the performance comparison of Q-factor Table 3: Comparison of received power with various dispersion compensation techniques. Factors Analyzed Q- Factor Min BER Pre Compensation 4.89907 4.71181 x 10^-7 Post Compensation 4.96922 3.26974 x 10^-7 Mix Compensation 5.7533 4.23322 x 10^-9 FBG 6.16313 3.56 x 10^-10 Delay Line IIR Filter 11.08 6.8 x 10^-29 and Minimum BER. BER patterns are also analyzed us­ing eye opening penalty which is shown in Table 1. Table 1: Comparison of BER pattern for Pre, Post, Mix compensation techniques Parameter Q-factor Minimum BER Pre Compensation Post Compensation Mix Compensation It is found that mix compensation gives better per­formance compared to the pre compensation and post compensation technique [26]. Also, the method of pre-compensation would not be suitable for sys­tems that have variable distortion like polarization mode dispersion. Post compensation would be better equipped to handle variable sources of dispersion. But, having compensation at transmitter end and receiver end would result in better performance as seen above, but increase in performance also increases the cost of deployment of the system. Delay line based post com­pensation gives better performance than mixed form of compensation without the expense of increasing the cost of the system. From the comparison Table 2 the Q-factor and Min BER are also analyzed for various dispersion compensation techniques. It is clear form Table 3. shows the received power when a NRZ signal is transmitted in a fiber of length 120 kms. Power pen­alty for Delay line IIR filter is similar to other compensa­tion techniques. However, delay line IIR filter results in a much better BER and Q-Factor when compared with other compensation techniques. Though DCF based mixed compensation technique produces better re­sults when related with power, mix compensation re­quires use of two identical compensation components at the transmitter and receiver end which increases the complexity of the system. From the values of BER and Q-Factor, it can be seen that delay line IIR filter based dispersion compensation produces better results with Compensation Techniques Received Power in dBm DCF – Pre Compensation –13.120 DCF – Post Compensation –12.109 DCF – Mix Compensation –10.125 FBG – 17.235 Delay Line IIR Filter –12.253 Figure 6: Received Power using various dispersion compensation techniques. K.Palanichamy et al.; Informacije Midem, Vol. 50, No. 4(2020), 285 – 292 post compensation, when mixed compensation is used it can produce better results. But, that has been avoid­ed as mix compensation technique can increase the complexity of the system. Figure 6 shows the received power when different compensation techniques are used. Table 4: Comparison of BER pattern for DLF using FBG and DLF IIR Filter. 5 Conclusions A communication channel with laser source, NRZ waveform which is generated from the binary values of PRBS at length of 128 bits, is provided to the Mach Zehnder modulator with the single-mode fiber at the data rate of 10 Gbps for 120 km fiber is investigated. Ini­tially, communication using single-mode fiber without any compensation schemes are analyzed, which shows Dispersion Compensation Q-factor Minimum BER Fiber BraggGrating Delay Line IIR Filter Table 5: Distance of Transmission vs Eye Height in DLF IIR Filter Distance Eye-Height 20 km 0.003785 40 km 0.001431 80 km 0.000205 120 km 2.9576 x 10-5 160 km 3.735 x 10-6 The eye pattern for the fiber Bragg grating and delay line IIR filter is explained in the Table 3. Table 5. Com­pares the distance of transmission with eye height in DLF IIR Filter. Performance of DLF IIR filter has been demonstrated in Figure 7. when a signal travels for the longer distance it leads to the pulse spreading that results in dispersion. Dis­persion compensation simulation is performed using various schemes and the performance has been com­pared. The most commonly used dispersion compen­sation techniques are pre, post and mix compensation. The performance comparison of these techniques is given in Table 2. Since there is more possibility of occur­rence of dispersion in the receiver end, post compen­sation technique offers Q-factor of 4.96922 that gives better result compared with the pre-compensation technique. Mix compensation offers Q-factor of 5.7533 which is 13.5% greater than post compensation due to the compensation of the dispersion on both trans­mitter and receiver side of the optical link. The BER of the pre compensation is 4.71181 x 10-7 which results of greater dispersion compensation, on comparing with the other compensation techniques. Whereas the mix compensation scheme offers less bit error rate of 4.23322 x 10-9 compared with the other two dispersion compensation schemes for the same optical link. Fiber Bragg grating also shows the effec­tive result in the dispersion compensation compared with dispersion compensation using dispersion com­pensating fiber are next investigated. Ideal dispersion compensator FBG is used to provide effective Q-factor of 6.16313 which is 6.65% greater performance than Mix compensation and also offers a bit error rate of about 3.56 x 10-10. This is because of low insertion loss. Finally, the delay line filters in dispersion compensa­tion are also discussed. The IIR filter delay line is used to achieve better performance than other compensa­tion techniques. The effective result can be achieved by the possible utilization of the feedback loops. On comparing the performance of the delay line filter with the other techniques, it is found that the Q-factor for delay line IIR filter of 11.08 which is 47.18% greater than Fiber Bragg grating and provides a minimum BER of 6.8 x 10^-29. Also, the IIR filter gives 50.7% higher Q-factor than Mix compensation schemes. So that the perfor­mance of delay line filters is efficient than other dis­persion compensation schemes. In this work, a novel DLF IIR filter is designed, and performance of the filter is compared with other compensation techniques. The cost of implementing IIR filters to compensate disper­sion is minimal compared with pre, post and mix com­ K.Palanichamy et al.; Informacije Midem, Vol. 50, No. 4(2020), 285 – 292 pensation techniques used in optical systems because the components used to design the dispersion com­pensation fibers are expensive. 6 Conflict of Interest The authors declare no conflict of interest. The founding sponsors had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, and in the deci­sion to publish the results 7 References 1. Zhang Hongbin, Qiu Kun.: Emulation of charac­teristics of optical fiber transmission for a 10Gb/s single channel situation. Acta photonicasinica. 30(6)715-720. (2001). http://www.photon.ac.cn/ EN/Y2001/V30/I6/715 2. M. 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Arrived: 22. 09. 2020 Accepted: 29. 12. 2020 Najvišje nagrade v slovenski znanosti v letu 2020 Electronic Components and Materials Vol. 50, No. 4(2020), 293 – 293 Najvišje nagrade v slovenski znanosti v letu 2020 Odbor za nagrade, ki mu predseduje prof. dr. Janez Plavec, je konec novembra v Predsedniški palači v Lju­bljani podelil najvišja priznanja za dosežke na znanst­veno raziskovalnem področju. Slavnostni govornik na prireditvi je bil predsednik republike Borut Pahor. Zoisovo nagrado za življenjsko delo sta prejela prof. dr. Stanislav Radovan Pejovnik in prof. dr. Tamara Lah Turnšek. Puchovo nagrado za življenjsko delo je pre­jel prof. dr. Janez Trontelj, dolgoletni član društva MI­DEM. Med letošnjimi dobitniki štirih Zoisovih nagrad za vrhunske dosežke na posameznih področjih je tudi predsednica društva MIDEM prof. dr. Barbara Malič, ki je prejela Zoisovo nagrado za vrhunske znanst­vene dosežke na področju raziskav elektrokaloričnih keramičnih materialov. Podelitev Zoisovih in Puhovih nagrad in priznanj si lahko ogledate na povezavi: https://www.rtvslo.si/4d/arhiv/174736192?s=tv Iskrene čestitke vsem prejemnikom nagrad in priznanj, še posebej pa dolgoletnima članoma našega društva prof. dr. Janezu Trontlju in prof. dr. Barbari Malič. Prof. dr. Marko Topič Glavni in odgovorni urednik Boards of MIDEM Society | Organi društva MIDEM MIDEM Executive Board | Izvršilni odbor MIDEM President of the MIDEM Society | Predsednik društva MIDEM prof. dr. Barbara Malič, univ. dipl. inž. kem., Institut Jožef Stefan, Ljubljana, Slovenija Vice-presidents | Podpredsednika prof. dr. Janez Krč, univ. dipl. inž. el., UL - Fakulteta za elektrotehniko, Ljubljana, Slovenija dr. Iztok Šorli, univ. dipl. inž. fiz., Mikroiks d.o.o., Ljubljana, Slovenija Secretary | Tajnik Olga Zakrajšek, UL - Fakulteta za elektrotehniko, Ljubljana, Slovenija MIDEM Executive Board Members | Člani izvršilnega odbora MIDEM prof. dr. Slavko Bernik, univ.dipl.kem., Inštitut Jožef Stefan, Slovenija izr. prof. dr. Miha Čekada, univ.dipl.inž.fiz., Institut Jožef Stefan, Ljubljana, Slovenija prof. ddr. Denis Đonlagić, univ.dipl.inž.el., UM - Fakulteta za elektrotehniko in računalništvo, Maribor, Slovenija prof. dr. Leszek J. Golonka, Technical University, Wroclaw, Poljska prof. dr. Vera Gradišnik, univ.dipl.inž.el., Tehnički fakultet Sveučilišta u Rijeci, Rijeka, Hrvatska mag. Leopold Knez, univ.dipl.inž.el., Iskra d.d., Ljubljana, Slovenija mag. Mitja Koprivšek, univ.dipl.ing.el., ETI Elektroelement d.d., Izlake, Slovenija doc. dr. Gregor Primc, univ. dipl. inž. el., Institut Jožef Stefan, Ljubljana, Slovenija prof. dr. Janez Trontelj, univ.dipl.inž.el., UL - Fakulteta za elektrotehniko, Ljubljana, Slovenija doc. dr. Hana Uršič Nemevšek, univ. dipl. inž. fiz., Inštitut Jožef Stefan, Ljubljana, Slovenija znan. svet. dr. Danilo Vrtačnik, univ. dipl. inž. el. Fakulteta za elektrotehniko, Ljubljana, Slovenija Supervisory Board | Nadzorni odbor prof. dr. Franc Smole, univ. dipl. inž. el., Fakulteta za elektrotehniko, Ljubljana, Ljubljana, Slovenija prof. dr. Drago Strle, univ. dipl. inž. el., UL - Fakulteta za elektrotehniko, Ljubljana, Slovenija Igor Pompe, univ. dipl. inž. el., upokojenec Court of honour | Častno razsodišče Darko Belavič, univ. dipl. inž. el., Inštitut Jožef Stefan, Ljubljana, Slovenija dr. Miloš Komac, univ. dipl. inž. kem. teh., upokojenec doc. dr. Hana Uršič Nemevšek, univ. dipl. inž. fiz., Inštitut Jožef Stefan, Ljubljana, Slovenija Informacije MIDEM Journal of Microelectronics, Electronic Components and Materials ISSN 0352-9045 Publisher / Založnik: MIDEM Society / Društvo MIDEM Society for Microelectronics, Electronic Components and Materials, Ljubljana, Slovenia Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale, Ljubljana, Slovenija www.midem-drustvo.si