EXPERIMENTAL INVESTIGATION OF Si-SiO2 INTERFACE TRAPS USING EQUILIBRIUM VOLTAGE STEP2 TECHNIQUE
M.S. Benlatreche1, F. Rahmoune1, O.Toumiat2
1University M'hamed Bougara of Boumerdes, Faculty of science, Physics department. Algeria 2University of Constantine, Faculty of science, Physics department. Algeria
Key words: Si-SiO2 interface traps; Equilibrium Voltage Step technique; traps.
Abstract: The concentration profile of Si-SiO2 interface traps in metal-oxide-semiconductor transistors has been studied using an equilibrium voltage step techniques. The Equilibrium Voltage Step (EVS), usually applied to extract the slow states profile in 3 dimensions, was used to deduce the in-depth profile of the slow states of the Si-SiO2 interface. The profile of the slow states decreased between 7Ä and 17Ä awing.
Eksperimentalne raziskave pasti na mejni plasti Si-SiO2 z uporabo napetostne tehnike EVS
Kjučne besede: pasti na meji Si-SiO2 , napetostna tehnika EVS, pasti
Izvleček: V prispevku preučujemo koncentracijski profil pasti na meji Si-SiO2 v MOS tranzistorju z uporabo napetostne tehnike EVS. Tehniko EVS, ki jo običajno uporabimo za študij počasnih energijskih stanj v treh dimenzijah, smo tokrat uporabili za določanje globinskega profila le-teh na meji Si-SiO2. Ugotovili smo, da koncentracija počasnih stanj močno pade na razdalji med 7Ä in 17Ä od meje.
1. Introduction
Because of their limitation on the scaling of SiO2 based metal-oxide semiconductors (MOS), the understanding of Si-SiO2 interface traps is necessary. Many methods and theoretical models have been proposed to study Si-SiO2 interface traps. The "1/f" noise method was the first technique, which supposed a distribution of traps in the direction of the oxide /1-2/. Recently, different methods have been proposed for the study of slow states /3-5/. A capture time constant distribution of traps has been confirmed by Bauza et al /6/, using the in-depth approach of charge pumping. This technique consists of measuring the charge pumping current as a function of frequency evaluated at the maximum of the Elliot curves. The Equilibrium Voltage Step (EVS) technique, developed by Tanner et al /5/, has been used to simultaneously extract the trap response time, density and energy in the silicon band gap of traps located near the Si-SiO2 interface. The technique is simple and direct and consists of scanning the gate voltage of a MOS capacitor with different delay times and then measuring the resulting current transients. In this article, the trap profile, assuming only pure tunneling for capture, using data obtained by the EVS techniques.
2. Extraction of Si-SiCg interface trap profile using the equilibrium voltage step technique
The EVS technique has been mainly used to characterize slow traps in the Si-SiO2 interface/4/. Then, it was extended to extract slow trap profiles in MOS capacitors with plasma damaged oxides /10/ and with NO and N2 O nitride oxides grown on Si and SiC substrates /11/. It has been later validated by Spillane et al. /12/.
This technique is based on the extraction of the current-voltage-time information in MOS capacitors /4/. It consists of scanning the gate voltage in a staircase manner and then measuring the resulting current transients after a delay time which is composed of the measurement time of the instrument, t0 and a time td which is adjusted by the operator. The transient current measured at time t0+ td corresponds to the trap density with that response time. After scanning the gate voltage with different delay times, it is possible to extract directly the trap density as a function of response time at each energy position in the silicon band gap.
To extract the slow trap profile, the measured transient substrate current shown in Fig. 1 is divided by (q x A xAE), where q is the absolute electronic charge, A the area of the gate and AE the change in the surface Fermi level resulting from the gate voltage step.
S
I
Holdtime^Os Delay tu^= 10 > Step voltage = 50 mV
-2
Fig 1:
-1 0 1 Gate voltage (V)
Transient substrate current due to the gate v oltage step at different delay times (p-type substrate MOS capacitor).
If we consider a set of slow traps at the Fermi level at equilibrium, then the capture time constant is equal to the emission time constant Tc=Te such that :
1
T =-
«CTV,^	(1)
where s is the capture cross section, n the carrier concentration at the surface and Vth the carrier thermal velocity. If we suppose a uniform distribution of traps into the oxide, then according to the Heiman-Wrafield tunneling model /9/, the capture cross section at distance x from the interface can be written as:
a(;c)=CT(0)exp(^)	(2)
Then, solving for the tunneling depth x we find /12/:
where Nc is the effective density of states in the conduction band, (Ec -EF) the Fermi energy level relative to the conduction band and KT is the thermal energy.
We assume that traps are distributed through the oxide both in energy and space with density Nt. By stepping the gate voltage, the Fermi energy changes by an amount DE If the device is in equilibrium before the step, then after the voltage step traps up to depth x will have changed charge (through emission or capture processes). Thus, the number of these states per unit area can be written as :
Nix)^xNAE	(4)
Introducing the expression of the tunneling depth x in Equation (2) and solving for Nt we get:
' XAqAE	(5)
where Isub(t) is the transient current measured at the substrate.
In this part, a MOS p-type capacitor with a thick oxide is used. When the surface of the semiconductor is swept from
accumulation to inversion using a staircase gate signal with increment Vs,ep= 50 mV, and a variable delay time from 10ms to 2s, we obtain positive transient current peaks attributed to emission of holes to the substrate, this peak decreases as the delay time increases, as shown in Fig.3. Applying the model of Tanner et al. /4/, which consists of dividing the measured current density by (q x DE), where q is the absolute electronic charge and DE the energy swept by the surface Fermi level, one obtains the 3D trap profile illustrated in Fig.2. This figure is attributed to the slow trap profile having response times from 70 ms to 2060 ms (since the measuring time of the instrument is 60ms). One can see the existence of a peak at 0.25 eV above the mid-gap which decreases as the response time is increased. This device has a Dit value of 1012 ev-1cm-2 measured using a conventional charge pumping technique. By applying now the theory of charge tunneling through energy barriers, one obtains the in-depth profile of traps, as shown in Fig.3.

E-^ (eV)
Fig 2: 3D slow trap profile of a p-type substrate MOS capacitor measured with delay times between 10 ms and 2s.
3. Resultants and discussion
The EVS technique allows the exploration of trap concentration into the oxide near the Si-SiO2 interface, between 7 and 17Ä, which corresponds to slow traps. Nevertheless, the charge pumping technique not only explores these types of traps, represented by the plateau of the profile, but probes also the fast states, which correspond to the exponential part of the profile /14/. The difference between the two techniques is that in charge pumping we measure a constant value of trap concentration for tunneling depth greater than 5 to 6Ä, while with EVS we measure a decreasing value of the trap concentration between 7 and 17 Ä into the oxide. Another main difference concerns the energetic distribution of traps probed by each technique. The CP interface states located up to ±0.42eV around the mid-gap of silicon, depending on measuring conditions /13-14/, contribute to the recombination process and hence to the charge pumping current. However, in the EVS technique only slow traps located at specific energy
Fig. 3: Tunneling depth distribution obtained from the measured 3D profile of Fig. 2.
levels in the silicon band-gap contribute to the measured transient current.
5. References
/1/ A. L. McWhorter, Semiconductor surface physics, Pennsylvania university press, Philadelphia, 1957 , p.293.
/2/ S. Christenson, I. Lundström and C. Svensson, Solid-St. Electron. 11,797 (1968).
/3/ R. E. Paulsen and M. H. White, IEEE Trans. Electron Devices ED-41, 1213(1994).
/4/ P. Tanner, S. Dimitrijev and H. B. Harrisson, Electron Letters 31, 1880 (1995).
/5/ S. Dimitrijev, P. Tanner, Z.-Q Yao and H. B. Harrisson, Microelectronics Reliability 37, 1143(1997).
/6/ D. Bauza and Y. Maneglia, IEEE Trans. Electron Devices, ED-44, 2262 (1997).
/8/ R. A. Wachnik and J. R. Lowney, Solid-St. Electron. 29,447 (1986).
/9/ P. Tanner, S. Dimitrijev, Y-T. Yeow and H. B. Harrison, IEEE Electron Device Letters 17, 515 (1996).
/10/ S. Dimitrijev, P Tanner, and H. B. Harrisson, Microelectronics Reliability 39, 441 (1999).
/11/ M. P. Spillane, S. Taylor and M. J. Uren, Microelectronic Engineering 48, 155(1999).
/12/ F. Hofmann and W. Hansch, J. Appl. Phys. 66, 3092, 1989.
/13/ F. Rahmoune, Contribution ä l'etude des defauts de l'interface Silicium/Isolant dans les transistors MOS avances. Ph.D Thesis, INPG , Grenoble, 2004.
4. Conclusion
The EVS technique has proven to be a simple and direct tool to simultaneously measure both the energy and response time distribution of traps located in the oxide near the Si-SiO2 interface by scanning the gate voltage with different delay times. By applying the theory of carrier tunneling through energy barriers, the trap response time has been related to the tunneling depths into the oxide. The EVS technique only the slow traps located near the Si-SiO2 interface and at specific energy levels in the silicon mid-gap are probed. This profile shows a decreasing trap concentration between 7 and 17Ä from the Si-SiO2 interface.
M.S. Benlatreche1, F. Rahmoune1, O.Toumiat2 bmshakim35@umbb.dz; hakim2535@gmail.com 1University M'hamed Bougara of Boumerdes, Faculty of science, Physics department. Algeria 2University of Constantine, Faculty of science, Physics department. Algeria
Prispelo: 07.01.2011
Sprejeto: 23.08.2011