THERMAL BOUNDARY CONDITIONS IN SMART POWER DEVICES Martin Knaipp, Franz Unterleitner, Austria IVI i k rosy ste me International AG, Unterpremstätten, Austria Keywords: semiconductors, smart power devices, device models, thermal boundary conditions, selfheating, state of the art, device simulations, comparisons between formalisms, DD formalism. Drift Diffusion formalism, HD formalism, HydroDynamic formalism, SOR, Safe Operation Regime, increased temperature, degradation of device operation, permanent device failure, practical examples, experimental results Abstract: This work gives a review of the state of the art device simulation including selfheating effects. A comparison between the Drift-Diffusion and Hydrodynamic formalism is given. Especially the influence of non-local effects in the lattice heating is shown. The influence of the interface and contact conditions on the final lattice temperature is described, It is shown that only a correct formulation of the boundary conditions enables energy conservation of the simulated device. But even in case of energy conservation, the contact conditions are the critical uncertainty in the description of the device behaviour. Izbira termičnih robnih pogojev pri modeliranju inteligentnih močnostnih vezij Ključne besede: polprevodniki, naoprave močnostne inteligentne, modeli naprav, pogoji termični mejni, samosegrevanje, stanje razvoja, simulacije naprav, primerjave med formalizmi, DD formalizem drita difuzije, HD formalizem hidrodinamični, SOR režim delovanja varnega, temperatura povišana, degradacija delovanja naprave, izpad naprave trajni, primeri praktični, rezultati eksperimentalni Izvleček: V prispevku opisujemo trenutno stanje na področju termične simulacije elektronskih elementov z upoštevanjem efektov samosegrevanja. Podajamo primerjavo med tokovno-difuzijskim in hidrodinamičnim pristopom. Se posebej poudarimo vpliv nelokalnih efektov pri segrevanju kristalne mreže, kakor tudi vpliv kontaktov in medpovršin na končno temperaturo kristalne mreže. Pokažemo, da le s pravilno izbiro robnih pogojev omogočimo ohranitev energije simuliranega elementa. Vendar celo v takem primeru so pogoji na kontaktih kritična neznanka pri pravilnem opisu obnašanja elementa. I. Introduction In modem semiconductor devices the selfheating effects play the major role in the specification of the safe operation regime (SOR). The increase of the lattice temperature during the operation can cause a complete different device behaviour, an accelerated degradation or even a permanent device failure (e.g. second breakdown). At least the local lattice temperature of the chip is a critical factor which determines if the IC fulfill its specification. To optimize the system performance, sophisticated device simulations are needed which should also include selfheating effects. Typical devices where selfheating plays a major role are smart power devices, electrostatic discharge structures (ESD) and structures with low thermal conductivity components like silicon on insulator devices (SOI). Modern device simulators are tools to solve nonlinear coupled partial differential equation systems. Their numerical iDehaviour is optimized for the semiconductor equations to find a solution in the shortest time with an accuracy which can be defined by the user. The numerical discretisation scheme is so sophisticated that even variations in the carrier concentrations in a range of 20 orders of magnitude can be solved. This is not trivial and major efforts are carried out to find new robust numerical schemes to solve the specified equation systems /1/. The feedback from the device lattice temperature to the electrical behaviour is given by the various physical models which depend on the lattice temperature. Some examples are the carrier mobility, the densities of states and the band edge energies /2,4,5/. The calculated solution inside the device strongly depends on the given boundary conditions. The specification of these conditions is not easy and has to be done by the user. The specification of electrical conditions is quite simple. In most time the potential drop in the interconnect metal (backend) can be neglected to describe the electrical device properties in a moderate current regime. The development of power devices is often done with a large scaled interconnectto avoid any potential drop in the metal or poly lines. However the thermal boundary conditions cannot be defined as simple as the electrical case. The thermal influence of the backend cannot be reduced, and much knowledge is necessary to estimate realistic thermal conditions. In addition it is not easy to decide to which metal or poly line the user should simulate the devices. At least the final SOR is determined by the complete packaging of the device. This thermal packaging includes a temperature drop in the packaging material, in the bonding wires of the 10 cells and in the pins of the chip. All these materials finally determine the local device temperature and therefore the boundary conditions of the semiconductor. To simulate a modern semiconductor device the user has to provide the simulating structure to the device simulator. In the general case this structure consists of several segments. Each segment corresponds to a certain material. Typical materials are silicon, poly lines, oxides, interconnect dielectric, etc. However it is not always useful to describe even the complete silicon with one segment/3/. Atypical example is the hetero bipolar transistor (HBT) with a silicon/germanium (SiGe) base. The major reason to describe silicon with several seg- ments is tiie simulation time winicli can be kept iowwliile including all necessary models. In case of the HBT only the base is evaluated with the sophisticated SiGe models while in the other segments the plain silicon models are used. II. Segment Models In this section a review of the heat source term is given within the Hydrodynamic (HD) and Drift-Diffusion (DD) model /2,5/. The equation to describe the lattice temperature is the lattice heat flow equation (1). On the right hand side the heat source term H corresponds to a power density which heats up the device segments. The formulation of the heat source term depends on the used equation set. The complete equation (1) describes the transient behaviour of the selfheating. The heat conductivity k depends weakly on the lattice temperature. The second term on the left side of (1) describes the time dependent part of the equation where the thermal heat capacity p defines the material dependent properties. In case of a stationary solution of the selfheating problem, the second term on the left side of (1) vanishes. -div(KL(TL)). grad(TL(r,t)) -r- p^ ■ Cp • ^ = H(r,t) (1) In case of the DD model the source term is given in (2). When a stationary simulation is done, H only depends on the position. For pure silicon the electron and hole band edges Ec and Ev are often assumed to be constant. Only in high doped regions the band gap narrowing has to be included. In case of recombination, the recombination rate Rnet is multiplicated with the bandgap Eg to give the recombination heat. H(r) = grad (E ^ ■ Jn -h grad V q y V q J ■ Jp + Rnet ■ Eg (2) In the HD model the heat source term H is given in (3). The first two terms of (3) describe the carrier energy which is transferred to the lattice. The amount of the energy is proportional to the difference of the carrier and the lattice temperature. This means that the carriers can give their thermal energy to the lattice even if they are not accelerated by an electric field. The hot carriers relax with the cold lattice and the first two terms of (3) are therefore called relaxation terms. The terms Hn.eff and Hp,eff describe the net recombination heat of the corresponding carrier system. It is assumed that the recombination term heats up the lattice in case of recombination and cools down the lattice in case of carrier generation. The calculation of these terms is not easy because it is not so clear how to split the recombination or generation heat between the carrier energy systems and the lattice heat system. At least in case of high currents the heat transfer caused by recombination or generation is small compared to the energy transfer of the relaxation terms. It is important to note that in space charge regions the carriers are heated up by the electric field. In these regions the final carrier temperatures can reach several thousand Kelvin. The reason why the semiconductor does not melt is the low energy density of the carriers because of their low concentration. On the other hand, in regions with high carrier densities (e.g. in case of high injection) only a moderate carrier heating can be achieved. H(r> 3 kp: Th-Tl , ^ TP-TL " Hn,eff Hp gff (3) As long as the carriers give their thermal energy to the lattice, the first two terms of (3) are positive values. However, it is possible that carrier temperatures are below the lattice temperature as shown in the example section. III. Interface and Contact Models A) Interface Model The interface model described in this section deals with the interface of two adjacent semiconductor segments. In the general case there are different values of the band edge energies on each side. An example is the emitter/base interface of a Si/SiGe HBT device, where a carrier current crosses the interface. The boundary condition for the potential at the interface is simple because there is no interface dipole charge and so the electrostatic potential on each side of the interface must be the same. However the carriers move at their band edge energies which might change abruptly at the interface. Because of this abrupt change the heat source term for the DD model according to (2) leads to an infinite large power density at the interface. Fortunately the heat transfer must not be calculated explicitly. The limes of this boundary problem leads to a surface divergence of the lattice thermal heat flux density S, which in turn changes the slope of the lattice temperature at the interface. On both sides of the interface the lattice temperatures are set equal. Equation (1) therefore reads for the DD hetero interface model: divk'L •grad(TL) = div-SL = — (Eci-EC2) (4) In case of the HD model the non-local effects have to be taken into account. This means that the abrupt change of the band edge energies cause a surface divergence of the carrier energy flux and not of the lattice thermal heat flux. The change of the carrier energy flux at the interface defines the shape of the carrier concentrations and their temperatures across the interface. Again the lattice temperatures on both sides of the interface are equal. At leastthe HD interface model only affects the carrier energy flux, and the lattice is only incorporated by the volume model according to (3). B) Contact model The two commonly used thermal contact models are the isothermal contact condition and the condition of a thermal contact resistance. These two conditions can be applied for ideal electrical conductors, for ideal electrical isolators and real electrical conductors (e.g. adjacent semiconductor segments). The option for adjacent semiconductor segments makes it possible to calculate the selfheating only in defined segments, to achieve shorter simulation times. The isothermal condition specifies a certain contact temperature for the contact boundary. This corresponds to a Dirichlet boundary problem of (1). In contrast the specification of a thermal contact resistance defines a Neumann boundary problem for the energy flux of (1). The physical meaning of this condition is that the amount of heat flux, which crosses the boundary, is proportional to the difference of the boundary temperature and the temperature of a specified thermal heat sink. The specification of these setup conditions seems to be simple, but each condition can lead to numerical and physical problems if a wrong specification is used. In case of the isothermal condition it is possible to simulate an overheated device with an arbitrary small current. The reason therefore is a too small chosen contact area, which leads to wrong simulation results. If a thermal resistance is defined and the resistance is too high, the device may heat up to arbitrary high temperatures even if the device current is low and the contact areas are large. This can result from an inaccurate definition of the simulation structure as described in a previous section. If an electric current crosses the boundary, the simple thermal contact models have to be extended to electro/thermal contact models. These models include the energy transfer when the carriers move from the contact metal to the semiconductor. The energy diagram of the metal/n-doped semiconductor contact is shown in Fig.1. metal E, ------^ r ii-doped seniicoiiducLor _i_^ e. e ■tsi! Ev Fig. 1: Bandedge energy diagram on a metaiIn-doped semiconductor contact. In case of a contact current the carriers gain or loose energy because of the difference between the metal Ferminiveau Ep and the corresponding conducting band Ec or Ev of the semiconductor. It should be noted that the intrinsic level of the semiconductor is shifted by the Build-in energy Eobi. In case of a n-doped semicon- ductor the barrier of the electrons is much lower compared to the barrier of the holes. If we assume a n-doped device with nearly equivalent electron and hole currents, it is easy to see that the hole current gives the main part of the carrier contact heating or cooling. A similar contact bandedge energy diagram can be given for a p-doped semiconductor. Only when all current semiconductor/metal boundaries are incorporated by this model, an energy conservation of the device can be shown as described in (5). In this equation the electrical power dissipation of m electrical contacts is equal to the lattice heat flux of n thermal contacts. The vector A corresponds to the boundary normal area and defines the sign of the power XA,-JrU,=XArSL 1=1 (5) i=i dissipation. Equation (5) also holds for hetero devices and even for multi segment structures. IV Examples This section will give two examples which should show the effects explained in the previous sections. First a simple two segment silicon diode with an abrupt p/n junction is described. The second example shows the selfheating of a hetero bipolar field transistor. Both were simulated with the stationary semiconductor equation set, which means that there is no transient thermal and electrical behaviour. A) The Diode The example was chosen because a bias applied in forward direction results in high electron and hole currents. This allows to verify the contact and interface conditions as described in section II. The device is modeled as a two segment structure with a step junction at the segment interface and a constant doping in each segment of about 1 .Oe1 /cm^^. Two contact resistances are applied with values of Rth = 6.9e-5 [Kcm^/W] on each side. The device has a length of 60 ijm and a contact area of 6 fjm^. Fig.2 shows the diode with an applied forward voltage of -t-0.6 V at the anode (left side). The left part of the figure shows the lattice heating while the right side shows the band edge potentials of the device. The most upper line of the band edge potentials corresponds to the hole potential which is followed by the device potential and the lowest line corresponds to the electron potential. In thermal equilibrium that means without an applied voltage, the potential drop at the junction corresponds to the Built-in potential which is about 0.82V. One should be aware that in the vicinity of the junction the potentials are continual functions without any unsteadiness at the physical junction. The right side of Fig. 2 shows that at a contact bias of 0.6V the junction voltage drop is already reduced to 0.22V. This voltage drop causes a high diffusion current over the junction with an electron to hole current ratio of nearly 2.5. This ratio is mainly determined by the different mobilities of ■ hole bandedge pobentiai device potential electron bandedge potential Fig. 2: Lattice temperature (ieft diagram) and band edge potentials (right diagram) of a diode in forward direction. The applied cathode voltage is 0.6V. The electrons move from the right to the left. hole bandedge potential device poteatidi electron bandsdge potenti^sl -3D -25 -20 -15 -lo' -5' b ' ^ ' I'o ' 15 ' 2b ' 25 3 X [urn] Fig. 3: Lattice temperature (left diagram) and band edge potentials (right diagram) of a diode in fonNard direction. The applied cathode voltage is O.SV. The electrons move from the right to the ieft. p—doped n-cioped hole bandedge poientiai device potential electiron bandedge potential -30 '-25 "2D -15 -lo' i ' 10 ' I's ' 20 ' 2i 3Ö X [u-I Fig. 4: Lattice temperature (left diagram) and band edge potentials (right diagram) of a diode in forward direction. The applied cathode voltage is 0.9V. The electrons move from the right to the ieft. The maximum lattice temperature Is in the p-doped side. From this point the lattice heat flux flows to the anode contact and the heat sinl< of the p/n junction. p-doped n-doped -30 -25 -20 -15 -lo' -5 ' ^ i " I'O ' l'5 20 ' 3Ö y. [um] Fig. 5: Lattice temperature (left diagram) and band edge potentials (right diagram) of a diode in forward direction. The applied cathode voltage is 2.0V. The electrons move from the right to the left. The maximum of the lattice temperature is at the pin junction. The device overheating is relatively high compared to the increase of the contact temperature. In a more realistic application the contact resistance would be higher so that the final lattice temperature would be also higher. <1 carrier uemperatiires X; 1 lattice temperature -!) -a -7 -5 -6 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9