SYSTEM DESIGN CONSIDERATIONS FOR LOW-POWER, BP A-E A/D CONVERTER USED FOR COHERENT DETECTION SYSTEMS Drago Strle University of Ljubljana, Faculty of Electrical Engineering, Slovenia Key words: BP Delta-Sigma A-D converters, BandPass Delta-Sigma A-D converters, coherent detection, power optimization, decimators, decimation filters, BW, Bandwidth, adders, running sum architecture Abstract; Design considerations for low-power coherent detection system using BP A-Z A/D converter are presented. Some optimization steps for reducing power consumption are explained together with some system and circuit level simulation results. A 6"^ order modulator design and corresponding 4"^ order running-sum decimator are presented. Suggestions are made for further reduction of power consumption, which is estimated to be less than SOO^iWfor 6"' order modulator with S-C loop filter implementation, oversampling ratio 0=256, S/N = 110dB at f<,„s=64kHz and bandwidth BW=260Hz. Zasnova sistema za koherentno detekcijo z uporabo BP A-E A/D pretvornika z nizko porabo moči Ključne besede: BP Delta-Sigma A-D pretvorniki pasovno propustni analogno-digitalni, detekcija koherentna, optimizacija moči, decimatorji, filtri deci-macijski, BW širina pasovna, seštevalniki, arhitektura s seštevalniki Izvleček: V članku je opisan postopek načrtovanja sistema za koherentno detekcijo z uporabo BP A-I A/D pretvornika na sistemskem nivoju. Predstavljeni so nekateri optimizacijski postopki na visokem hierarhičnem nivoju s pomočjo katerih lahko zmanjšamo porabo moči takega sistema ter rezultati nekaterih simulacij. Zasnovi BP A-Z modulatorja šestega reda in pripadajočega decimatorja četrtega reda sta izbrani glede na postavljene zahteve in ostale pripadajoče kriterije. Podani so predlogi za zmanjšanje porabljene moči. Ocenjena poraba moči je približno 500(.iWza eno bitni modulator s filtrom šestega reda implementiranim s tehniko S-C, razmerjem vzorčevalne frekvence proti mejni D=256, razmerjem S/N=110dB pri vzorčevalni frekvenci fovs=64kHz in pasovno širino BW=260fHz. 1. Introduction With down-scaling of integrated circuit technology in recent years analog signal processing circuits are more and more replaced by digital signal processing circuits because of several advantages: flexibility, programmability reliability, noise immunity, reduced power consumption, easier and more reliable design and test if automated procedures are used. The key operations in such systems are A/D conversion and for narrow band signals appropriate sub-sampling of correctly band-limited spectrum. In our case, simple coherent detection circuit and BP A-E modulator followed by simple and efficient digital decimation filters are used to transfer input double side band signal with suppressed carrier and limited bandwidth to a digital stream of data, which can be further processed by appropriate DSP algorithm. The technique has several advantages compared to traditional analog implementation: lower power consumption, easier integration and because of that higher reliability, better flexibility etc. It is essential to reduce power consumption as much as possible. The only way to do that is to perform optimization on each hierarchical level from the system to the layout. We are trying to design a coherent detection system with as small power consumption as possible. The signal that must be down-sampled is double side band signal with suppressed carrier and with the bandwidth BW<260Hz centered at 16kHz. The purpose of the system is to perform coherent detection of a low-frequency signal that causes modulation of the carrier, bring it down to the base-band and convert it to the digital domain using high resolution A/D converter with S/N>110dB. As usual this can be done in many different ways and it seems that most promising approach regarding silicon area and power consumption is BP A-2 A/D converter and coherent detection. In section II principles of coherent detection using BP A-Z A/D converter are shortly explained and some system level simulation results are presented. Design steps for order BP A~E modulator are shortly presented in section III with some key parameters regarding architecture, stability, speed, power consumption. Section IV deals with possible realisation of the decimator. Section V summarises simulation results and presents the conclusions. 2. System for coherent detection Block diagram of possible system for coherent detection of narrow-band signals is presented on figure 1. cos 1 fdec ^_L. PSD of a bifslream - vm BP nwdiilator vm 6tli order , ...........■ DEC m fovs k silt DEC \Cos ySin sigJN t t fdc'c V Fig. 1: Coherent detection system BP modulator can be implemented with continuous time or S-C loop filter. Using S-C realisation makes A/D conversion more accurate and less sensitive to the process parameters and temperature variations compared to continuous time implementation, but requires additional filtering (anti-aliasing filter) to prevent folding of unwanted components to the base-band of the BP modulator. The continuous time gm-c loop filter reduces power consumption even further because it does not require anti-aliasing filter since all out-of-band components are attenuated efficiently by its loop filter. In addition the speed of the transconductance element needs to be smaller compared to the operational amplifier used in S-C implementation. Unfortunately CT approach it is less stable and less accurate. In this article S-C implementation is proposed for the reasons of accuracy. Sampling frequency of the BP modulator is selected as low as possible: fovs=4fosc, thus a very simple method of coherent detection is available: multiplication of a bit-stream with coherent sine wave. It can be easily accomplished before the decimation filtering using frequency fcos=fovs/4 realised as another bit-stream with values taken from table 1 /4/. Coherent detection with defined relation among signal frequencies is reduced to the generation of simple streams of +1, 0 and -1 and 1 bit multiplication between bit-stream and Sin or Cos signal. Multiplying Vm by Cos or Sin signals is followed by filtering and down sampling. Some additional digital signal processing not described in this article gives further information about frequency and phase of demodulated signal: x=VmCos and y^VmSin. Table 1:Sin and Cos signal generation K Cos Sin 0 1 0 1 0 1 2 -1 0 3 0 -1 4 1 0 Frequency 1,55 1.56 1,57 1.58 Frequency 1,63 1,64 1,65 Fig. 2: Spectrum of a bit-stream Vm The spectrum of a bit-stream Vm after BP A-S A/D converter is very rich and shown on figure 2 for the case of 2 spectral components of equal power with frequencies fovs/4-fx and fovs/4+fx (see detail on figure 2). Frequency fx is a frequency of modulation signal that carhes the information. The whole spectrum is composed of 2 spectral components in the band of interest, quantisation noise, thermal and 1 /f noise and aliased crosstalk, which is much smaller than any other component if designed properly. Ideally the Cos or Sin signals are sine waves with only one spectral component with frequency fx. Let us discuss the process of multiplication with our coherent signals. One can imagine that every spectral component in the Vm is multiplied by a sine wave with frequency fs/4, which is in fact a stream of +1, 0 and -1. The band below fs/4 is by multiplication reversed and placed to the same band and also translated to the band between fs/4 and fs/2. The band above fs/4 is transferred between 0 and fs/4 and fs/ 2 and 3fs/4 and aliased back to the band fs/2 to fs/4. The spectrum after multiplication is shown on figure 3. 1 /f noise and offset components are transferred around frequency fs and are later attenuated by decimation filter. The noise power after multiplication with a coherent sine-wave is composed of all noise sources from the band below and above fosc and are included in the simulation results presented on figure 3/1/. The upper portion of the spectrum can not be seen because of the logarithmic scale. Similar spectrum exists fon/mS/n. Frequency components above 125Hz must be attenuated using appropriate decimation filter. Possible realisation of the decimation filter is sine'' characteristics with accumulate and dump architecture. Transfer function is presented on figure 5. A order is used because in that case the slope of the decimation filter is bigger than the slope of quantisation noise produced by 6"'' order BP modulator. Short description of the implementation of the decimation filter is given in section IV. The spectrum ycos after sinc'^ decimator, down-sampled to fdec=fovs/f^=250l-iz, with modulation frequency fx=33Hz is presented on figure 4. Similar spectrum with different phase is obtained on the output ysin- Further digital signal processing of both signals can extract all necessary infor- PSD of Vm'Cos signaNO noise=-106.8267 band=0to125 Frequency [Hz] Fig. 3: Spectrum of VmCos for fx ^'SSHz mation about frequency and phase of the rotation. Since all signals are very low frequency, serial digital signal processing can be used to save silicon area. H(z)deci4 fs=64000 clec1= 256 __________ (req. (Hz] 3. order modulator A 6th order 1 bit BP modulator with oversampling ratio R=256 can fulfil the requirements: S//V> HOdB in a band of 125Hz. Figure 6 plots possible noise transfer function with poles and zeroes defined in table 2 and on figure 7, Signal transfer function (STF) depends on realisation, stability constraints, area and power consumption and will be presented in near future with special emphasise on power consumption optimisation and stability constraints. For 3-C implementation the jitter does not present a problem, so normal comparator is used for one-bit A/D, while 1 bit D/A is implemented by non-return-to-zero S-C stage charged to the reference voltage and controlled by the outcome of the A/D conversion process or in other words by the bit-stream. The positions of poles and zeros are for the time being selected according to the Lee's rule of thumb /5/, which requires that the | NTF (e'"') | <2 for the whole band of interest. Since this condition is pessimistic and does not give insight into the real stability of the modulator it will be refined in the design and simulation steps that still needs to be implemented. Table 2: Poles/Zeros of possible Noise Transfer Function Poles Zeros -0.2151\pm jO.8333 -0.0048\pm jl.OOOO +0.0000\pm jO.7499 +0.0000\pm 11.0000 +0.2151\pm jO.8333 +0.0048\pm 11.0000 NTF Fig. 4: Decimator frequency characteristics ___ -20:- CÜ i X3 -40 -100 -120 PSD of y'Cos signalno noise=-113.8629 Q.10 I ■ 10- K lO" lo' CD "O V \,! -'^§24-0.248 0.2'5 0.252 0.254 0.256 0.256 0.26 f/fs Fig. 6: Noise transfer function (NTF) Frequency |Hz] Fig. 5: Down-sampled spectrum of the rotation signal after decimator Poles & zeros 08 0.6 0. 0.2 M " -0.2 Poles. Zeros. -0.2151 +/-j0.8333 -0.0048+/-jl .0000 *0.0000*/-i0.7499 •0.0000»/-i1.0000 +0 2151+/-j0.s333 +0.0048+/-j1.0000 Re F/g. 7: Poles and zeros of noise transfer function (NTF) 4. Decimator There are many possible realisations of the decimation filters. Efficient solution in terms of area and complexity is sine decimator /3/, which does not need any multiplication and the only arithmetic operation needed is 2's complement addition. Here sine" (figure 8) is implemented because we have 6th order BP modulator with transfer function presented on figure 4. The slope of the frequency characteristics of the integrators before down sampling is bigger than the slope of the quantisation noise and thus guaranties enough attenuation of high frequency quantisation noise as well as other noise contributions. Very simple programmable accumulate-and-dump architecture has been implemented, so the oversampling ratio can be easily changed by simply taking every r"^ sample from the IIR part and processed it by FIR low-frequency section of the decimator. Number of bits needed for correct operation is: M log,o(2) = 32bits Where R is decimation ratio, M is decimator order, ri= 1 is number of bits at the input and nbits is number of bits needed for internal registers of the decimator, so that the overflow is correctly processed. IIR and FIR parts can be processed serially since the sampling frequency is rather low. Programming of the decimator is possible by changing the oversampling ratio from f?=2 to 256 and taking different bits from the last register of IIR to the first register of FIR every R'^ oversampling clock cycles. Figure 5 is the result of processing the signal VmCrnos with real s/nc'' decimator If attenuation at 125Hz is not acceptable this can easily be corrected by simple digital all-pass filter following the decimator The decimator realised in 0,6|im CMOS technology with foi/s=64kHz consume approximately 20).iA average current and the rest (80)„iA) are reserved for the modulator Fig. 8: Block diagram of sine'* decimator 5. Conclusions A system design considerations and some important steps for the power consumption optimisation of a coherent detection system using 6"^ order BP modulator and 4"^ order sine'' that can be used for mixed-signal processing of a narrow band double-side band signals with suppressed carrier are presented in the article. Possible architecture is evaluated and some system and circuit level simulations were performed to show the usefulness of the approach. Architecture of the BP modulator and decimator has been defined and important system level simulation results have been presented. The realisation of proposed architecture is feasible, so circuit design of a BP modulator will follow using S-C and gm-c implementation of the loop filter with big attention to the power consumption optimisation and stability constraints. References /1/ strle D., "Capacitor area and power-consumption optimisation of higii order modulators", Informacije fvtlDEM, 31(1), 129-135, 2001. /2/ ReeseG.lvl., MarekE.L., LobitzD.W., "Three dimensional finite element calculations of an experimental quartz rotation sensor", Proceedings of Ultrasonic symposium, 419-422, Oct. 1989. /3/ Norsworthy S.R., Sotireier R., Temes G.C., "Delta-Sigma Data Converters,", IEEE press, 1997. /4/ Jürgen A.E.Pvan Engelen, R.J. vandePlassclie, E.Stilwoort, A.G. Venes, "A sixtii-order continuous-time bp sigma-delta modulator for digital radio if", IEEE JSSC 39{!"), 1753-1764, Dec. 1999. /5/ K.C.H. Ctiao, S. Nadeen, W.L.Lee, C.G. Sodini" A Higher Order Topology for Interpolative Modulators for Oversampling A/D Converters," IEEE Trans on CAS, vol. 37, no. 3, pp 309-318, March 1990. Drago Strle Faculty of Electrical Engineering Tržaška 25, 1000 Ljubljana, Slovenia E-mail: drago.strle@fe.uni-lj.si Prispelo (Arrived): 26.10.01 Sprejeto (Accepted): 10.12.01 263