ISSN 0352-9045 Informacije L MIDEM Journal of Microelectronics, Electronic Components and Materials Vol. 44, No. 3 (2014), September 2014 Revija za mikroelektroniko, elektronske sestavne dele in materiale letnik 44, številka 3 (2014), September 2014 □□□□□ □□ □□□□□ □□ □□□□□ □□ □□□□□ □ □□□ nXLDD □□ □□□mu RS □□□□□ 1 UDK 621.3:(53+54+621+66)(05)(497.1)=00 ISSN 0352-9045 Informacije MIDEM 3-2014 Journal of Microelectronics, Electronic Components and Materials VOLUME 44, NO. 3(151), LJUBLJANA, SEPTEMBER 2014 | LETNIK 44, NO. 3(151), LJUBLJANA, SEPTEMBER 2014 Published quarterly (March, June, September, December) by Society for Microelectronics, Electronic Components and Materials - MIDEM. Copyright © 2014. All rights reserved. | Revija izhaja trimesečno (marec, junij, september, december). Izdaja Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale - Društvo MIDEM. Copyright © 2014. Vse pravice pridržane. Editor in Chief | Glavni in odgovorni urednik Marko Topič, University of Ljubljana (UL), Faculty of Electrical Engineering, Slovenia Editor of Electronic Edition | Urednik elektronske izdaje Kristijan Brecl, UL, Faculty of Electrical Engineering, Slovenia Associate Editors | Odgovorni področni uredniki Vanja Ambrožič, UL, Faculty of Electrical Engineering, Slovenia Slavko Amon, UL, Faculty of Electrical Engineering, Slovenia Danjela Kuščer Hrovatin, Jožef Stefan Institute, Slovenia Matjaž Vidmar, UL, Faculty of Electrical Engineering, Slovenia Andrej Žemva, UL, Faculty of Electrical Engineering, Slovenia Editorial Board | Uredniški odbor Mohamed Akil, ESIEE PARIS, France Giuseppe Buja, University of Padova, Italy Gian-Franco Dalla Betta, University of Trento, Italy Martyn Fice, University College London, United Kingdom Ciprian Iliescu, Institute of Bioengineering and Nanotechnology, A*STAR, Singapore Malgorzata Jakubowska, Warsaw University of Technology, Poland Marc Lethiecq, University of Tours, France Teresa Orlowska-Kowalska, Wroclaw University of Technology, Poland Luca Palmieri, University of Padova, Italy International Advisory Board | Časopisni svet Janez Trontelj, UL, Faculty of Electrical Engineering, Slovenia - Chairman Cor Claeys, IMEC, Leuven, Belgium Denis Donlagic, University of Maribor, Faculty of Elec. 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Prispevke iz revije zajema ISI® v naslednje svoje produkte: Sci Search®, Research Alert® in Materials Science Citation Index™. Po mnenju Ministrstva za informiranje št.23/300-92 se šteje glasilo Informacije MIDEM med proizvode informativnega značaja. Design | Oblikovanje: Snežana Madic Lešnik; Printed by | tisk: Biro M, Ljubljana; Circulation | Naklada: 1000 issues | izvodov; Slovenia Taxe Percue | Poštnina plačana pri pošti 1102 Ljubljana Informacije imidem Journal of Microelectronics, Electronic Components and Materials 44, No. 3 (2014) Content | Vsebina Review scientific paper Pregledni znanstveni članek B. Batagelj, V. Janyani, S. Tomazic: Research Challenges in Optical Communications Towards 2020 and Beyond 177 B. Batagelj, V. Janyani, S. Tomažič: Raziskovalni izzivi optičnih komunikacij do in preko leta 2020 Original scientific papers Izvirni znanstveni članki T. Korotko,U. Merisalu, M. Magi, K. Peterson, E. Pettai: Development of Testing Method for Smart Substations with Prosumers 185 T. Korotko,U. Merisalu, M. Magi, K. Peterson, E. Pettai: Razvoj testnih metod za pametne postaje s proizvajalci-porabniki A. Djugova, J. Radic, M. Videnovic-Misic, 201 B. Goll, H. Zimmermann: A Compact 3.1-5 GHz RC Feedback Low-Noise Amplifier Employing a Gain Enhancement Technique A. Djugova, J. Radic, M. Videnovic-Misic, B. Goll, H. Zimmermann: Kompakten 3.1-5 GHz RC povratni nizkošumni ojačevalnik s tehniko povečanja ojačenja T. Alam, M. R. I. Faruque, M. T. Islam: 212 Printed Circular Patch Wideband Antenna for Wireless Communication S. S. Islam, M. R. I. Faruque, M. T. Islam: 218 Design and Analysis of a New Double Negative Metamaterial A. Chub, O. Husev, A. Blinov, D. Vinnikov: 224 CCM and DCM Analysis of Quasi-Z-Source Derived Push-Pull DC/DC Converter T. Alam, M. R. I. Faruque, M. T. Islam: Tiskana krožna krpičasta širokopasovna antena za brezvrvične zveze S. S. Islam, M. R. I. Faruque, M. T. Islam: Načrtovanje in analiza novega dvojno negativne meta material A. Chub, O. Husev, A. Blinov, D. Vinnikov: Analiza CCM in DCM Push-Pull DC/DC pretvornika z impedančnim prilagodilnim vezjem E. Karakulak, R. Mutlu, E. U?ar: 235 Sneak path current equivalent circuits and reading margin analysis of complementary resistive switches based 3D stacking crossbar memories E. Karakulak, R. Mutlu, E. U?ar: Nadomestna električna vezja za analizo kvarnih tokov in analiza bralne meje pri komplementarnih uporovnih stikalih na osnovi 3-D večplastnih križnih pomnilnikov S. Kelej, F. Kaçar, H. Kuntman, F. Kelej: 242 A New FGMOS FDCCII and Filter Applications Front page: Radio and optical mulitpath (B. Batagelj et al.) S. Kelej, F. Kaçar, H. Kuntman, F. Kelej: Nove možnosti uporabe FGMOS FCCII in filtrov Naslovnica: Radijske in optične poti (B. Batagelj et al.) 175 175 Review scientific paper /midem Iournal of M Informacije | Journal of Microelectronics, Electronic Components and Materials Vol. 44, No. 3 (2014), 177 - 184 Research challenges in optical communications towards 2020 and beyond Boštjan Batagelj1, Vijay Janyani2, Sašo Tomažič1 1University of Ljubljana, Faculty of Electrical Engineering, Ljubljana, Slovenia 2Malaviya National Institute of Technology, Dept. of Electronics and Communication Engineering, Jaipur, India Abstract: This paper presents an overview of future research activities in the field of optical telecommunications. The year 2020 is considered a milestone, when the capacity of optical communication links via a single optical fiber will reach the physical limitation called the "fiber wall". It is expected that advances in systems with a standard, single-mode, optical fiber, which enables increasingly higher transmission capacities due to accelerated scientific research, will reach the point where the capacity of the optical link via a single optical fiber will no longer grow. Due to this collision with the "fiber wall", research efforts to develop future solutions are all the more necessary. This article provides an overview of the fields in which the future development of optical communications will give the most focus. In the field of optical devices and components, the development goes in the direction of integrated optics and new optical fibers. In order to achieve the objectives, the new communication techniques comprise coherent communications, multidimensional modulation formats and multiplexing techniques, as well as the use of digital signal processing. Modern optical networks extend from the high-performance fiber optic connections in the backbone to broadband access in user's home, in the future their architecture will enable an adaptability to wavelength, bandwidth and modulation format. The main aim of the development towards 2020 and beyond is to build optical communication systems that will enable the transfer of large amounts of data with the minimum power consumption using the simplest and cheapest equipment. Keywords: optical devices, optical fiber, optical networks, optical communication Raziskovalni izzivi optičnih komunikacij do in preko leta 2020 Izvleček: Članek predstavlja pregled bodočih raziskovalnih aktivnosti na področju optičnih telekomunikacij. Leto 2020 se pojmuje kot mejnik, ko bo predvidoma zmogljivost optične komunikacijske zveze po enem optičnem vlaknu dosegla fizično omejitev imenovano »vlakenski zid«. Pričakuje se da bodo raziskave v sistemih s standardnim enorodovnim optičnim vlaknom, pri katerih se poskuša doseči vedno višje prenosne zmogljivosti, prišle do položaja, ko zmogljivost optične zveze po enem optičnem vlaknu ne bo več napredovala. Zaradi trčenja v »vlakenski zid«, so raziskovalni napori v bodoče rešitve toliko bolj potrebni. V članku je narejen pregled področij na kareta se bo razvoj optičnih komunikacij najbolj osredotočil. Na področju optičnih naprav in elementov gre razvoj v smeri integrirane optike in razvoja novih optičnih vlaken. Z namenom doseganja svojih ciljev nove komunikacijske tehnike vključujejo koherentne komunikacije, večdimenzionalne modulacijske formate in tehnike multipleksiranja ter s pridom uporabljajo digitalno obdelavo signalov. Sodobna optična omrežja se raztezajo od visoko zmogljivih optičnih povezav v hrbtenici do širokopasovnega dostopa v uporabnikovem domu. Njihova arhitektura pa bo v bodoče omogočala prilagodljivost na valovno dolžino, pasovno širino in modulacijski format. Cilj razvoja do in preko leta 2020 je izdelati optične komunikacijske sisteme, ki bodo omogočili prenos velike količine podatkov z najmanjšo porabo moči s pomočjo najenostavnejše in najcenejše opreme. Ključne besede: optične naprave, optično vlakno, optična omrežja, optične komunikacije * Corresponding Author's e-mail: bostjan.batagelj@fe.uni-lj.si 1 Introduction Optical communications have been continuously developing over the past four decades and today they represent a mature industry [1]. New applications and services that require more and more data, and users who expect the instant and correct delivery of such data, without having to wait and experiencing errors, require increasingly sophisticated optical communication systems. Users are mainly interested in the speed 177 © MIDEM Society B. Batagelj et al; Informacije Midem, Vol. 44, No. 3 (2014), 177 - 184 and the quality of the services, which provide them with a good user experience [2]. In this context, it is necessary to bear in mind that underneath a user's requirements there are many communication levels. Operators of telecommunications networks should ensure the smooth operation of their systems, which face the challenges of a constant increase in data traffic that must be transferred as fast as possible and with the least possible delay. They are, however, constrained by the costs associated with building (capital expenditures - Capex) and operating (operational expenditure - Opex) a telecommunications network. From the upcoming systems telecommunications operators expect a better ratio between transmission capacity and costs. The capacity of the optical communication link is subject to the equipment available and its electronics, the communications channel and the type of transmission signal. All three elements are equally important for the correct and immediate delivery of telecommunications data, and therefore future researches will also be focused on these main areas: new optical devices, improved communication techniques and new architectures for optical networks (as shown in Figure 1). It is in these areas of optical communications that the most innovative solutions and development achievements can be expected in the future. There are many studies based on new modulation methods and new models for data transmission, which can also handle non-linear and randomly changing optical communication channels, whereby the objective is to provide higher bit rates and better signal or service quality. For these reasons, research in the field of signal issues, questions related to the transmission channel and electronics in the receiver and transmitter are closely inter-related and interdependent. Figure 1: Three directions of development in optical communications. Ever more powerful optical links, which are able to transmit more and more data over increasing distances, are the results of previous research. These optical links are now adapted to the use of a standard, single-mode, optical fiber, which has been a well-established trans- mission medium for a long time [1]. If future research achievements with the same time increment will shift the capacity boundaries of optical communication links by single-mode optical fiber [3], it is expected that by around 2020 the physical limit will be reached when the capacity of an optical line via a single optical fiber will no longer progress. The exact time of the emergence of the point of capacity constraint for a single mode fiber, called the "fiber wall" is difficult to predict. At present, research is needed, which will focus on new solutions in the field of optical backbone networks [4]. Once the "fiber wall" is achieved, it will be too late for this kind of research, because service providers will not be able to afford the subsequent installation of a parallel network in order to increase capacity. The installation of a parallel network is linked to Capex and Opex, which increase almost linearly with increasing capacity. 2 Optical devices In the field of optical communication devices, developments are in the direction of integrated optics known as Planar Lightwave Circuits (PLCs) or Photonic Integrated Circuits (PICs). Integration has become an important tool in the effort to reduce the production costs of optical devices, increase the functionality of telecommunications networks and, ultimately, limiting the impact on the environment in relation to the amount of carbon-footprint emissions resulting from the use of electricity. The development of optical circuits suggests that cheaper monolithic solutions will replace the current hybrid solutions [5]. The current technology of hybrid integrated circuits in a single enclosure combines various integrated circuits or discrete components that, connected together, perform certain optical and electrical functions. Future, monolithic integrated circuits will be a combination of passive and active circuit elements in a single optical chip. The aim of modern research is the integration of light sources (lasers), transmitters, modulators and signal processing elements (and vice versa; detectors, demodulators and receivers) on a single semiconductor substrate. Special attention will continue to be given to optical receivers as, based on the entire telecommunications connection, the signals in the receiver are the weakest and therefore this requires careful treatment. The developments in the field of optical devices also includes the now familiar Micro-Electro-Mechanical Systems (MEMS) [6], Free-Space Optics (FSO), discrete optics, photonic crystals, ring resonators, gratings and plasmonic circuits and devices. 178 M. E. Basak et al; Informacije Midem, Vol. 44, No. 2 (2014), 142 - 151 In relation to the development of new devices, the research will not focus only on III-V semiconductors (such as indium phosphide - InP) [7] but also on devices based on silicon, which is the so-called area of Silicon Photonics [8], and its family of oxides and nitrides. Silicon is more abundant, cheaper and more effective than III-V semiconductors. The latest developments in the field of integration are the integration of silicon waveguides with silicon nitride waveguides, or organic materials, the integration of waveguides of lithium nio-bate (LiNbO3) with silicon waveguides and the integration of liquid crystals with silicon waveguides. In the future these and other integrations will also be an important part of research in the field of optical materials and technologies. The fact is that optical integrated circuits are much more expensive than the existing electronic integrated circuits; therefore, for many years the signal processing has been transferred from the optical domain to the domain of electronics. Electronics is also much more effective than optics, because it uses Digital Signal Processing (DSP). In the past decade, DSP became much more effective than analogue signal processing, which is still in use when we are working in the optical domain. Because there are no new technologies on the horizon that would enable the cheaper processing of optical signals, integration will retain an important role in combining the fields of optics and electronics in the years to come. According to the new system requirements, it is expected that the new generation of optoelectronic devices and integrated optics will be adaptable to the wavelength, bandwidth and modulation format [9]. Future research will also focus on the development of entirely new all-optical devices, which will have less consumption than the current opto-elec-tronic solutions. 3 Communication techniques The aim of the further development of optical communications is thus to extend the reach as well as increase the transmission capacity of optical links. Currently, the use of coherent optical systems is very interesting and very important. This idea emerged in the early 1980s and then "disappeared" due to the invention of optical amplifiers [1]. Now, a new need for the use of coherent systems has emerged that can come to life in reality with the use of new optical devices. The great advantage offered by coherent systems is the possibility of performing electronic equalization of the optical channel. Coherent optical systems can operate at very low levels of the received signal and very high bit rates, which range into the sphere of Tbit/s [10]. Interestingly, coherent optics uses techniques that are commonly used in radio systems, such as multi-level modulation formats (Differential Phase Shift Keying (DPSK), Quadrature Phase Shift Keying (QPSK) and various forms of Quadrature Amplitude Modulation (QAM)) and techniques with more orthogonal carriers known as Orthogonal Frequency-Division Multiplexing (OFDM). In order to correctly work a coherent system has to measure the complete received electric field (amplitude, phase and polarization) and use this information to electronically equalize chromatic, polarization and even modal dispersion. More than two decades ago Wavelength Division Multiplexing (WDM) technology began to enforce itself on the backbone optical networks. In all the previous years, an increase in the transmission capacity of WDM technology went in the direction of increasing the number of channels, the used bandwidth and bit rate for each channel and reducing the channel spacing. All four methods of development have now reached a high level of engineering perfection. Modern, spectrally efficient systems have a large number of channels (sometimes over a hundred), which extend beyond the Conventional (C), Long (L) and even Short (S) wavelength bands, wherein in each of the channels the traffic can run with a bit rate of 40 Gbit/s and more. In accordance with the ITU-T standardization the downward trend of channel spacing has led to the current use in the distribution network of 12.5 GHz. The new network elements are adapting to the flexible grid of the optical spectrum. While increasing the spectral efficiency of WDM systems by reducing the spacing between individual WDM channels, the development goes in two largely equivalent directions. In this way, complex procedures for shaping the spectrum are used, based on the orthogonality between the different WDM channels, either in the time domain or in the frequency domain. As an alternative to coherent OFDM transmission the system is known as the Nyquist WDM (Ny-WDM). In the case of Ny-WDM, the subcarriers are spectrally shaped so that their bandwidth is close to, or equal to, the Nyquist border for the emergence of inter-symbol interference and crosstalk between the channels [11]. In this context, to separate closely spaced WDM channels, highly selective optical filters are no longer used; instead, advanced Digital Signal Processing (DSP) [12] and Digital-to-Analogue Converters (DAC) are employed, which enables the precise formulation of the spectrum for each channel [13]. The use of high bit rates and long fiber ranges by WDM technology and erbium-doped fiber amplifiers (EDFA) triggered some previously insignificant restrictive phenomena. Among them, it is necessary to draw 798 B. Batagelj et al; Informacije Midem, Vol. 44, No. 3 (2014), 177 - 184 attention to Polarization Mode Dispersion (PMD) and the nonlinearity of the optical fiber. The increased importance of PMD gave rise to many research studies, based on addressing the weaknesses and limitations as a result of the PDM as well as Chromatic Dispersion by means of digital signal processing. As shown in Figure 2, the transfer of the optical fiber, on the one hand limits the low signal-to-noise ratio, and on the other, a too high nonlinearity is becoming noticeable at large distances and high optical powers. The transfer can be improved by reducing the attenuation and non-linearity in an optical fiber, wherein Large-Aeff Pure-Silica Core Fiber (LA-PSCF) optical fibers are essential as they introduce the lowest attenuation (up to 0.161 dB/km) and two times smaller non-linearities known in a standard single-mode fiber. transmission capacity "fiber wall" direction of development lower limit due to low signal to noise ratio transmission distance or transmission capacity Figure 2: Transmission limits for optical fiber communications. For radio communications the originally developed techniques are also used in the case where a so-called multimode fiber transmits a smaller number of modes, which forms the optical Multiple-Input Multiple-Output (MIMO) system [14]. As shown in Figure 3, while in radio communications the MIMO is reached with a larger number of transmission and reception antennas, in optical communications, multipath in multi-mode optical fiber is utilized. The generic dispersion in the fiber acts as a multipath in the space. Figure 3: Radio and optical multipath. In addition to the established multiplexing techniques, which can increase transmission capacities at the expense of the multi-dimensionality of the frequency, space or polarization, in recent years the exploitation of Orbital Angular Momentum (OAM) of electromagnetic waves presents itself as a new dimension of multiplexing in optical communications. In this context the orthogonality of the so-called vortex modes or modes with a phase singularity are exploited, which carry different orbital angular momentum [15]. Some researchers do not consider the use of OAM as a new technique of multiplexing, but as spatial multiplexing, which includes the MIMO. The similarity between optical MIMO and OAM is, in optical communications, seen in the fact that both of them exploit more modes for data transmission. They differ in the way of distributing the data between modes. The main difference between radio MIMO and optical MIMO is noticeable in the way of reception or the design of the receiver. Radio MIMO techniques require digital signal processing at the receiver side, with which individual data streams are distinguished by a knowledge of the transmission channel characteristics. Before and during the communication, the characteristics of the transmission channel are determined by a learning sequence, which is known to the receiving side. Neither digital processing nor a knowledge of the channel are not required for multiplexing with OAM, because to distinguish between the signals only spatial filtering is needed with this technique. In the case of radio technology, the difference is all the more apparent than in optical communications, because in OAM a direct sight between the transmitter and the receiver is desired, in MIMO the key requirement is a strongly emphasized multipath and thus Rayleigh statistics of fading. For the transmission of multiplexing using the OAM via the optical fiber, a single-mode fiber is fundamentally inappropriate, since it does not allow the enlargement of more than one mode. Potentially, the single-mode fiber could be used at shorter wavelengths, where it acts as a few-mode fiber, or it would be necessary to use a fiber with an appropriately larger core diameter. If vortex modes spread along the normal multi-mode fiber, they make undesired coupling due to the frequency degeneration and birefringence caused by the bends and technological irregularities in the fiber. The ability to manage the vortex modes can be improved by using new types of fibers. For example, a vortex fiber [16] solves the problem of degeneration and enables the management, especially, of the lower modes (Figure 4). The air-core fiber is currently seen as the best solution for the management of higher modes. 180 B. Batagelj et al; Informacije Midem, Vol. 44, No. 3 (2014), 177 - 181 SMF MMF FMF vortex HC-PBGF Figure 4: Single-mode fiber (SMF), multi-mode fiber (MMF), few-mode fiber (FMF), vortex fiber, hollow-core photonic band-gap fiber (HC-PBGF). Transmission systems up to the point are based on single-mode (single-core) optical fiber, but current technology is approaching the limit of the capacity of single-mode fibers in the C and L bands. By approaching the theoretical capacity limits of optical fiber [17] in inter-metropolitan connections, we will soon witness the use of a technology that seemed impossible five years ago. The example of such technology is Space-Division Multiplexing (SDM) in multi-core fibers (Figure 5) [18], which is the most realistic step to Pbit/s links [19], which are located behind the "fiber wall". In the past few years we have been witnessing a 10x increase in capacity of optical transmission by using spatial multiplexing. The development of new multi-core fibers will further increase system performance. Future research projects will deal with merging few-core fibers with each other and with a single-core fiber and with the development of transmitters, receivers and amplifiers for few-core fiber connections. Finally, few-core systems will also require commutations between the cores and the individual channels and bit streams within the SDM system, which will also be the focus of future research efforts. 3-core fiber 7-core fiber 13-core fiber 19-core fiber ® few-core fibers multi-core fibers fiber Figure 5: Single-core fiber (SCF), few-core fibers (FCF), multi-core fibers (MCF). 4 Optical networks Research and development in the field of optical networks move towards mass broadband access in the vicinity of the end user and in the direction of highperformance optical connections between cities. The current three-segment network, comprising access, metropolitan and core networks, will in the future be substituted by a two-segment network that will include a combined metropolitan-access network and a core network. Around the world, as well as in Slovenia, there is a lot of interest in managing the fiber all the way to user's home - Fiber to the Home (FTTH) [20]. A lot of development work has been invested in network architectures that enable high bit rates and the long reach of fiber from the central office to the user's home. In the background of new services there is the need for FTTH that will enable transmission speeds of up to several Gbit/s. The entire telecommunications sector also strives to meet the requirements for bandwidth in access networks for the required price of mass economy. For this purpose a number of new passive optical network architectures have been developed. For many years, Passive Optical Network (PON), based on the technology of classification using Time Division Multiplex (TDM), has been known. In the process of increasing the speed from 2.5 Gbit/s to 10 Gbit/s TDM-PON still benefits from technical improvements. The wavelength remodulation optical access network schemes are promising technique to reduce the crosstalk from downstream signal [21]. It should be noted that researches in the field of PON systems with a wavelength selectivity (WDM-PON) have been less frequent in last few years, as the requirement for building, or at least upgrading, the optical network presents operators with an unwelcome obstacle. TWDM-PON (Time Wavelength Division Multiplexing PON) and even coherent PON are becoming more noticeable. Today, optical systems provide the backbone for the transmission of large amounts of data generated online, while using a packet, which is cheaper and more effective than any other type of transmission. The development is still in progress towards finding better and more expansive optical systems with high bandwidth, where the aim is to develop optical transmission systems that are suitable for the high-speed networking of continents, major cities and data centers. In this context, many researches focus on Software Defined Networks (SDN) [22], which will enable a transformation of the network without significant operator interference and in accordance with the demand for data transmission. SDN combine the optical network devices and the software that controls them. Programmable network interfaces enable a flexible optical network, which will have a new functionality such as dynamic control and virtualization. The optical physical level thereby obtains a certain degree of network intelligence, which will enable increased efficacy and the expansion of services. However, this also means more complexity in network operations, and therefore numerous studies in this area will be needed to optimize the algorithms of the design of optical networks [23] as well as the dynamic allocation of bandwidth [24]. Maybe this will allow the deletion of, or at least softening of, the boundaries between 180 B. Batagelj et al; Informacije Midem, Vol. 44, No. 3 (2014), 177 - 182 telecommunications operators and content providers, which demand greater flexibility. A significant proportion of all the optical connections are now also used to connect the data centers and within high-performance computers, because the compactness and capacity of optical communication has become indispensable to the design of large data-handling systems [25]. Data-center networks form a powerful backbone infrastructure for many existing internet service providers as well as the emerging providers of cloud computing. Many services, such as e-mail, on-line banking, software for business environments are happening in large data centers. The emerging cloud-computing model also encourages more and more innovation in the construction of extensive and efficient data centers. In typical data-center networks there are tens of thousands of servers that are connected to each other and are faced with technical challenges, such as high power consumption and the complexity of control in the transition to ever higher bit rates. It is from this perspective that optical communications represent a huge potential. Finally, we must not forget that new systems are created that directly integrate optical and wireless technologies, and which are in the future expected to exceed the limitations faced by current traditional wireless and fiber systems. An example is Radio-over-Fiber (RoF), wherein different "wireless" radio or even mm-wave signals are transmitted via fiber to a remote antenna or in the interiors of buildings [26]. In the case of a practical network with a large number of cellular end stations and very few central stations RoF transmission has a substantial advantage over current data transfer. In addition, RoF systems with a stabilized optical path and a constant signal delay in an optical fiber over long distances allow redundant and precise synchronization [27] also to telecommunications networks. Another example of optical and wireless technologies are optical wireless links [28], where a new generation of light-emitting diodes are used for the illumination and data transmission at home or in the office environment. If optical wireless link is done by using ordinary visible light emitting source, which is used for illumination, we talk about Visible Light Communication (VLC) [29]. VCL systems can be done as single color modulation or by using RGB-type light emitting source where simple WDM is implemented. We expect that low-cost, simple and high-speed VCL approaches will open door to various applications [30]. 5 Conclusion This article presents the major research challenges in optical communication technology towards 2020 and beyond. Like in the past, optical communications are expected to be promoted in order to develop their unparalleled speed in the future. Optical communications will also continue to be subject to continuous development and sophistication that will apparently overcome new boundaries. In fact, the competition for higher speeds, higher quality and enormous capacity continues to dictate an extensive development in the field of optical communications. In this respect, multilevel modulations, polarization multiplexing, coherent detection and digital processing have an important position as they give support to each other and complement each other. It may be that the introduction of a flexible network grid with WDM brought about a revolution in the field of the management of telecommunications traffic. The present, well-established scheme of General Multiprotocol Label Switching (GMPLS) will be replaced by the Software Defined Networking (SDN) of telecommunication traffic. This will ensure the easier implementation of programmable transponders, increase network flexibility and simplify its management. A glimpse into the future shows that a standard singlemode fiber will be withdrawn after three decades of successful application to a new type of optical fiber, like multimode optical fiber, which was abandoned in practice in the past. Future research efforts in the field of optical backbone networks will be aimed at tackling the problem of "fiber wall", with two trends from the field of spatial multiplexing in sight. Scientific research will focus on systems with multi-mode fiber, which allows optical MIMO transmission or few-core or even multi-core fibers. In the case of the proper management of cross-talk between individual cores, even a hybrid solution can be expected. In the past the very successful WDM technology required 10 years from first laboratory experiments to an implementation in practice. It is difficult to predict how much time will be needed for spatial multiplexing to become commercialized. Before a certain technology is applied in practice, it is necessary to make scientific discoveries and laboratory tests to engineering solutions and standardization harmonizations. Physical feasibility is not the only relevant factor for today's telecommunications operators, they are primarily looking for economic viability. An exponential increase in data traffic it is not easy to meet with a linear increase in the costs for building and operating the network, which gives a particularly difficult task to researchers in the field of optical communications. 180 B. Batagelj et al; Informacije Midem, Vol. 44, No. 3 (2014), 177 - 183 Acknowledgements This work was supported by the Slovenian Research Agency (ARRS) as part of the "Algorithms and optimisation procedures in telecommunications" programme. References 1. Matjaž Vidmar, "Optical-fiber communications: components and systems", Informacije MIDEM, 2001, year 31, No. 4, pp. 246-251. 2. M. Volk, J. Sterle, U. Sedlar, A. Kos, "An approach to modeling and control of QoE in next generation networks'; IEEE communications magazine, 2010, 15. Vol. 48, No. 8, pp. 126-135. 3. P. P. Mitra and J. B. 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Roberts, Lim Sang-Kyu "IEEE 802.15.7 visible light communication: modulation schemes and dimming support," IEEE Communications Magazine, vol. 50, no. 3, pp.72-82, March 2012. 30. S. Haruyama "Advances in visible light communication technologies," 38th European Conference and Exhibition on Optical Communications (ECOC), We.3.B.5, 16-20 Sept. 2012. Arrived: 10.4.2014 Accepted: 2.7.2014 180 Original scientific paper /midem Iournal of M Informacije | Journal of Microelectronics, Electronic Components and Materials Vol. 44, No. 3 (2014), 185 - 200 Development of Testing Method for Smart Substations with Prosumers Tarmo Korotko1,Ulo Merisalu1, Marek Magi2, Kristjan Peterson1, Elmo Pettai1 1Department of Electrical Engineering, Tallinn University of Technology, Tallinn, Estonia 2AS Harju Elekter Elektrotehnika, Keila, Estonia Abstract: The paper presents a concept of design and realization of a new testing method for distribution substations which form a microgrid with prosumers. The distribution substation acts as a service provider for distributed resource units in a microgrid and can be used for bidirectional energy exchange between prosumers, such as electric vehicles, battery pack energy storage devices and utility networks. Use of distribution substations equipped with energy storing and bidirectional energy exchange capability enable peak load shaving and demand response, which will reduce the need for new investments into building new power sources or electric power grids to meet peak demand. While the state of the art in the field analyses mainly different theoretical microgrid topologies and integration of unidirectional distributed energy resources, focus in this paper is on practical issues regarding bidirectional energy exchange, which can provide solutions to microgrid manufacturing enterprises. Protection and control functions of the low voltage part of the distribution substation must be tested prior to exploitation. The new testing method for substations includes both computer simulations and practical verifications for automated energy exchange. Simulation results can be used to define and optimize parameters for protection and control functions before constructing a real microgrid. Functions of an experimental microgrid application were simulated with MATLAB, which showed that several prosumers can be served simultaneously and effectively utilized for peak shaving of utility network loads. The results of the simulations were used to develop sample control algorithms and program modules for the substation controller of the experimental microgrid prototype. Keywords: bidirectional power flow, electric vehicles, microgrids, smart substation, substation testing methods Razvoj testnih metod za pametne postaje s proizvajalci-porabniki Izvleček: Članek predstavlja koncept načrtovanja in realizacije novih testnih metod za distribucijske postaje, ki oblikujejo mikro omrežje s proizvajalci-porabniki. Distribucijske postaje nastopajo kot ponudniki storitve za distribuirane enote virov v mikro omrežju in so lahko uporabljene za dvosmerni pretok energije med proizvajalci-porabniki, kot so električna vozila, hranilne enote in omrežja. Uporaba distribucijskih postaj s hranilniki energije omogoča rezanje vrhov porabe in odzivnost porabe, kar zmanjšuje potrebo po novih investicijah v nove proizvodne kapacitete, ki bi pokrivale vrhno porabo. Medtem ko se trenutne analize osredotočajo na različna teoretična mikro omrežja z enosmernim pretokom energije, ta članek opisuje praktične vidike dvosmernega pretoka energije in nudi rešitve proizvajalcem mikro omrežij. Pred uporabo distribucijskih postaj je potrebno testirati zaščite in kontrolne funkcije. Nove testne metode vključujejo računalniške simulacije in praktična preverjanja avtomatiziranega prenosa energije. Simulacijski rezultati so lahko uporabljeni za načrtovanje in optimizacijo zaščit in kontrolnih funkcij realnih mikro omrežij. Funkcije poskusnega omrežja so bile simulirane v MATLABu. Rezultati so pokazali, da se lahko oskrbuje več proizvajalcev-porabnikov hkrati, ki učinkovito omogočajo rezanje vrhov porabe energije. Rezultati so bili uporabljeni za razvoj kontrolnih algoritmov in programskih modulov za kontrolo postaj prototipnega mikro omrežja. Ključne besede: dvosmerni pretok energije, električna vozila, mikro omrežja, pametne postaje, testne metode * Corresponding Author's e-mail: elmo.pettai@ttu.ee i 1 Introduction Smart Grids and microgrids have attracted much attention due to the increasing awareness of energy conservation and environmental problems. Use of differ- ent prosumers (e.g. modern electric vehicles) and their effective integration into electric power grids depends on the technologies applied around distribution substations. The concept of a prosumer has two common meanings: a union of words of a producer with a con- 185 © MIDEM Society T. Korötko et al; Informacije Midem, Vol. 44, No. 3 (2014), 185 - 200 sumer or a professional consumer [1]. "Producing consumer" type of a prosumer either generates energy or consumes energy. A "professional consumer" is a well-educated, skilled consumer who commonly makes smart purchasing or selling decisions using additional information [1], [2]. Integration of prosumers to electric power grids is beneficial both to utility networks and prosumers. Prosumers can consume or generate electric energy and improve reliability of electric power supply (e.g. peak shaving, frequency regulation, voltage sags) by integrating renewable energy resources to electric power grids more efficiently. Prosumers can earn additional money with selling ancillary services to utility networks. In energy trading, the role of distribution substations will increase when different types of prosumers are connected to their output bays. In this paper, mainly electric vehicles (EV) with Li-Ion batteries or battery energy storage unit (BESU) applications are considered as prosumers. EVs with vehicle-to-grid (V2G) capability can be charged or discharged through substations. Other types of prosumers that could be connected with distribution substations are generators (e.g. photovoltaic), energy storage units (e.g. supercapacitors, electrolyser, flywheel) or different subsystems (e.g. other bidirectional distribution substations, microgrids or smart homes). The aim of this paper is to develop a new testing method for the next generation distribution substations (smart substations), which includes optimization of requirement validation algorithms and testing scenarios (defined according to the rules of testing functions), and selecting proper parameter values for protection and control functions. The method can be applied in the construction of new distribution substations (existing substations are typically designed for given purpose and do not have reserve space to expand to include energy storage). The developed method will be used in the construction of an experimental microgrid prototype. For transparency, example control topologies for the substation controller are presented. The paper is divided into ten main parts. Parts 2 and 3 describe the state of the art of smart substations and the proposed topology for smart distribution substation. Part 4 describes the state of the art of substation testing methodology. Part 5 introduces the new approach to substation development methodology. The substation organization and control architecture are firstly described and simulated according to the requirements, then saved for reuse in a repository. The results are practically verified during the experiments, using the experimental microgrid, and production cycle of the smart substation, and finally accepted by prosumers. General functional requirements and parameters are defined for distribution substations with prosumers (BESU and EV). Part 6 discusses the principles of the development and testing of control algorithms for the central controller of the distribution substation. Part 7 describes simulation of the control functions for bidirectional energy exchange between Li-Ion prosumers and the utility network with MATLAB Simulink. Parts eight and nine discuss the principles of testing novel distribution substations and the data required during the tests from prosumers. Finally, future studies and conclusions are presented. 2 State of the art of smart substations Several papers have addressed microgrid (distributed resource island systems according to IEEE 1547.4) architectures [3]-[8], V2G architectures [9], [10] and bidirectional converter topologies [11], [12]. However, research papers regarding testing of microgrids or presenting technical analysis about control functions for automated bidirectional energy exchange between distribution substations and several prosumers are scarce. Several papers have addressed the concept of virtual power plants (VPP) [13], [14], but no technical analyses show how the concept could be realized in real applications. Some reports address the testing of distributed resource units [15], PV [16] or V2G [17] applications and energy storage systems [18], [19], but not regarding prosumers in general. Some companies are using the term "smart substation" [20] to describe substations, which only monitor and transmit data to a microcontroller or outside server. These types of substations include no devices e.g. for suppressing harmonics [21] or providing uninterruptible power supply. Today's smart substations are either in the planning or in the prototype phase. Few projects can be found in field testing [22], [23]. It can be concluded that distribution substations for integrating prosumers to electric power grids are still in the development phase. IEEE 1547 standard presents mandatory requirements [24] for interconnection itself and testing. IEEE 1547 standard is not a design handbook or application guide. Thus, it is necessary to solve how to construct next generation distribution substations and how to test these substations. 186 T. Korötko et al; Informacije Midem, Vol. 44, No. 3 (2014), 185 - 200 3 Topology of distribution substation for integratingprosumers with utility network Transformer substations are part of the electric power system concentrated in a given place to transmit electric energy, distribute power and step up or down the voltage. Substations for medium voltage grids (typically 6-24 kV) transform 3-phase medium voltage to 3-phase AC low voltage (typically 400 V AC). State of the art distribution substations do not include bidirectional energy exchange capability between prosumers, LV side consumers and utility network. Next generation distribution substations could control electric power quality in a local area, maximize benefits for prosumers and owners of microgrids, integrate several prosumers to electric power grids (e.g. large EV parking lots). An example of a distribution substation topology for microgrids is presented in Fig. 1. The substation consists of a MV switchgear, a transformer and a low voltage (LV) switchgear (with switches, smart meters, contactors and power converters). The substation allows bidirectional energy exchange between all the prosumers and consumers that are connected with the integrated AC & DC bus, and transfer energy to the utility network. Prosumers are connected either to behind AC/DC power converter with a common DC bus or to a common AC bus. For every prosumer in the common DC bus separate protection and switching apparatuses are available at the DC side. The BESU in the substation is connected with the common DC bus. The DC bus voltage can float in the specified voltage range to increase the efficiency of energy conversion. For example, the BESU can support fast charging of EVs, provide backup energy and power capability for a utility network power outage. As the number of renewable energy sources is increasing in the grid (e.g. wind and solar energy), the balancing of excess generation sources and load demands can be controlled through the substation. This enables stabilization of the grid AC voltage and frequency [23]. The presented distribution substation topology is beneficial mainly to the future owners of a microgrid (e.g. manufacturing enterprises) for controlling energy storage and usage inside the microgrid. The master controller of the substation can be adjusted (e.g. scheduling, trading, optimization) according to the needs of the future owners of the microgrid. Figure 1: Topology of a distribution substation with an integrated AC & DC bus and prosumers for microgrid applications. 187 T. Korötko et al; Informacije Midem, Vol. 44, No. 3 (2014), 185 - 200 4 State of the art of substation testing methodology Ordinary substation testing is divided into factory routine tests and field tests [25]. Factory routine tests are divided into visual tests, mechanical tests and electrical tests. During visual factory tests, a general check is carried out to ensure the hardware is in accordance with project documentation, there exist no errors of assembly and all labels are correct. Also the absence of leakages will be checked. The tightness of all electrical and mechanical connections will be checked during factory tests. Electrical factory tests include: installation correctness (topology), wire insulation resistance and tests of protection and switching apparatus. Transformer parameters will also be checked [25]. A very important part is to test the substation under nominal current and voltage (separately).- Substation field tests are is similar to factory tests. During mechanical field tests, only the connections installed on site will be tested. Electrical field tests measure the insulation resistance of only those cables which are installed on site. Protection systems and switchgear will also be tested on site. The testing methodology details will vary in different countries and legislative areas. [26], [25], [27]. The information structure (testing requirements, testing methods, test cases, functional descriptions and other detailed views as source texts of control programs) of an ordinary substation can be represented using a requirements definition software e.g. Axiom (Fig. 2).. The collected information is used as reference during optimization, validation, and verification processes. The software allows parallel use of requirements information, simulation and verification data enable faster validation of microgrid projects. Independent certification of specified and tested microgrid modules, such as energy storage systems, can reduce installation time at customer site from weeks to hours, since certification transforms energy storage from a nascent technology into a safe plug-and-play appliance. After the integration of the system (substation, prosumers and utility), main use cases need to be tested. The verification process commonly demands rigorous testing and evaluation and is a time consuming and costly process. ¡Concur Axiom 2011 File Edit View Window Help tf: Artifact Explorer m (fy □331 ~ * v 1 fi) o = □ ■» 3 [485] Ordinary_Substation - a a [486] Test cases a si [487] Needs a s [488] System level a [489] Sub-system level 13) [490] AC Feeders .. | [496] Module Communications ß [498] AC Bus .. ; [499] Reactive Energy Compensation a a [500] Simulations a qi [501] System Simulation a 1_i [502] Sub-System Simulation hj [503] Module Simulation Q [504] Voltage Test a a [505] Substation a lui [506] System Test Cases a a [507] Communication & Control Sub-System > a [508] RTU a ëj [513] MV Switchgear Sub-System h ej [514] Transformer ej [515] Energy Meter a ej [5161 Feeder [517] Monitoring Supply Values [518] Supply Connections a □ [522] AC Bus Sub-System a u [523] Low Voltage AC Feeder q_i [524] Protection c_j [525] Energy Meter a [_j [526] Switchgear Q [527] LV & MV Switchgear Q [528] AC-Bus Sub-System Test Casel Q [543] System Test Casel - I n* Figure 2: Screenshot of testing requirements for ordinary distribution substation. 5 New approach to substation development methodology The substation testing methods, which were described in the previous part of this paper, are included in the construction of a new methodology. The new methodology is based on a software development methodology (X-model) and is visually represented in Fig. 3. During software testing, it is useful also to follow IEEE standard 829-2008 recommendations. The Requirements box (including e.g. application software functional requirements, substation user requirements, use cases etc.) is visualized in the left-upper part of Fig. 3. Documentation and repositoring is visualized in the left-lower part of Fig. 3. Prototype construction is visualized in the right-lower part of Fig. 3. Producing is visualized in the right-upper part of Fig. 3. Next chapters of the paper introduce some control aspects of the smart substation and their testing methods. 188 T. Korötko et al; Informacije Midem, Vol. 44, No. 3 (2014), 185 - 200 Functional requirements and parameters for distribution substations with prosumers are described in different standards (e.g. IEEE 1547.1 and VDE-AR-N 4105 [28]). IEEE 1 547.1 standard describes test procedures for equipment interconnecting distributed resources (e.g. prosumers) with electric power systems. In addition, the German standard VDE-AR-N 4105 provides for the improved network integration of decentralized power generation (in particular, inverter-based generators). During normal operation, the magnitude of the voltage change caused by the generating prosumers must in any connection point not exceed a value of 3 % compared to the voltage, when the generating prosumers were not connected. Voltage change of 3 % in the connection or disconnection with the distribution substation should not occur more frequently than once every 10 minutes. Figure 3: Substation testing methods in the developed methodology. VDE-AR-N 4105 specifies the disconnection of inverters connected to the LV network due to grid side disturbances [29]. When the voltage variation (undervoltage, overvoltage) exceeds the limits 80%U U) 5.2. Clearing time to abnormal frequency (f) 5.3. Clearing time unintentional islanding 5.4. Clearing time to simulated faults 5.5. Duration time for recovery (from abnormal area EPS values to nominal values) 5.6. Duration time for recovery (fault trip clearance) 5.7. Duration time to intentional islanding 5.8. Duration time to resynchronization 5.9. Duration time to blackstart 5.10. Duration time to peak shaving (target value, duration time and reference signal tracking error) 5.11. Ramp rate to active power production 5.12. Active power reduction gradient in frequency regulation 5.13. Duration time for VAR Management (target value, duration time, reference signal tracking error) 5.14. Duration time for harmonic suppression (target harmonic content, duration time and reference signal tracking error) 5.15. BESU roundtrip efficiency 5.16. BESU scheduling execution 5.17. Standby losses The key measured parameters in the test report are the efficiency values of the power converters, overall energy conversion efficiency and maximum continuous output power of the prosumers. Other important parameters are the stress values for prosumers (current, temperature), power quality measurements at the utility network side (accordance to IEC 61000), clearing times and duration times of different IEEE 1547.1 determined functions and ancillary tasks. From the measured parameters energy density and power density values can be calculated for prosumers and BESU. 9 Configurable values for prosumers While the main parameters of bays are defined in the designing phase, some of the bay parameters and ancillary services can be adjustable for the prosumers. Table 4 presents an example configurable value list for the bays of the distribution substation, which can be adjusted through HMI. These parameters include nominal, maximum and minimum values of different prosumer side parameters, price and scheduling options when to consume or produce (charge or discharge). Maximum values cannot exceed the limits of the selected devices. Minimum values, in most cases, are limited due to economic reasons or capabilities of the devices. Positions 1.1-1.7 in Table 4 can be inserted and simulated in the MATLAB simulation environment. Functional settings include different ancillary tasks, threshold values, time delays, time synchronization, BESU side preferences, event/history logging and status reporting/reading. Time delays should provide ride-through for low/high voltage and frequency values. Table 4: Configurable values for prosumers No. Description of values Value 1. Prosumer parameter values 1.1. Nominal/min/max voltage 1.2. Nominal/min/max current 1.3. Nominal/min/max charging power 1.4. Nominal/min/max discharging power 1.5. Maximum capacity (e.g. Ah) 1.6. Capability selection for bay: V2G 1.7. Maximum DOD (%) 1.8. Nominal/min/max temperature 1.9. Nominal/min/max prices for charging 1.10. Nominal/min/max prices for discharging 1.11. Scheduling preferences for prosumers 2. Functional settings 2.1. Peak shaving option activation 2.2. PQ preferences (VAR management or harmonic suppression) 2.3. Target cos 9 2.4. Individual harmonic compensation list 2.5. Load balancing activation 2.6. Non-islanding voltage and frequency range 2.7. Time delays for ride-through of abnormal conditions 2.8. Response times to abnormal conditions 2.9. Time synchronization 197 T. Korötko et al; Informacije Midem, Vol. 44, No. 3 (2014), 185 - 200 2.10. Scheduling preferences for BESU management 2.11. Event/history logging 2.12. Status reporting/reading 10 Future studies Tallinn University of Technology currently develops a smart substation development methodology and constructing an experimental microgrid that enables us to study energy flows and data communication. Parts of the smart substation development methodology that are not covered in this paper need future studies. The basic functions and operation modes (including protection algorithms) such as energy transmission from the power grid to the energy storing system, EV battery charging, balancing power loads and other functions have to be developed, tested and analysed. The simulated management and control algorithms have to be fine-tuned and will be transferred to the substation RTU (Fig. 7). Data will be collected for further analysis using an iConcur Axiom software. Primary goals are to analyse the quality of energy flow, energy efficiency and harmonic levels during EV charging through the microgrid, electromagnetic compatibility related issues and to improve and apply the testing methodology. The analysis will indicate needs for modifications to be made in the microgrid structure to optimize and improve the overall efficiency and power factor levels in the system to ensure the quality of electricity in accordance with international standards. Figure 7: View of an experimental setup with RTU devices for microgrid experimentations. Practical applications will show possible drawback areas in the communication between the devices, which will then have to be solved with different control algorithms. Future studies will focus on development of a prototype microgrid and on possibilities to transfer en- ergy to the common AC bus or to the power grid with synchronization related issues. Results from microgrid experiments will be published in future papers. Advice and warnings of issues to be aware of for smooth and accurate testing will be provided. 11 Conclusions This paper has reviewed a developed testing method for distribution substations which form a microgrid with prosumers. Topology of the substations has been presented with an integrated AC and DC bus. The topology enables providing simultaneously services to prosumers, consumers and utility network. It has been proven through simulations that an integrated AC and DC bus (Fig. 1) can be the main topology solution for integrating prosumers with different nominal voltages to electric power grids. Simulation results have verified that bidirectional energy exchange between the utility network and prosumers can be used for peak shaving of utility networks loads. In microgrid applications a distribution substation can be viewed as an energy router and it is the function of the substation's main controller in the higher level to determine when to utilize prosumers for ancillary services. This paper has presented a new testing protocol for distribution substations. The testing procedure includes running computer simulations, prototype tests (using laboratory tests for substation and microgrid integration), factory tests and onsite tests. Before constructing a real life substation, a smaller stand has to be constructed and examined. An experimental microgrid is being constructed at Tallinn University of Technology. Experiments with the microgrid will give vital data about charging/discharging algorithms and communication between the devices. These studies will enable us to construct a larger real life substation capable of supplying power to several prosumers that will be part of a microgrid or even a viable module of Smart Grid solutions. Acknowledgment This research work has been supported by European Social Fund (project "Doctoral School of Energy and Geotechnology II"), Estonian Ministry of Education and Research (project SF0140016s11), Estonian Science Foundation (Grant ETF9350), Estonian Archimedes Foundation (project AR10126), SmartGrids Era-Net (project GERA1) and European Regional Fund. 198 T. Korötko et al; Informacije Midem, Vol. 44, No. 3 (2014), 185 - 200 This research was supported by European Social Fund's Doctoral Studies and Internationalisation Programme DoRa conducted by Foundation Archimedes. References 1. M. Magi, K.Peterson, and E.Pettai, "Analysis of Protection and Control Functions of Low Voltage Part of Substation for Smart Grid Applications," in "Proceedings of 8th International Conference 2012 Electric Power Quality and Supply Reliability: 2012 Electric Power Quality and Supply Reliability" Tartu 2012, 2012, IEEE, pp. 297-304. 2. G. Ritzer, N. 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Arrived: 17.9.2013 Accepted: 8.5.2014 200 Original scientific paper Informacije ff MIDEM ímidem Journal of Journal of Microelectronics, Electronic Components and Materials Vol. 44, No. 3 (2014), 201 - 211 A Compact 3.1-5 GHz RC Feedback Low-Noise Amplifier Employing a Gain Enhancement Alena Djugova1, Jelena Radic1, Mirjana Videnovic-Misic1, Bernhard Goll2, Horst Zimmermann2 1Department for Power, Electronics and Communications Engineering, Faculty of Technical Sciences, University of Novi Sad, Novi Sad, Serbia 2Institute of Electrodynamics, Microwave and Circuit Engineering, Vienna University of Technology, Vienna, Austria Abstract: A low-noise amplifier (LNA) with main cascode amplifying stage utilizing a current-reuse transconductance-boosting technique is presented in this paper. This topology increases the effective transconductance, gm, of the input transistor and prevents a large voltage drop across the load resistor, thus reducing power consumption. The feedback topology made of source follower connected in series with a parallel RC network improves input impedance matching at high frequencies, while a gate peaking inductor inside the feedback loop enhances the amplifier bandwidth. The proposed LNA is implemented in UMC 0.18 ^m CMOS technology for a lower band of the ultra-wideband spectrum from 3.1 to 5 GHz. Measurements show a power gain (S21) of 9.7±0.45 dB with the 3-dB band from 1.1 to 5.57 GHz. The input return loss (Sn) is below -10 dB from 1 to 5 GHz, while the output return loss (S22) is less than -10 dB and the reverse isolation (S12) is better than -25.5 dB across the whole measured bandwidth, 1-7 GHz. The input-referred 1-dB compression point (P1dB) is -10.5 dBm at 3 GHz. The average noise figure (NF) obtained by post-layout simulations is 4.24 dB, with a minimum value of 4.05 dB at 4.92 GHz. By using only one inductor in the proposed design, the total chip area is greatly reduced to 0.913 mm2. The LNA core area occupies 0.353 mm2 and consumes 9.97 mW from a 1.8 V supply. Keywords: CMOS technology, radio frequency integrated circuits (RFIC), ultra-wideband (UWB), low-noise amplifier (LNA), current-reuse technique, resistive-feedback technique Kompakten 3.1-5 GHz RC povratni nizkošumni Izvleček: V članku je predstavljen nizkošumni ojačevalnik (LNA) z glavno kaskodno ojačevalno stopnjo s tehniko ponovne uporabe toka in povečanja transkonduktance. Uporabljena topologija povečuje efektivno transkonduktanco gm vhodnega tranzistorja in preprečuje velike napetostne padce na bremenskem uporu, kar zmanjšuje porabo. Povratna topologija serijsko povezanega sledilnega vira s paralelnim RC omrežjem izboljšuje ujemanje vhodne impedance pri visokih frekvencah, pri čemer gladilna tuljava vrat v povratni zanki povečuje pasovno širino ojačevalnika. Predlagan LNA je izveden v UMC 0.18^m CMOS tehnologiji za spodnji del ultra širokega pasu spektra od 3.1 do 5 GHz. Meritve izkazujejo donos moči (S21) 9.7±0.45 dB s pasovno širino 3-dB med 1.1 in 5.57 GHz. Povratne vhodne izgube (S,,) so pod -10 dB med 1 in 5 GHz, izhodne povratne izgube (S22) so pod -10 dB, povratna izolativnost (S12) boljša od -25.5 dB preko celotne pasovne širine 1-7 GHz. Vhodno naslovljena 1 dB točka kompresije (P1dB) je -10.5 dBm pri 3 GHz. Povprečna slika šuma simulacije po postavitivi je 4.24 dB. Pri uporabi le ene tuljave se površina čipa močno zmanjša na 0.913 mm2. Jedro LNA zaseda 0.353 mm2 in porabi 9.97 mW pri 1.8 V napajanju. Ključne besede: CMOS tehnologija, radio frekvenčna integrirana vezja (RFIC), ultra širok pas (UWB), nizkošumni ojačevalnik (LNA), uporovna povratna tehnika * Corresponding Author's e-mail: alenad@uns.ac.rs 201 © MIDEM Society S. S. Islam et al; Informacije Midem, Vol. 44, No. 3 (2014), 218 - 223 1 Introduction In 2002, the Federal Communication Commission (FCC) set up rules and regulations for ultra-wideband (UWB) technology and allocated 7.5 GHz of unlicensed spectrum (from 3.1 to 10.6 GHz) for commercial deployment [1]. An UWB signal is defined as any signal that occupies bandwidth greater than 500 MHz or whose fractional bandwidth exceeds 0.20, where fractional bandwidth is defined as the -10 dB bandwidth occupied by the signal divided by its center frequency. There are two different UWB approaches: multi-band (MB) UWB technology and impulse radio (IR) UWB. The former uses frequency hopping with orthogonal frequency division multiplexing (OFDM), where the available bandwidth of 7.5 GHz is divided into 528 MHz subbands, while the latter uses a series of short duration impulses, typically on the nanoseconds scale, utilizing a very wide bandwidth in the frequency domain. In MB-OFDM four band groups are defined, such as group A (3.1-4.9 GHz), B (4.9-6 GHz), C (6-8.1 GHz), and D (8.1-10.6 GHz), while the IR-UWB can be subcategorized in Time-Hopping (TH) UWB and Direct-Sequence (DS) UWB. The band of DS-UWB is separated into two parts, low band (3.1-4.9 GHz) and high band (6.2-9.7 GHz) [2]. The applications of UWB technology cover two areas: high data rate transmissions over short distances and low data rate communications with ranging and localization capabilities. The high data rate mode of UWB is related to short range wireless personal area networks (WPANs), while in the low data rate mode, UWB systems allow a new range of applications, including medical, military, vehicular radar, and security systems [3]. Generally, UWB shows a number of advantages compared to conventional narrowband applications, such as good time domain resolution, immunity to multipath propagation and interference, and potentially low complexity and low cost [4]. The FCC did not specify the type of the signal and modulation scheme of the UWB signal, but only the spectrum mask that the signal needs to meet with the emission limit restrictions issued for each specific UWB application. Power levels set for wireless communications are very low, i.e. -41.3 dBm/MHz, which allows coexistence of UWB and other conventional narrowband systems. Due to these strict power emission rules for the transmitter and the additional transmission path losses, the received signal power is typically three orders of magnitude smaller than that of narrowband systems [5]. This makes UWB receiver front-end design very challenging, particularly the design of the UWB low-noise amplifier. Since the overall noise figure of the receiver is mainly determined by the NF and the gain of the LNA, a sufficient gain and a low noise figure within a defined bandwidth is obligatory. In addition, to reduce return losses, adequate input and output matching is needed. All these requirements have to be fulfilled with low power consumption and within a wide bandwidth. Furthermore, for an UWB LNA designed for OFDM systems good power linearity is required to suppress adjacent channel interference. In the UWB impulse radio systems with more complex forms of modulation, e.g. BPSK (Binary Phase Shift Keying), good phase linearity (i.e., small group delay variation) is required instead. The frequency component of the transmitted signal should experience the same delay amount to be recovered properly. With increasing interest on commercial wideband integrated systems such as radars and wireless UWB and optical receivers, there is a demand for wideband complementary metal-oxide semiconductor (CMOS) amplifiers in the front-end section of such systems, since the CMOS process is more attractive and promising technology for high level of integration and system-on-chip (SOC) applications. CMOS devices offer the advantages of high fT and fmax as well as superior linearity and lower voltage operation, due to lower threshold voltages (CMOS VT vs. bipolar VBE). Bipolar junction transistors (BJT) offer the advantages of noise performance and an improved transconductance. The 1/f noise due to carrier trapping-detrapping at interface states and thermal noise due to gate and channel resistances are both significantly higher in CMOS than in BJTs. To reduce noise, very large CMOS devices and large operating current are often required. While the ultimate selection is based on system specifications, the noted differences between performance and economics also need to be considered. Often, the LNA's performance depends on on-chip inductors, which occupy a large area, making these topologies less attractive for low-cost application [6-8]. In this paper, an LNA with one main amplifying stage implemented in low cost UMC 0.18 pm CMOS technology is presented. Since inductors available in the used technology consume very large chip area, it was necessary to decrease their number. Only one peaking inductor inside the feedback loop is used in proposed design for enhancement of the amplifier's bandwidth. Furthermore, to overcome this technology constraint and to meet the requirements for LNA figures of merit (FoMs) some additional design techniques need to be used. To achieve wideband input impedance matching, the feedback network enhanced with a shunt capacitor. High gain in the whole operating band and low power consumption are obtained by merging resistive-feedback and current-reuse transconductance- 202 S. S. Islam et al; Informacije Midem, Vol. 44, No. 3 (2014), 218 - 223 boosting technique. Section 2 presents basic UWB LNA topologies, Section 3 gives insight into the feedback technique and Section 4 explains the proposed circuit topology. Section 5 reports the measurement results along with the simulation data. Section 6 contains the conclusions based on the performance of the proposed LNA. challenging to achieve very wide bandwidth with low NF. Moreover, due to strong dependence of voltage gain on the amplifying transistor's transconductance a large amount of current is required to achieve high gain. Therefore, to increase the transconductance and to reduce the power consumption a novel LNA circuit design needs to be proposed. 2 UWB LNA design techniques There are several wideband amplifier architectures that can be used in CMOS technology. The general block diagram of a distributed amplifier consists of transmission lines (realized using either co-planar waveguides or cascaded LC circuits) and gain stages distributed along them, that determine the overall gain of the amplifier. With this architecture impedance matching over a wide bandwidth can be achieved, but losses in the transmission lines limit the maximum gain. Moreover, it usually employs many spiral inductors that occupy a large chip area and consume considerable amounts of power, which makes them unsuitable for low power and low cost applications [6], [7]. The overall input reactance of the common-source amplifier with inductive source degeneration and extended with a multi section filter structure as input impedance matching circuit, is in resonance over the whole band. With this architecture low power consumption can be achieved, although noise performance will be degraded due to the LC network loss. In addition, a large silicon area is required, occupied by numerous integrated inductors [8]. The common-gate stage provides wideband input impedance matching with less design complexity and small area occupancy, for proper device size selection and bias current of the input transistor. However, the main disadvantage of this amplifier is a high noise figure as its relatively low transconductance value cannot provide low noise and high gain in the whole frequency range. To overcome this issue and discrepancy between input and noise matching, noise cancelling methods need to be used. Also, this type of amplifier is usually combined with an additional amplifying stage, which provides high-frequency gain and enhances the bandwidth [9]. Another area-saving solution is a common-source amplifier with resistive shunt-feedback technique [10]. With this approach wideband input impedance matching and flat gain can be obtained, though it is 3 Theory of resistive-feedback LNA The basic feedback topology, where the feedback resistor Rf, is implemented directly between the gate and drain of the input transistor, at low frequencies and under the impedance matched condition, exhibits a voltage gain of: A v out Vin RL - gmlRLRF RF Rl + Rf Z,„ (1) where R, is the load resistor, g , is transconductance of L ' =/m1 the input transistor M1, and Zn is the input impedance of this circuit given by: Vu rl + rf Z = ~ = m hn 1 + gm1RL Rl + Rf = 1 gm1RL g ml \ + Rl v L y (2) For a common-source (CS) amplifier employing the feedback resistor connected through a source follower, the voltage gain at low frequencies under the impedance matched condition is: A Vout _ g R _ RF -_ -Sm\rL — (3) and the input impedance is given by: Z,.„ = — = ■ 1 + gm 2 RF 1 Rl hn gm2 (l + gm1RL ) g ml RL (4) where gm2 represents the source follower's transcon-ductance. By using Av and Z.n approximate equations (1)-(4), for a voltage gain of 10 dB and input impedance matched to 50 Q, the feedback resistor RF in both cases is 158 Q. If gm1 = 50 mS, it follows from (2) and (4) that RL is 105 Q and 63 Q, respectively. By inserting a source follower in the feedback, the value of RL is reduced by 40% compared to the topology without it. The reduction in RL leads to a wider amplifier bandwidth, since a decrease 203 S. S. Islam et al; Informacije Midem, Vol. 44, No. 3 (2014), 218 - 223 in load resistance shifts the main pole, determined by the RC time constant of the CS output node, to higher frequencies. An additional benefit of a smaller load resistor value is the decrease in voltage drop across RL, which allows proper biasing of the amplifying transistor with high current demands. 4 UWB LNA circuit design The schematic of the proposed UWB LNA is shown in Fig.1. The input stage consists of an amplifying stage based on a cascode configuration, which is enhanced with resistive feedback connected through a source follower, and current-reuse M3-M5 block. The output stage is realized as a simple source follower that provides a broadband output impedance of 50 Q for measurement purposes. Input impedance matching is obtained by using a shunt feedback circuit, composed of source follower and RfCf parallel network. By using the source follower in the feedback path, the value of resistor RL is decreased, resulting in a smaller voltage drop across the load resistor and in an enhancement of frequency band. However, to achieve a high gain, the drain current of transistor M1 should be large, which makes the voltage drop still significant. By adding transistor M3 these two effects, RL voltage drop and enhancement of the M1 transconductance, are less coupled. In this way, the current through cascode transistor M2 is only part of the current of transistor M1 and the voltage drop across resistor RL is reduced, thus improving the voltage headroom. The amount of current through transistor M3 is controlled by the current mirror, formed by transistors M4 and M5 By connecting the gate of M3 to that of M1, the total transconductance of the input stage gm is enhanced and is given as the sum of the transconduct-ances of transistors M1 (NMOS) and M3 (PMOS). Consequently, the gain of the LNA increases. Additionally, by inserting the current-reuse stage, current through Rl decreases, thus the value of the resistor RL could be increased, which leads to higher amplifier gain and reduced noise figure value, but smaller bandwidth. For the basic feedback topology, the input impedance, given by (4), increases at high frequencies as the amplifier gain, gm1RL, drops due to parasitic capacitances. By adding a capacitor CF in parallel with feedback resistor Rf, the feedback impedance at high frequencies is reduced, the input impedance remains constant with frequency change and the broadband impedance matching is improved. Figure 1: Proposed 3.1-5 GHz CMOS UWB LNA. The total input node capacitance is approximately the sum of the capacitance CF and the gate capacitances of transistors M and M . Inductor L is connected to the 1 3 g gate of M1 and M3, as shown in Fig. 1, to resonate with these capacitances. Simulations show, that by increasing the inductance of Lg, gain peaking becomes more significant and the amplifier bandwidth enhances up to some value above which the bandwidth starts to decrease. The voltage signal at the gate of M1 (M3), and hence the transconductance, increases approaching the resonant frequency causing gain peaking. Additional increase in the gain value is obtained by adding a large value capacitor C2 at the source of transistor M3. With increasing frequency, the source impedance seen by transistor M3 decreases. This results in a larger transconductance gm3 value and consequently a higher LNA gain. Three simple bias circuits composed of resistors Rdn (n = 1, 2, 3) and transistors Mn (n = 4, 5, 7, 8, 10, 11) as current mirrors are used. To decrease the overall power consumption (PD), the width of the bias transistors is a small fraction of that of the corresponding amplifying transistors. A bias circuit using a modified Wilson current mirror sets the bias level for transistor M2, as shown in Fig. 1. Supply voltages V^, Vbias sf2, and ybias n are driven externally to provide an additional degree of measurement freedom and ability to compensate for process and voltage variations. In a final design these voltages can be set to VDD, which in turn decreases the number of pads and reduces chip area. In further analysis, influences of cascode stage and output buffer stage are omitted for simplicity. 4.1 Bandwidth enhancement with inductor L g For the LNA employing the RC feedback network connected through a source follower, without inductor Lg at the gate of the input transistor M1, the voltage gain of the amplifying stage is derived as: 204 S. S. Islam et al; Informacije Midem, Vol. 44, No. 3 (2014), 218 - 223 (Cm1 + gm3 )Rl Ai — 1 + jœ C \ gm6 1 + j®- c ëmrn gs6 I 1 + RL Zf 1 + j®{cgsi + Cgs3 )Rg (5) where Rg is the gate resistance, and ZF is the impedance determined by the capacitor Cf in parallel with the feedback resistor R, given by: Z R F F 1 + jœCpRp (6) If the value of resistor RF is of the same order as the value of resistor RL, Av1 can be simplified as: (gml + gm3 R gs1 + Cgs3Rg Av1 ~ - ybm/ \ - -(gmi + gm3 RL 1 + jMCgsl + Cgs3 )Rg (7) After inductor Lg is placed inside the feedback loop, the first amplifying stage voltage gain can be approximated as: (gm1 + gm3 R 1 + jrn C. gs 6 Sm6 1 + ja C gs 6 1 + L gm6 1 Z F 1 + ja(Cgs1 + Cgs3 )Rg - O)1 (Cgsl + Cgs3 )Lg (g) and after simplifying: A,, {gml + gm3 )Rl (Cgs1 + Cgs3 )Lg l ■ Rg 2 (C + C L + JVyg-6} lCgsl + Cgs3 Pg Lg (9) It can be seen that by inserting inductor Lg at the gate of transistor M1, the second-order circuit is obtained. From (9) follows that the frequency of the pair of complex-conjugate poles is rn0: Lg(( + Cgs3) and the Q-factor of a complex-conjugate pole pair is equal to: Q = Lg Rg \Cgii + C' gi3 (10) It can be seen that with this inductor Lg addition potential bandwidth enhancement can be achieved. Fig. 2 shows the simulation results of the voltage gain for different values of the gate inductor Lg. For an increasing value of inductor Lg, the bandwidth of the amplifier is improved. However, based on the expression for bandwidth in terms of Q-factor and resonant frequency, BW=a0/Q, exceeding a certain value of the inductance, the peaking becomes severe and the bandwidth starts to degrade. xw/oLg -©Lg=1nH *Lg=1.5nH » Lg=2nH T Lg=2.5nH 1.0 2.0 3.0 4.0 5.0 6.0 Frequency [GHz] Figure 2: Simulation results of the voltage gain for different L values. For the proposed design the optimum inductance value of L is found to be 2.3 nH. With this value the LNA covers g the frequency band from 3.1 to 5 GHz with 1.82 dB variation in S21 parameter. 4.2 Influence of capacitor CF on impedance matching The input impedance of the proposed LNA is given by: ZF + Z;„ = - 1 + jœCgs è RL gm6 + j^Cgs6 , 1 -a>2 (1 + Cgs3 )) 1 + A -v1 (11) where Cgj6 and gm6 are the gate-source capacitance and the transconductance of the source-follower transistor M6, respectively. The real and imaginary parts of the input impedance are examined, as shown in Figs. 3 and 4. From Figs. 3 and 4 it can be seen that the input impedance is determined by two equivalent subcircuits. At low frequencies the parallel resonant circuit with resonant frequency around 4 GHz shows the dominant effect on overall LNA impedance. Below this frequency the parallel RLC circuit has inductive and beyond it capacitive character, as shown in Fig. 4. From the expression for the output impedance of the source follower, given by 205 A. Djugova et al; Informacije Midem, Vol. 44, No. 3 (2014), 201 - 211 Figure 3: Simulation results of the real part of the input impedance for different CF values. Figure 4: Simulation results of the imaginary part of the input impedance for different CF values. 1 + ja>RLC L gs 6 -'out gm6 + jaC: gs 6 (12) it can be observed that by increasing the frequency, for 1/gm6 < RL, the impedance of the source follower shows inductive behavior. Based on the method presented in [11], this impedance can be represented as a parallel LR1 circuit connected in series with a resistor R2. The component values can be obtained as: This inductance forms a parallel resonant circuit together with the input capacitances Cg1 and Cg3. By adding capacitor CF in parallel to feedback resistor RF, the real component of the feedback impedance is reduced, given by (6), and comes closer to ideal 50 Q, as shown in Fig. 3. In addition based on (11) the capacitive effect is increased by Av1, which decreases the imaginary part closer to zero and, therefore, improve input impedance matching. Consequently, the parameter S11 is improved, as shown in Fig. 5. Figure 5: Simulation results of the S11 parameter for different C values. At high frequencies the influence of the serial resonant circuit, formed by inductor Lg and input capacitances of transistors M1 and M3, can be seen with resonant frequency at 6 GHz given by: (Cgsi + Cgs3 j (16) The influence of capacitor CF can be seen from Figs. 3 and 4, as a reduction of the input impedance real part. As before, capacitor CF decreases the feedback impedance for increasing frequency. The imaginary part of the input impedance will start to increase with frequency as a result of inductive behaviour. 4.3 Noise analysis L jœC; gs 6 g m6 Rl - R = Rl - Sm6 Ro g m6 (13) (14) (15) At high frequencies the noise is white, but at low frequencies the power spectral density is inversely proportional to the frequency. For transistors in the proposed LNA, it was found that the flicker noise (1/f) corner frequency is around 10 MHz, which is in accordance with the data given in Process Design Kit (PDK) for 0.18 ^m CMOS technology. From simulation it was found that 1/f noise of the LNA 1 1 1 206 S. S. Islam et al; Informacije Midem, Vol. 44, No. 3 (2014), 218 - 223 is mainly contributed by the input amplifying NMOS transistor M1 (14.55 %), with the W1 = 105 ^m. The noise factors of the most important thermal noise sources of the LNA, under input impedance matched condition and not considering a gain boosting stage, are derived as: F 1 RL gm1 RLRS Fr R F RF Fm M1 F Sm12 RL 2 RS 1 II gmiRs a 1 ' M 6 gm6 RS \2 K Sm1RL j Y a6 (17) (18) (19) (20) where F F WIICIC I RL I RF F„„ and F„c stand for the noise factors due to thermal noises of the load resistor RL, the feedback resistor RF, the amplifying transistor M1, and the source follower transistor M8, respectively. RS is the input source resistance, y is the MOSFET's thermal noise ratio, coefficient, and parameter a describes gm/gd0 where gd0 is the drain-source conductance at ze The total noise factor of the LNA is given as: F 1 + frl + frf + fm i + fm 6 (21) In the final LNA design, transistor M3 is added to enhance transconductance of input transistor M1, so lower value of noise factor can be achieved, as can be seen from (17)-(20). Consequently, a lower current flows through resistor RL providing some additional increase of Rl for the same voltage headroom, but a smaller bandwidth. During the design procedure trade-offs among power consumption, BW, input impedance matching and NF are performed. 5 Measurement and simulation results The proposed LNA circuit was designed and implemented in UMC 0.18 ^m twin-well CMOS technology with supply voltage VDD = 1.8 V. Simulations were obtained by using Cadence Design System with Spectre device models for all components. Post-layout simulations were performed using Assura, Cadence parasitic extractions tool. Transistor models are realized as multi-finger structures with 0.18 nm fixed gate length. The information about transistor widths is presented is Table 1, while values of passive components used in the circuit are given in Table 2. The bulks of all NMOS/PMOS transistors are connected to adequate reference voltages (GND in case of NMOS, and VDD in case of PMOS transistors), as shown in Fig. 1. Table 1: Transistors widths (W), L = 0.18 ^m. Devices Design values 21 x 5 13 x 5 11 x 5 9 x 5 7 x 5 5 x 5 Table 2: Values of passive circuit components. A die microphotograph of the proposed LNA circuit is shown in Fig. 6. Using only one inductor in the LNA design, the chip area is greatly reduced and measures 1.251x0.729 mm2. The active area, which excludes the pads, is approximately 0.919x0.384 mm2. Figure 6: Die microphotograph of the designed LNA. On-wafer probing under a 1.8 V supply voltage was performed to characterize the circuit performance of the LNA. The S-parameters were measured by using a Rohde & Schwarz ZVM Vector Network Analyzer. Fig. 7 shows the measured S11, S22, S21, and S12 parameters along with the simulation results. The measured input return loss (S11) is better than -10 dB for the frequency range from 1 to 5 GHz. The discrepancy between simulation and test results is mainly attributed to the additional parasitic effects. Over the entire frequency band of interest (3.1-5 GHz), the measured output return loss (S22) and the measured isolation (S12) remain below -11.52 dB and -36.07 dB, respectively. Fig. 7(c) shows the measured power gain (S21) versus frequency. The LNA achieves a high S21 of 9.7±0.45 dB over the 3.1-5 GHz band, and a 3-dB bandwidth from 1.11 to 5.57 GHz. 1 207 A. Djugova et al; Informacije Midem, Vol. 44, No. 3 (2014), 201 - 211 (a) (c) (d) Figure 7: Measurement and simulation results: (a) S11 parameter, (b) S22 parameter, (c) S21 parameter, (d) S12 parameter. The post-layout simulation result for the noise figure (NF) is shown in Fig. 8. It can be seen that the parameter value varies from 4.42 dB at 3.1 GHz to 4.06 dB at 5 GHz, with a minimum of 4.05 dB at 4.92 GHz. Figure 8: Post-layout simulation results: Noise figure (NF). The linearity of the proposed LNA was characterized measuring the 1-dB compression point using a Rohde& Schwarz Spectrum Analyzer FSP 30. An Hewlett Packard Network Analyzer 8753E, was used as an input source for varying the input power from -35 to 0 dBm. Due to its limitation in the frequency range, the linearity was measured only at 3 GHz. Measurements were performed for five LNA samples, and the results range from -9.5 to -11.5 dBm. Average result is plotted in Fig. 9. 10 5 D F m -S (j in Ï r> -10 LL =3 -lb Ü -20 -25 -30 -40 -35 -30 -25 -20 -15 Input power [dBm| Figure 9: Measured results: 1-dB compression point. The use of source-follower as LNA output stage leads to amplifier linearity degradation. The additional source follower in the feedback circuit further decreases 1-dB compression point. Despite this, proposed LNA meets the linearity requirements for the UWB amplifier design and shows better linearity performance than other re- 208 S. S. Islam et al; Informacije Midem, Vol. 44, No. 3 (2014), 218 - 223 ported amplifiers designed in 0.18 ^m technologies, which in addition use more complex circuit designs and increase costs. A common measure for phase linearity is the group delay, defined as the derivation of the transfer function S21 phase. The measured maximum group delay variation of the proposed LNA is ±34.59 ps across the 3.1-5 GHz band. By definition, a group delay variation of less than ±10 % of the bit period over the specified bandwidth is required to limit the generation of data dependent jitter [12]. This corresponds to maximum possible bit period of 345.9 s, i.e. bit rate up to 2.89 Gb/s. Thus, proposed LNA shows good phase linearity. The stability of the LNA is determined by the Rollett stability factor Kand the auxiliary stability factor B1. Minimum values of K and B1 are 3.66 and 0.94, respectively, hence unconditional stability requirements, given by K > 1 and B1 > 0 [13], are satisfied. In addition, the geometric stability factors of an amplifier are calculated. The |i (Mu) and (Mu-prime) factors are so called load stability factor and source stability factor, respectively. A two port network is unconditionally stable if | > 1 or > 1 [14], which means that with any load presented to the input or to the output of the device, the circuit will not become unstable. Furthermore, it can be said that larger values of | and imply greater stability. The stability factors of the proposed UWB LNA are calculated for all frequencies where the device is able to provide a gain larger that unity. The measured results are shown in Fig. 10. It can be noticed, that LNA circuit is stable for all frequencies, up to 10 GHz. The current consumption of the LNA was measured with a Keithley 2000 Multimeter. The LNA's total core current is 5.54 mA. Taking the currents drawn by the bias circuits and the output buffer into consideration, the LNA dissipates a total of 28.54 mW from a 1.8 V supply. To provide a certain level of controllability, separated pins are added in the design for supply voltages Vbias sf1, Vbhs sf2, and Vbias n. By decreasing these voltages (they are nominally set to 1.8 V), S-parameters and noise figure characteristics are affected. Post-layout simulation results are shown in Figs. 11-13. By changing the voltage Vbiasff1 from 1.8 to 1 V, the gate-source voltage of transistor M7, Vs7, and consequently the gate-source voltage of transistor M1, V, is increased. A higher Vs1 voltage results in a larger transconductance value a , and leads to S„ increase. -?m1 21 Additionally, due to higher output resistance the low-frequency gain increases and peaking is less pronounced. According to the (4), input impedance value decreases and diverges from 50 Q, which leads to a higher parameter S11 value. Furthermore, voltage Vbias sf1 variations result in minor S22 change and slight increase of NF. Decrease in voltage V, value influences tran- btas_n sistor M2 biasing point, thus decreasing the overall gain of the amplifier up to 1dB. As a result, input impedance value, given by (11), increases and S11 parameter degrades. The voltage Vbias sf2 variations affect output impedance matching. For Vbias sf2 = 1 V, the output resistances of transistors M9 and M10 increase. As a result, the LNA's output impedance changes, which leads to S22, and consequently, S21 decrease. Frequency [GHz] Figure 10: Measured results: Stability factors. Figure 11: Post-layout simulation results: Simulated Sn and S21 when varying Vbias sf1 in the range from 1 to 1.8 V, with 0.4 V step. Table 3 summarizes the measurement results of the proposed LNA compared to the FoMs of the recently published works. The design presented in this paper shows low variation of gain and noise in the 3.1-5 GHz band. As the main drawback of selected low cost 0.18 nm technology are inductors, that occupy a large area, by reducing their number to one, the chip area is greatly reduced and comparable to the area occupied by other designs, implemented in different 0.18 ^m technolo- 209 S. S. Islam et al; Informacije Midem, Vol. 44, No. 3 (2014), 218 - 223 "T S21, Vbias_n=1V * S21, Vbias_n=1.4V * S21. Vbias_n=1.8V -S11. Vbias_n=1V + S11, Vbias_n=1 4V « S11. Vbias_n=1,8V 15.0- -20.0 I . . . . I . . .......| , , , , | , , . , | , ....... 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 Frequency [GHz] Figure 12: Post-layout simulation results: Simulated Sn and S21 when varying Vbias n in the range from 1 to 1.8 V, with 0.4 V step. X S21. Vbias_sf2=1V * S21, Vbias_sE2=1,4V 1 S21, Vbias_sf2=1,8V S22, Vbias_sf2=1 V + S22, Vbias_s£2=1.4V « S22, Vbias_sl2=1.8V 15.0- -20.01 .... | .... | .... | .... | .... | .... | ... . 0 1.0 2.0 3.0 4,0 5.0 6.0 7.0 Frequency [GHz] Figure 13: Post-layout simulation results: Simulated S22 and S21 when varying Vbias f22 in the range from 1 to 1.8 V, with 0.4 V step. gies. For example, the LNA topologies presented in [15] and [16] use four inductors, in [17] and [18] three, and in [19] five. Consequently, the small number of inductors in LNA design reduces the degrees of freedom, so additional techniques need to be used to meet requirements for all LNA FoMs. From Table 3 follows that parameters achieved in the presented paper are com- parable to the results given by other authors, making the proposed architecture suitable for UWB wireless applications. 6 Conclusion The proposed LNA is designed for lower UWB band from 3.1 to 5 GHz. By utilizing only one inductor placed inside the feedback loop, a compact layout design in low cost UMC 0.18 ^m CMOS technology is presented. Therefore, proposed design is comparable with the other reported designs implemented in different technologies. To meet other LNA requirements different techniques are used. The amplifier employs the feedback resistor connected through a source follower, which leads to a wider operating frequency range and improved voltage headroom of the amplifier. In addition, the drain current of the cascode transistor is reduced by adding the PMOS transistor to form a current-reuse topology with the amplifying transistor. Consequently, the effective transconductance is enhanced, leading to high gain values. By adding feedback capacitor in parallel to feedback resistor, the input impedance is kept constant with frequency and wideband input impedance matching is obtained. The simulation and measurement results show low gain and noise variations in the band of interest, from 3.1 to 5 GHz, while satisfying the input and the output matching conditions and the power consumption requirements. Good power and phase linearity performances make the proposed LNA suitable for both OFDM and UWB impulse radio system applications. Acknowledgments This work was supported in part by the Ministry of Education, Science and Technological Development, Republic of Serbia (the project contract numbers III-43008 and TR-32016). Ref. BW [GHz] S21 [dB] S„ [dB] S22 [dB] NF [dB] P1dB [dBm] PD [mA@V] Die area [mm2] /15/ 3-5 12.7±0.4 <-13 <-10 3.2-5.5 -11.7 9.6*@ 1.8 0.7 /16/ 3-4.8 13.5±1.5 <-10 / 3.5-6.8 -18 3.7*@ 0.9-1.8 0.76 /17/ 3-7 10±1.5 <-11 <-11 3.5-4 / 5 @ 1.8 0.59 /18/ 0.6-6.2 10.1±1.5 <-21 <-22 5.3-5.8 -13 5.6 @ 1.5 0.8 /19/ 2-6 12.5±0.5 <-10 / 3-3.7 / 8.3 @ 1.8 0.98 This work 3.1-5 9.7±0.4 <-10 <-11 4-4.4** -9.5 5.5*@ 1.8 0.91 *LNA core **simulated Table 3: Performance comparison of LNAs implemented in 0.18 ^m technologies. 210 S. S. Islam et al; Informacije Midem, Vol. 44, No. 3 (2014), 218 - 223 References 1. First report and order: Revision of part 15 of the commission's rules regarding ultra-wideband transmission systems, Federal Communications Commission (FCC), Washington, DC, ET Docket 98-153, February 14, 2002. 2. H. Nikookar, and R. Prasad, "Introduction to ultra wideband for wireless communications signals and communication technology", Springer, 2009. 3. D. Porcino and W. Hirt, "Ultra-wideband radio technology: potential and challenges ahead", IEEE Communications Magazine, vol. 41, no. 7, pp. 66-74, 2003. 4. M. Ghavami, L. B. Michael, and R. Kohno, "Ultra wideband signals and systems in communication engineering", John Wiley and Sons Ltd, 2004. 5. D. Barras, F. Ellinger, and H. Jackel, "A comparison between ultra-wide-band and narrow-band transceivers", Proceedings of TRLabs Wireless 2002, pp. 211-214, 2002. 6. K. Entesari, A. R. Tavakoli, and A. Helmy, "CMOS distributed amplifiers with extended flat bandwidth and improved input matching using gate line with coupled inductors", IEEE Transactions on Microwave Theory and Techniques, vol. 57, no. 12, pp. 2862-2871, 2009. 7. A. Hajimiri, and Y.-J. Wang, "A compact low-noise weighted distributed amplifier in CMOS", Proceedings of IEEE International Solid-State Conference, San Francisco, CA, pp. 220-221, 2009. 8. Y. J. Lin, S. S. H. Hsu, J. D. Jin, and C. Y. Chan, "A 3.1-10.6 GHz ultra-wideband CMOS low noise amplifier with current-reused technique", IEEE Microwave Wireless Component Letters, vol. 17, no. 3, pp. 232-234, 2007. 9. C.-F. Liao, and A.-I. Liu, "An ultra-wide-band 0.4-10-GHz LNA in 0.18-pm CMOS", IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 3, pp. 217-221, 2007. 10 J. Jung, T. Yun, and J. Choi, "Ultra-wideband low noise amplifier using a cascode feedback topology", Microwave and Optical Technology Letters, vol. 48, pp. 1102-1104, 2006. 11. B. Razavi, "Design of Analog CMOS Integrated Circuits", New York, McGraw-Hill, 2001. 12. E. Sackinger, "Broadband circuits for optical fiber communication", New Jersey: John Wiley & Sons, 2005. 13. G. Gonzalez, "Microwave Transistor Amplifiers: Analysis and Design", Prentice Hall, 1984. 14 D. M. Pozar, "Microwave Engineering", 2nd edition, New York: John Wiley & Sons, 1998. 15. F. Lisong, H. Lu, B. Xuefei, and X. Tianzuo, "A 0.18 pm CMOS 3-5 GHz broadband flat gain low noise amplifier"", Journal of Semiconductor, vol. 31, no. 2, pp. 025003-1-025003-7, 2010. 16. C. P. Liang, P. Z. Rao, T. J. Huang, and S. J. Chung, "Analysis and design of two low-power ultrawideband CMOS low-noise amplifiers with outband rejection"", IEEE Transactions on Microwave Theory and Techniques, vol. 58, no. 2, pp. 277286, 2010. 17. A. I. A. Galal, R. K. Pokharel, H. Kanaya, and K. Yoshida, "3-7 GHz low power wide-band common gate low noise amplifier in 0.18pm CMOS process", Proceedings of Asia-Pacific Microwave Conference, Yokohama, pp. 342-345, 2010. 18. K.-H. Chien, and H.-K. Chiou, "A 0.6-6.2 GHz wideband LNA using resistive feedback and gate inductive peaking techniques for multiple standards application", Proceedings of Asia-Pacific Microwave Conference, Seoul, pp. 688-690, 2013. 19. W.-H. Hung, K.-T. Lin, J.-Y. Hsieh, and S.-S. Lu, "A 2-6 GHz broadband CMOS low-noise amplifier with current reuse topology utilizing a noise-shaping technique", IEEE International Symposium on Circuits and Systems, Rio de Janeiro, pp. 1291-1294, 2011. Arrived: 01. 03. 2014 Accepted: 13. 05. 2014 211 Original scientific paper /midem lournal of M Informacije | Journal of Microelectronics, Electronic Components and Materials Vol. 44, No. 3 (2014), 212 - 217 Printed Circular Patch Wideband Antenna for Wireless Communication T. Alam1, M. R. I. Faruque1, M. T. Islam2 1Space Science Centre (ANGKASA), Universiti Kebangsaan Malaysia, Bangi, Selangor, Malaysia. 2Department of Electrical Electronic & System Engineering, Universiti Kebangsaan Malaysia, Bangi, Selangor, Malaysia. Abstract: This letter presents a new wideband, printed, microstrip-fed, circular patch antenna for multifunctional wireless communication applications. The commercially available CST Microwave Studio software package, which is based on finite difference time-domain (FDTD) analyses, has been adopted in this study. The experimentally determined impedance bandwidths are 2.2 GHz (1.75 GHz to 4 GHz) and 750 MHz (4.15GHz to 4.90 GHz), which cover the GSM-1800, GSM-1900, UMTS, Bluetooth (2400-2800) MHz, WLAN (2400-2485) MHz, WiMAX (2500-2690) MHz and WiMAX (3400-3600) MHz frequency bands. The experimental measurements taken using the proposed antenna are in good agreement with the computational results. Keywords: Antenna, circular patch, wideband, wireless communication. Tiskana krožna krpičasta širokopasovna antena za brezvrvične zveze Izvleček: Članek opisuje novo širokopasovno tiskano mikro trakasto krpično krožno anteno za večfunkcijsko brezžično komunikacijo. Za potrebe študije je bilo predelano komercialno programsko orodje CST Microwave Studio, ki temelji na metodi končnih razlik v časovnem prostoru. Eksperimentalno določene impedančne pasovne širine so 2.2 GHz (od 1.75 GHz do 4 GHz) in 750 MHz (od 4.15GHz do 4.90 GHz), ki pokrivajo frekvenčne pasove GSM-1800, GSM-1900, UMTS, Bluetooth (2400-2800) MHz, WLAN (2400-2485) MHz, WiMAX (2500-2690) MHz in WiMAX (3400-3600) MHz. Eksperimentalni rezultati so v dobrem ujemanju s simulacijami. Ključne besede: Antena, krožna krpičasta antena, široki pas, brezžična povezava * Corresponding Author's e-mail: touhid13@yahoo.com 1 Introduction In recent years, microstrip-fed circular patch antennas have become popular in antenna researcher because of their numerous benefits such as cost effectiveness, wideband abilities, simple fabrication and improved performance. Moreover, Improvements in wireless communications have introduced tremendous demands in the antenna technology. .It's withal the paved the way for extensive utilization of mobile phones in modern society resulting in mounting concerns circumventing its inimical radiation [1-3]. Furthermore, this type of antenna satisfies the challenges of connectivity with both mobile and fixed devices with greater user experience and also overcomes the limitation of narrow impedance and axial ratio bandwidth. Researchers have analysed various types of circular antennas for different operating frequencies [4-7]. Various techniques, such as the annular ring microstrip patch antenna using a prolonged ear [8], have been used to obtain the desired operating frequency. Moreover, to achieve wideband abilities, a number of additional techniques were studied. For example, a dual rectangular wire loop configuration above an infinite ground plane was designed in [9]; an L-probe patch antenna was proposed in [10]; a magneto-dielectric resonator antenna was proposed in [11] and electromagnetically coupled, two-layer substrate was used in [12]. Furthermore, by adding one or more parasitic elements, a wide bandwidth of up to 40% axial-ratio bandwidth was achieved in [13]. A fan-shaped, parasitic patch with 212 © MIDEM Society T. Alam et al; Informacije Midem, Vol. 44, No. 3 (2014), 212 - 217 an annular-ring patch antenna was investigated in [14], where a bandwidth of 2.3% was achieved, and the effect of parasitic elements was investigated in [15-18]. A number of studies have been conducted on slot antennas as well [19-24], where CP antennas have achieved 4% to 25% axial-ratio bandwidths. In this article, a new wideband, circular polarized, printed monopole antenna is proposed that can be operated in the GSM, UMTS, WLAN and WiMAX frequency bands with improved gains. The concept of adding a parasitic element and cutting slot are investigated and compared. The experimental results of the antenna exhibit continuous wide bands from 1.75 GHz to 4 GHz and from 4.15 GHz to 4.9 GHz. 2 Antenna geometry The geometries of the proposed and fabricated antenna prototype are shown in Fig. 1 and Fig. 2, respectively. The length of the printed circuit board is Lg = 50 mm and the width is Wg = 62.9 mm. The antenna consists of two main parts: the circular patch with parasitic elements and the defected ground. The radius of the circular radiator is 12.5 mm. The width and length of the feed line are Wf and Lf, respectively, which has an input impedance of 50 Q. A parasitic element is attached to the patch to change the surface current's path. The dimensions of the proposed antenna are shown in Table I. Table. 1: The proposed antenna specifications (in mm). Parameters Values (mm) Parameters Values (mm) Wg 50.00 L1 28 Lg 62.9 L2 15 Lf 25.5 W1 1.06 Wf 2.89 W2 6.5 R 12.5 L3 15 Ls 12.3 L4 21.4 Ws 1.06 R1 10 Lp 14.5 R2 11 Wp 2.00 3 Parametric studies 31 Effect of parasitic elements and slots The best performances of the proposed antenna are obtained by adding different types of parasitic elements and cutting slots. Parasitic elements and cut- Figure 1: Design layout of the proposed antenna: (a) Top View and (b) Bottom view. Figure 2: Photograph of the fabricated proposed antenna. ting slots are added to change the current flow and attain better radiation profiles. The proposed antenna has been designed using optimally sized parasitic elements. Initially, analyses were performed with one conventional, circular patch microstrip monopole antenna. Several steps were subsequently followed. In the first step, a 15 mm x 3 mm copper element was added to the ground plane, which resulted in a smaller reflection coefficient. In the second step, a 15 mm x 6.5 mm copper element and an ellipse were added to the ground plane together with first element and analysed. In the third step, the 15 mm x 50 mm copper elements were added in the upper side of the ground plane, which resulted in improved results relative to the previous step. In the fourth step, a slot was cut from the upper portion of the ground. In the fifth step, a parasitic element was added to the patch, which resulted in improved results. Finally, a slot was cut from the patch, which resulted in 213 T. Alam et al; Informacije Midem, Vol. 44, No. 3 (2014), 212 - 217 the desired results. The reflection coefficient values of the different slots are compared in Fig. 3. Table. 2: Material properties of different materials Figure 3: Effect on the reflection coefficient from adding parasitic elements and slotting. 3.2 Substrate Height Fig. 4 shows the simulation result of the reflection coefficient of the proposed antenna for FR4 substrate thicknesses of 0.254 mm, 0.500 mm, 1 mm and 1.6 mm. From Fig. 4, it is clearly observed that the best performance of the proposed antenna was found using a thickness of 1.6 mm. Because the thicker substrate increases the radiated power and improve impedance bandwidth. Figure 4: Reflection coefficient for different values of substrate thickness. 3.3 Different Substrates The reflection coefficients of the antenna using different types of substrate materials are shown in Fig. 5. From Fig. 5, we see that the substrate material is an important parameter for the antenna design. The different materials properties are shown in Table II. Substrate Name Permittivity Loss Tangent Substrate thickness RT 5880 2.2 0.0015 1.6 RT 5870 2.33 0.0012 1.6 RT 6010 10.2 0.002 1.6 FR4 4.6 0.02 1.6 Bio plastic 15 0.002 1.6 Figure 5: Reflection coefficient for different types of substrates. Figure 6: Reflection coefficient for different values of the feed line width 3.4 Feed Line Width Fig. 6 shows the simulated reflection coefficient values of the proposed antenna for different feed line widths (Wf). The optimum value of Wf for the desired frequency band was determined to be 2.89 mm. which indicates that the input impedance matches smoothly at 2.89 mm feed line width. 214 T. Alam et al; Informacije Midem, Vol. 44, No. 3 (2014), 212 - 217 Figure 7: Reflection coefficient for different values of patch radius . 4.9 \\ L£5 GHZ / J j ~ ~ 'y \ T\ [ 1 ' \ 1 1 1 \ VN S { N/ \ / \K 1 \ / 11 V 11 (1 ■ ■i -Measured S » i i I I ----Simulated St l i i i Frequency (GHz) Figure 8: Simulated and measured reflection coefficient value of the proposed antenna. 3.5 Patch Radius The optimized patch radius for the proposed antenna is 12.5 mm as seen in Fig. 7. The frequency band from 3.9 GHz to 4.5 GHz can be controlled by regulating the patch radius as seen in Fig. 7. 4 Results and discussions The design and simulation of the proposed antenna have been performed using the commercially available CST Microwave Studio and High Frequency Structural Simulator (HFSS) software package. The prototype of the proposed antenna has been fabricated and measured. The reflection coefficient measurement has been performed using an Agilent TE8362C network analyzer. The simulated and the experimental reflection coefficients were compared as seen in Fig. 8. It is seen from Fig. 8 that the simulated peak resonant was achieved at 1.95 GHz and 3.16 GHz. Moreover, two wide band-widths of 1.65 GHz and 550 MHz were seen from 1.62 GHZ to 4.45 GHz. In the experiment, two wide band-widths of 2.2 GHz from 1.75 GHz to 4 GHz and 750 MHz from 4.15 GHz to 4.9 GHz were found. The surface current distribution was observed for different frequencies as seen in Fig. 9. In addition, the simulated E-plane and H-plane radiation pattern at 1.8 GHz, 2.1 GHz, 2.4 GHz, 2.7 GHz, and 4.5 GHz are shown in Fig. 10. From Fig. 10, it is observed that the proposed antenna shows a directional radiation pattern for E-plane and H-plane radiation pattern. At higher frequency there are some distortion in the radiation pattern.The main reason of this distortion is the excitation of higher-order current mode. The dimensions of the wideband wireless antenna to cover the GSM 1800, GSM 1900, GSM 2100, UMTS, Bluetooth (2400-2800 MHz), WLAN (2400-2485 MHz), WiMAX (2500-2690 MHz), and WiMAX (3400-3600 MHz) frequency bands are quiet larger. In [25], the authors achieved a wide bandwidth of 1.37 GHz from 1.04 to 2.41 GHz, and the antenna ground plane dimension was 300 mm x 300 mm. In [26], the authors presented a wideband, circularly polarized antenna; however, their antenna ground plane radius is larger than the proposed antenna, which is 150 mm. Conversely, the dimensions of the proposed antenna were 50 mm x 62.9 mm, which achieved a wide bandwidth of 2.2 GHz and 750 MHz from 1.75 GHz to 4 GHz and from 4.15 GHz to 4.9 GHz, respectively. 5 Conclusion A simple, low-cost, wideband, circular patch microstrip-fed monopole antenna was presented. The presented antenna has a wide bandwidth of 2.2 GHz from 1.75 GHz to 4 GHz and 750 MHz from 4.15 GHz to 4.9 GHz, respectively. The proposed antenna can cover the GSM 1800, GSM 1900, UMTS, Bluetooth, WLAN and WiMAX frequency bands. In this study, it was observed that the proposed antenna can play an important role in current wireless communication systems. References 1. M. R. I. Faruque, M. T. Islam, and N. Misran, "Electromagnetic (EM) absorption reduction in a muscle cube with metamaterial attachment," Medical engineering & physics, vol. 33, pp. 646-652, 2011. 2. M. T. Islam, H. Z. Abidin, M. R. I. Faruque, and N. Misran, "Analysis of materials effects on radio fre- 215 T. Korötko et al; Informacije Midem, Vol. 44, No. 3 (2014), 185 - 200 E-plane H-plane (c) (d) I A/m 2.0000e+001 1.7889e+001 1.5778e+001 1.3667e+001 1.1556e+001 9.4444e+000 7.3333e+000 5.2222e+000 3.lllle+000 1.00006+000 Figure 9: Simulated surface current at (a) 1.8 GHz, (b) 1.9 GHz, (c) 2.1 GHz, (d) 2.4 GHz, (e) 3.6 GHz and (f) 4.5 GHz Figure 10: Radiation Pattern (a) at 1.8 GHz, (b) 2.1 GHz, (c) 2.4 GHz, (d) 2.7 GHz and (e) 4.5 GHz quency electromagnetic fields in human head," Progress In Electromagnetics Research, vol. 128, 2012. 3. M. R. I. Faruque, M. T. Islam, and N. Misran, "Evaluation of specific absorption rate (SAR) reduction for PIFA antenna using metamaterials," Frequenz, vol. 64, pp. 144-149, 2010. 216 T. Alam et al; Informacije Midem, Vol. 44, No. 3 (2014), 212 - 217 4. S. Ahdi Rezaeieh and M. Kartal, "A new triple band circularly polarized square slot antenna design with crooked T and F-shape strips for wireless applications," Progress In Electromagnetics Research, vol. 121, pp. 1-18, 2011. 5. N. P. Agrawall, G. Kumar, and K. P. Ray, "Wide-band planar monopole antennas," Antennas and Propagation, IEEE Transactions on, vol. 46, pp. 294-295, 1998. 6. J. Pourahmadazar and S. Mohammadi, "Compact circularly-polarised slot antenna for UWB applications," Electronics letters, vol. 47, pp. 837-838, 2011. 7. M. M. Islam, M. T. Islam, and M. R. I. Faruque, "Dual-Band Operation of a Microstrip Patch Antenna on a Duroid 5870 Substrate for Ku-and K-Bands," The Scientific World Journal, vol. 2013, 2013. 8. A. K. Bhattacharyya and L. Shafai, "A wider band microstrip antenna for circular polarization," Antennas and Propagation, IEEE Transactions on, vol. 36, pp. 157-163, 1988. 9. M. Sumi, K. Hirasawa, and S. Song, "Two rectangular loops fed in series for broadband circular polarization and impedance matching," Antennas and Propagation, IEEE Transactions on, vol. 52, pp. 551-554, 2004. 10. K. L. Lau and K. M. Luk, "A novel wide-band circularly polarized patch antenna based on L-probe and aperture-coupling techniques," Antennas and Propagation, IEEE Transactions on, vol. 53, pp. 577582, 2005. 11. A. Buerkle and K. Sarabandi, "A wide-band, circularly polarized, magnetodielectric resonator antenna," Antennas and Propagation, IEEE Transactions on, vol. 53, pp. 3436-3442, 2005. 12. S. Gao, Q. Yi, and A. Sambell, "Low-Cost Broadband Circularly Polarized Printed Antennas and Array," Antennas and Propagation Magazine, IEEE, vol. 49, pp. 57-64, 2007. 13. L. RongLin, G. DeJean, J. Laskar, and M. M. Tentz-eris, "Investigation of circularly polarized loop antennas with a parasitic element for bandwidth enhancement," Antennas and Propagation, IEEE Transactions on, vol. 53, pp. 3930-3939, 2005. 14. L. Yi-Fang, C. Hua-Ming, and L. Shih-Chieh, "A New Coupling Mechanism for Circularly Polarized Annular-Ring Patch Antenna," Antennas and Propagation, IEEE Transactions on, vol. 56, pp. 1116, 2008. 15. J. S. Meiguni, M. Kamyab, and A. Hosseinbeig, "Effect of parasitic elements on spherical probe-fed antennas," in Electrical Engineering (ICEE), 2013 21st Iranian Conference on, 2013, pp. 1-4. 16. A. Tsien Ming and L. Kwai-man, "Effect of parasitic element on the characteristics of microstrip antenna," Antennas and Propagation, IEEE Transactions on, vol. 39, pp. 1247-1251, 1991. 17. Y. Xue-Song, W. Bing-Zhong, Y. Sai Ho, X. Quan, and M. Kim-Fung, "Circularly Polarized Reconfigurable Crossed-Yagi Patch Antenna," Antennas and Propagation Magazine, IEEE, vol. 53, pp. 65-80, 2011. 18. K. S. Chin, W. Jiang, W. Che, C. C. Chang, and H. Jin, "Wideband LTCC 60-GHz Antenna Array With a Dual-Resonant Slot and Patch Structure," Antennas and Propagation, IEEE Transactions on, vol. 62, pp. 174-182, 2014. 19. R. L. Fante, "The effect of an offset impedance sheet on the admittance of a slot antenna," Antennas and Propagation, IEEE Transactions on, vol. 15, pp. 516-518, 1967. 20. H. V. Prabhakar, U. K. Kummuri, R. M. Yadahalli, and V. Munnappa, "Effect of various meandering slots in rectangular microstrip antenna ground plane for compact broadband operation," Electronics Letters, vol. 43, pp. 848-850, 2007. 21. Z. Boyu and S. Zhongxiang, "Effect of a finite ground plane on microstrip-fed cavity-backed slot antennas," Antennas and Propagation, IEEE Transactions on, vol. 53, pp. 862-865, 2005. 22. C. Rowell and E. Y. Lam, "Band-stop filter effect of multiple slots in mobile phone antennas," in Antennas and Propagation Society International Symposium (APSURSI), 2012 IEEE, 2012, pp. 1-2. 23. R. Jeen-Sheen, "The design of a squarer-ring slot antenna for circular polarization," Antennas and Propagation, IEEE Transactions on, vol. 53, pp. 1967-1972, 2005. 24. C. C. Chou, K. H. Lin, and H. L. Su, "Broadband circularly polarised crosspatch- loaded square slot antenna," Electronics Letters, vol. 43, pp. 485-486, 2007. 25. B. Lei, G. Yong-Xin, L. C. Ong, and X.-q. Shi, "Wideband Circularly-Polarized Patch Antenna," Antennas and Propagation, IEEE Transactions on, vol. 54, pp. 2682-2686, 2006. 26. Z. Zhi-Ya, L. Neng-Wu, Z. Jia-Yue, and F. Guang, "Wideband Circularly Polarized Antenna With Gain Improvement," Antennas and Wireless Propagation Letters, IEEE, vol. 12, pp. 456-459, 2013. Arrived: 13. 04. 2014 Accepted: 20. 05. 2014 217 Original scientific paper Informacije Journal of Microelectronics, Electronic Components and Materials Vol. 44, No. 3 (2014), 218 - 223 /midem Journal of M Design and Analysis of a New Double Negative Metamaterial Sikder Sunbeam Islam1, Mohammad Rashed Iqbal Faruque1, Mohammad Tariqul Islam2 1Centre for Space Science, Research Centre Building, National University of Malaysia (UKM), Malaysia 2Department of Electrical, Electronic and Systems Engineering, Faculty of Engineering and Built Environment, Universiti Kebangsaan Malaysia, UKM, Bangi, Selangor, Malaysia Abstract: This paper presents a new double negative metamaterial unit cell structure which is designed on a Rogers RT 6010 substrate. The proposed structure exhibits resonant frequency within the C-band of microwave spectra and shows a negative permeability and permittivity at that resonant frequency. The commercially available simulation software CST Microwave Studio has been used to get the reflection and transmission parameters of the unit cell. The simulated result shows good conformity with the experimental result. In addition, an analysis has been done with the same design by replacing the substrate with popular FR-4 and then it behaves as a single negative metamaterial at the same frequency band. Keywords: DNG, Metamaterials, SNG Načrtovanje in analiza novega dvojno negativne meta material Izvleček: Članek opisuje novo strukturo osnovne celice dvojno negativnega meta materiala, ki je načrtovana na Roger RT 6010 substratu. Predlagana struktura izkazuje resonančno frekvenco v C pasu mikrovalovnega spektra in izkazuje negativno permeabilnost in permitivnost pri resonančni frekvenci. Za določitev refleksijskih in transmisijskih parametrov je bil uporabljen komercialna programska oprema CST Microwave Studio. Simulacijski rezultati se dobro ujemajo s poskusi. Opravljena je bila tudi analiza strukture na popularnem FR-4 substratuu, kjer struktura deluje kot enojno negativen meta material v enakem frekvenčnem pasu. Ključne besede: DNG, meta material, SNG * Corresponding Author's e-mail: sikder_islam@yahoo.co.uk 1 Introduction Metamaterials are artificially constructed materials which may exhibit some exotic electromagnetic property and not naturally found. It may exhibit negative value of permittivity and permeability simultaneously at a specific frequency range. Metamaterials with simultaneous negative permeability (e) and permittivity are called double negative (DNG) metamaterials. Materials of this type of negative characteristics are also called left handed materials (LHM), negative-refractive index materials, and backward wave media. The metamaterials with either of the permittivity or permeability negative is called single negative metamaterial. In 1968, Victor Veselago first explained and theoretically showed that materials with simultaneous negative permeability (^<0) and permittivity (£<0) had some different properties as compared to ordinary materials that are found in nature [1] but until 1999 this topic was not much interesting to the researchers due to lack of available such natural materials. Although there are some materials that show the property of effective negative permittivity but materials with effective negative permeability was still a challenging issue. In 2000 Smith at et al. successfully showed a new artificial material of such double negative property (i.e both ^ and £ are negative) where, Snell's law, Cherenkov radiation, Doppler Effect are inverted [2]. Due to these exotic electromagnetic properties of these materials, it can be used in many important applications like, antenna design, electromagnetic cloaking, SAR reduction etc [3-6]. There are varieties of metamaterial structures 218 © MIDEM Society S. S. Islam et al; Informacije Midem, Vol. 44, No. 3 (2014), 218 - 223 have been proposed according to the applications like U-shape, V-shape, S-shape, Triangular etc. and very few of them are applicable for C-band microwave spectra [7-12]. In this paper we are introducing a new metamaterial unit cell structure that contains two split ring resonators with a metal stripe between them and shows resonant frequency in the C-band (4-8 GHz) [13] of microwave spectra and it also shows double negative properties (both permittivity and permeability are simultaneously negative) at that frequency. 2 Design of the Unit Cell The design parameter and the schematic view of the proposed double negative unit cell structure are given in Fig. 1(a). The structure has been designed with two split ring resonators (SRR) of copper and a metal strip of copper between them with all of them having thickness of 0.035mm. Each ring has inner radius 3mm and outer radius 4mm and gap width of 1mm. In between the rings there is a metal strip of copper with a length of 14mm and width of 1.6mm. The gap between each ring and the metal is 0.33mm. The structure is printed over a square shaped Rogers RT 6010 substrate with dielectric constant of 10.2, dielectric loss-tangent of 0.002, side length and width of 30mm and thickness of 1.6 mm. The unit cell parameters are seen in the Table 1. Afterwards for further investigation, the popular FR-4 Substrate has been replaced by the Rogers RT 6010 substrate of the proposed design structure which has dielectric constant of 4.5, dielectric loss-tangent of 0.002, side length and width of 30mm and thickness of 1.6 mm. Table 1: Design specifications of the unit structure Unit Cell Parameters Value (mm) d 1 l 14 m 1.6 s 1 3 Methodology The commercially available Simulation software CST Microwave Studio has been used to compute complex scattering parameters and also to monitor the resonance frequencies of the proposed unit cell structure. These parameters are used for the retrieval of effective permeability (p) and permittivity (e) for the proposed unit cell structure. (a) - % % °lc (b) Set*ioHi Analrztr l)-► Horn Antenna Rx ^ MM Sample ^ Tx 1.5 m (c) Figure 1: (a) The proposed unit cell structure (b) Fabricated metamaterial prototype for measurement on Rogers RT 6010 substrate material (c) Measurement setup (top view) The structure has been placed between two waveguide ports of positive and negative of z- axis and excited by the transverse electromagnetic (TEM) wave. The perfect electric conductor (PEC ) boundary has been defined in the x-plane and the perfect magnetic conductor (PMC) boundary has been defined in the y-plane. Frequency domain solver has been used for simulation. The normalized impedance has been set to 50 ohm. Simulation is done for the frequency range of 4-7 GHz. 219 S. S. Islam et al; Informacije Midem, Vol. 44, No. 3 (2014), 218 - 223 However, further simulation is done after replacing the substrate with a FR-4 substrate and the same methodology has been used to get the values of S-Parameters and effective medium parameters. A 160x160 mm2 prototype of 4x4 unit cell is fabricated for measurement, as shown in Fig. 1(b). The prototype is then placed between two horn antennas which are 1.5m apart in the same plane. The measurement arrangement is being displayed in Fig. 1(c). An Agilent E8363D vector network analyzer is used to calculate the transmission co-efficient. For calibration purpose, measurement without metamaterial and with metamaterial is done. There are many methods exist for effective parameter extraction of metamaterial like-TR Method, Lossy-Drude Method, Nicolson-Ross-Weir method etc. The effective medium parameters permeability and permittivity are extracted from the simulated complex S21 and S11 parameters using method mentioned in [14]. The simplified formulae have been given bellow, v1=s21+s„ v2=s21-s„ 2 1 - V £r ; K d 1 + V2 2 1 - V1 jk0 d 1 + Vi n = (1) (2) (3) (4) (5) where, £ is the effective permittivity, pr is the effective permeability, 'd' is the thickness of the substrate, k0 is the wave number and n is the refractive index. 4 Results and Discussion The simulated result of transmission coefficient (S21) for the proposed unit cell structure is given in Fig-2(a) and the experimental results for the unit cell are seen in Fig. 2(b) and 2(c). Here the simulated spectra of the transmission coefficient (S21) shows the maximum resonance at 5.09 GHz which is in the range of C-band microwave spectra and the experimental result of the transmission coefficient that is seen in the Fig. 2(c), agrees well with the simulated result. Unlike the SRR rings the currents flows in the opposite direction of the two rings and these two opposite currents also create opposite currents in the two sides of the metal strip and Fig-3 shows the currents distribution at frequency 5.09 GHz in the unit cell structure. t—i—i i I i—i i i I—i—n—r-1—1—r-r 4.5 5 5.5 6 6.5 7 Frequency (GHz) (a) Frequency (GHz) (b) -5 -15 S -25 CM -35 -45 m i 1 1 1 1 1 i 1 1 n 1 1 1 i 1 1 1 1 1 1 1 i i 3.5 4 4.5 5.5 Frequency (GHz) (c) Figure 2: (a) Simulated transmission coefficient (S21) in dB (b) Measured value of S21 in dB without metamaterial (c) Measured value of S21 in dB with metamaterial sample The two metal rings are responsible for creating the inductance and by increasing the side length of the rings the inductance can be increased which leads to decrease the LC resonance frequency. On the other hand M 220 S. S. Islam et al; Informacije Midem, Vol. 44, No. 3 (2014), 218 - 223 Figure 3: Current distribution in the unit cell structure as the split of the rings are responsible for creating the capacitance for the design, by increasing the gap the capacitance can be reduced which leads to increase the LC resonant frequency. These results are given in Fig-4(a) and Fig-4(b) where the effective permeability is shown in Fig-4(a) and effective permittivity is shown in Fig-4(b) against frequency. In Fig-4(a) and 4(b), we see that at the maximum point of resonance frequency of 5.09 GHz, the both curve of permeability and permittivity show negative value and they are £= -13.93 (Real) and -11.92 (Real) . So, the structure can be said a double negative (DNG) metamaterial. Normally a charge builds up in the gap of a split ring resonator and creates capacitance if it is kept in a changing magnetic field. At low frequency the current of the oscillator remain in phase of the driving field but in higher frequency the current starts lagging which produces negative permeability at that frequency. The DNG material are also called negative refractive index materials, backward media, and left handed materials (LHM). In case of negative refractive index material, the light rays are refracted in the same side of its entrance. Actually in a double negative media the phase and the energy flow of the wave moves in the opposite direction which makes the wave to flow in the backward direction. Accordingly in Fig-5 the real part of refractive index curve is seen against the frequency where at frequency 5.09 GHz the refractive index is also negative and that is n= -19.09 . So, realization of negative permeability over that frequency bands may also be useful in long distance communication applications. The simulated result also depicts the double negative characteristics for the unit cell at the frequency of 4.03GHz which is in the range of S-band (2-4GHz) microwave spectra. However, the measured result has bit displaced from the simulated result in this case. This difference most likely happens because of fabrication error. 100 £ 50 Frequency (GHz) (a) Figure 4: (a) Real value of effective permeability versus frequency (b) Real value of effective permittivity (e) versus frequency Figure-5: Real value of Refractive Index versus frequency. After using the FR-4 substrate for the same design structure it is seen in Fig-6 (a), that the S-Parameter spectra has changed a bit. Previously we found that transmission spectra at 5.09 GHz for the design on Rogers RT 6010 substrate and we had sharp resonance below -25dB whereas for substrate FR-4 we have got 221 S. S. Islam et al; Informacije Midem, Vol. 44, No. 3 (2014), 218 - 223 the resonance at the frequency of 6.65 GHz but this time the resonance is seen very close to -18dB. Actually this difference in the transmission coefficients of Fig. 2(a) and Fig. 6(a) has occurred due to the difference of dielectric constants in the two substrate materials, where the Rogers RT 6010 has dielectric constants of 12.2 and FR-4 has 4.2. The dielectric constant of a material depends on the material internal structure. When electromagnetic waves propagated through a material it's electric and magnetic fields oscillate as sinusoidal pattern and its velocity depends upon the electrical conductivity of the material which actually depends on the internal structure of the material. The relative speed of electrical signal that travel through the material varies according to the type of interaction with its internal structure and this variation caused the different results in the transmission characteristics. In Fig. 6(b), the frequency versus permittivity curve for FR-4 0 -, -4 • m -7- u Csl -11 • U) -14 - 5.0 5.3 5.5 5.8 6.0 6.3 Frequency (GHz) 6.5 6.8 7.0 (a) substrate depicts that permittivity is still negative and its real value is £= -4.77 which was -1.03 for Rogers RT 6010 based design. However the Fig. 7(a) reveals that the permeability for the FR-4 substrate for the same design does not show negativity and the real value is 8.33 which was previously -4.48 for Rogers RT 6010 substrate. So, now it is clear that the design based on FR-4 substrate does not show double negative characteristics and accordingly the real value of refractive index in Fig-7(b) reveals the positive value of n= 0.92. So, for FR-4 substrate the material can be characterized as single negative (SNG) metamaterial. The overall comparative results are presented in Table 2. 5.8 6.0 6.3 Frequency (a) Figure 7: (a) Real magnitude of permeability for FR-4 substrate material (b) Real magnitude of refractive Index (n) for FR-4 substrate material Figure 6: (a)Transmission coefficient for FR-4 substrate material (b) Real magnitude of permittivity (e) for FR-4 substrate material Table 2: Effective parameters comparisons for two popular substrate materials Substrate Dielectric Constant Frequency (GHz) Permittivity(E) Permeabiiity(^) Refractive Index (n) Metamaterial Type Rogers RT 6010 10.2 5.09 GHz -13.93 -11.92 -19.09 DNG FR-4 4.2 6.65 GHz -4.77 8.33 0.92 SNG 222 S. S. Islam et al; Informacije Midem, Vol. 44, No. 3 (2014), 218 - 223 5 Conclusion In this paper we have presented a new double negative metamaterial structure on Rogers RT 6010 that resonates at frequency in 5.09 GHz which is in the C-band of microwave spectra. We have then changed the substrate by popular FR-4 substrate and we have found the resonance at point of 6.65 GHz which is also in the C-band. However, it does not show double negative characteristics at 6.65GHz. C-band of microwave spectra specially used for long distance communication like, satellite communications. We have used two popular substrates to demonstrate its metamaterial characteristics and we have done comparative analyses between them. So, this structure can be used besides other metamaterials especially in the C-band metamaterial applications. 6 Reference 1. V. G. Veselago, "The electrodynamics of substances with simultaneously negative values of £ and M," Soviet Physics Usp., vol. 10, pp.509-514, 1968. 2. D. R. Smith, Willie J. Padilla, D. C. Vier, S. C. Nemat-Nasser, and S. Schultz, "Composite medium with simultaneously negative permeability and permittivity," Physical Review Letters, vol. 84, no. 18, 2000 3. M. H. Ullah, M. T. Islam and M. R. I. Faruque, A Near-Zero Refractive Index Meta-Surface Structure for Antenna Performance Improvement; Materials, 6, pp.5058-5068; 2013 4. M. T. Islam, M. H. Ullah, M. J. Singh and M. R. I. Faruque; A New Metasurface Superstrate Structure for Antenna Performance Enhancement; Materials 6, pp.3226-3240,2013 5. M. R. I. Faruque, M. T. Islam, N. Misran, "Design analysis of new metamaterial for EM absorption reduction," Progress In Electromagnetics Research, PIER 124, pp. 119-135, 2012 6. M. R. I. Faruque, M. T. Islam, N. Misran, "Analysis of Electromagnetic Absorption in the Mobile Phones Using Metamaterials," Electromagnetics Journal (Taylor & Francis Group), Vol. 31, Issue no. 3, pp.215-232, 2011 7. Baena, J. D., R. Marques, F. Medina, and J. Martel, Artificial magnetic metamaterial design by using spiral resonators," Phys. Rev. B, Vol. 69, pp.0144021-5, 2004. 8. Chen, H., L. Ran, J. Huangfu, X. Zhang, and K. Chen, Left-handed materials composed of only S-shaped resonators," Phys. Rev. E, Vol. 70, pp. 0576051-4, 2004. 9. Wang, D., L. Ran, H. Chen, M. Mu, J. A. Kong, and B.-I. Wu, Experimental validation of negative refraction of metamaterial composed of single side paired S-ring resonators," Appl. Phys. Lett., Vol. 90, 2541031-3, 2007. 10. Gallas, B., Robbie, K., Abdeddaim, M., Guida, G., Yang, J. Rivory, J. and Priou, A., "Silver square na-nospirals mimic optical properties of U shaped metamaterials", Optics express, Vol-18, 16335, 2010. 11. M. R. I. Faruque and M. T. Islam, "Novel design of triangular metamaterial for electromagnetic absorption in human head," Progress In Electromagnetics Research, PIER 141, pp. 463-478, 2013 12. Evren Ekmekci and Gonul Turhan-Sayan, "Investigation of effective permittivity and permeability for a novel V-shaped metamaterial using S-parameters,"proceedings od 5th International Conference on Electrical and Electronics Engineering, December 2007, Bursa, Turkey. 13. IEEE standard letter designations for Radar frequency bands, IEEE standard. 521-2002. Available at: https://standards.ieee.org/findstds/ standard/521-2002.html (accessed on 22th March 2014) 14. Olli Luukkonen, Stanislav I. Maslovski, and Sergei A. Tretyakov, A Stepwise Nicolson-Ross-Weir-Based Material Parameter Extraction Method, IEEE Antennas And Wireless Propagation Letters, VOL. 10, 2011 Arrived: 02. 04. 2014 Accepted: 25. 06. 2014 223 Original scientific paper Informacije | Journal of Microelectronics, Electronic Components and Materials Vol. 44, No. 3 (2014), 224 - 234 /midem loiirnal of M CCM and DCM Analysis of Quasi-Z-Source Derived Push-Pull DC/DC Converter Andrii Chub1, Oleksandr Husev1,3, Andrei Blinov1,2, Dmitri Vinnikov1 1Tallinn University of Technology, Estonia 2Royal Institute of Technology, Sweden 3Chernihiv National University of Technology, Ukraine Abstract: This paper presents a steady state analysis of the operation modes of the quasi-Z-source (qZS) derived push-pull DC/DC converter topology. It was derived by the combination of the qZS network and coupled inductors. The output stage of the converter consists of a diode bridge rectifier and an LC-filter. This topology provides a wide regulation range of the input voltage and galvanic isolation. These features fit the requirements for the integration systems of renewable energy sources, such as PV panels, variable speed wind turbines, and fuel cells. A converter can operate in continuous (CCM) and discontinuous conduction mode (DCM). Switching period is divided into four and six intervals for CCM and DCM, respectively. Equivalent circuits and analytical expressions for each interval are presented. The DC gain factor for each mode is derived. To simplify our analysis, coupled inductors were substituted with a model that consists of an ideal transformer and magnetizing inductance. Leakage inductances are neglected because the coupling coefficient in this topology should be close to unity. In DCM the converter operation depends on the active duty cycle and the duty cycle of the zero current condition. Two solutions are possible for the DC gain factor in DCM. It is theoretically impossible to achieve the unity DC gain factor in DCM if the turns ratio of coupled inductors is equal to or more than one. The proposed topology was simulated with PSIM software in two operating points. Experimental verification proves our theoretical and simulation results. Keywords: DC/DC converter, quasi-Z-source converter, galvanic isolation, renewable energy, steady state analysis. Analiza CCM in DCM Push-Pull DC/DC pretvornika z impedančnim prilagodilnim vezjem Izvleček: Članek opisuje statično analizo delujočih stanj push-puli DC/DC pretvornika z impedančnim prilagodilnim vezjem (qZS). Izveden je s kombinacijo qZS omrežja in sklopljenih tuljav. Izhodna stopnja pretvornika je sestavljeno iz diodnega usmerniškega mostiča in LC filtra. Topologija omogoča široko regulacijsko območje in galvansko ločitev. Lastnosti ustrezajo zahtevam integriranih sistemov obnovljivih virov energije, kot so PV moduli, vetrne turbine s spremenljivo hitrostjo in gorivne celice. Pretvornik lahko deluje v neprekinjenem (CCM) ali prekinjevalnem (DCM) prevodnem režimu. Perioda preklapljanja je razdeljena na štiri ali šest intervalov za CCM oziroma DCM. Predstavljeno je ekvivalentno vezje in analiza za vsak interval ločeno. Za vsak način je izračunano faktor DC ojačenja. Za poenostavljeno analizo so bili, za sklopljene tuljave, uporabljeni modeli z idealnim transformatorjem in magnetno induktivnostjo. Uhajalne induktivnosti so zaradi enotnosti koeficienta enotnosti v tej topologiji zanemarjene. Pri DCM je delovanje odvisno od aktivnega obratovalnega ciklusa in obratovalnega ciklusa pri ničelnem toku. Možni sta dve rešitvi za DC ojačenje pri DCM. Teoretično je nemogoče doseči enotno ojačenje pri DCM če je razmerje ovojev sklopljenih tuljav večje ali enako ena. Predlagana topologija je bila simulirana s programskim paketom PSIM v dveh točkah delovanja. Ekperimentalen preizkus potrjuje teorijo in rezultate simulacij. Ključne besede: DC/DC pretvornik, impedančno prilagodilno vezje, galvanska ločitev, obnovljivi viri, statična analiza * Corresponding Author's e-mail: andrii.chub@ieee.org 1 Introduction Quasi-Z-source inverters (qZSIs) providing logical improvement of Z-source inverters were proposed in 2008 [1]. QZSIs extend the family of single stage buck-boost inverters. The concept of the QZSI provides improved reliability due to high EMI withstandability, wide input voltage regulation possibility, and continuous input 224 © MIDEM Society A. Chub et al; Informacije Midem, Vol. 44, No. 3 (2014), 224 - 234 current. These features make the qZSI appropriate for the realization of renewable energy systems (PV panels, fuel cells, wind turbines, etc.) [2]-[5] and electric vehicle applications [6]. Output voltage of the renewable energy sources (RES) usually is by far lower than grid voltage. An intermediate DC/DC converter can be used for voltage stabilization when high step-up is needed for RES integration into the grid [7-9]. DC/DC qZSI-based converters have been widely used because of their good performance as voltage matching converters that interconnect the RES and the grid-tied inverter [10]-[12]. The recent push-pull converter derived from the quasi-z-source (qZS) concept is shown in Fig. 1 [13]. This topology has ample opportunities for DC gain regulation [14]. Continuous input current can be achieved in a wide range even for the discontinuous conduction mode (DCM) in branches. The converter contains small component count and only two active switches that lead to a simple control circuit. Topology derivation is based on the combination of two qZS networks implemented with two three-winding coupled inductors. The converter utilizes two qZS networks: C;, C2, Dv TRt and C3, C4, D2, TR2, as shown in Fig. 1. Three-winding coupled inductors TRt and TR2 provide galvanic isolation and store energy in the form of equivalent magnetizing current (i.e. field in the core of the coupled inductors). Transistors Tt and T2 work interleaved. The turn-on state of the transistor corresponds to the shoot-through behavior of the qZS network. Capacitors of the qZS network transfer part of the stored energy to the coupled inductor and the output load during the equivalent shoot-through state. Voltage across the primary windings can be described similarly to that of the conventional qZS network. Current in the primary windings of the coupled inductors differs from the current in the conventional qZS network due to the energy transfer process in the coupled inductors. From the input side the converter looks like two independent branches. These branches are connected in series by means of secondary windings. Summarized voltage of the secondary windings vS(t) is applied to the diode bridge rectifier Dr..D6. Rectified voltage feeds the output load with the rectified voltage through the LC-filter L, C. The frequency of the current ripple of the input current and the output inductor current is twice higher than the switching frequency of the transistors. Voltage regulation is achieved by the adjusting of the turn-on state (active) duty cycle of the transistor. The aim of this article is to present an analytical description for possible operation modes of the qZS derived push-pull converter. Like most of step-up switching power converters, the investigated topology can operate in the continuous conduction mode (CCM) and DCM. In DCM the transistors and diodes of the qZS networks suffer from high voltage stress. DCM occurs at low DC gain and low input power. The DC gain characteristic depends strongly on the operation mode. This paper is based on our earlier preliminary version [15] and includes substantially revised theoretical analysis and additional experimental results, not presented there. Figure 1: qZS-derived push-pull converter topology. Several assumptions should be made for our further analysis. In this topology a coupled inductor should have the coupling coefficient close to unity. Primary windings should have an equal number of turns NJ2. It means that in each qZS network voltages across the primary windings are equal: vPll(t) = vPJ2(t), vP21(t) = vP22(t). The secondary winding utilizes N3 turns. The turns ratio k = N3/NJ2 defines the minimum achievable DC gain. Voltage across the secondary winding depends on the turns ratio and the voltage of the primary windings: vjt) = k-vpu(t), vS2(t) = -k-vP2J(t), vjt) + vS2(t) = vS(t). In this case coupled inductors can be substituted with a simplified model that consists of the magnetizing inductance Lm reflected to one of the windings and an ideal transformer with NJ2:N3 primary to secondary turns ratio. Also, in any mode currents in the primary windings of each coupled inductor are equal: i(t) = i2(t), i3(t) = i4(t). Let us assume that the voltage ripple of all capacitors in the converter is well below the corresponding average voltage. These assumptions and the symmetry of branches result in equal average voltages across the capacitors: VC1 = VC3, VC2 = VC4. Let us assume that the current of the filter inductor iff(t) is continuous in any mode. None of the losses are considered in this article. It means that the input power P and the output power are equal: IOUT = ILf = P/VOUT. The lower case letter of the voltage and the current corresponds to an instantane- 225 A. Chub et al; Informacije Midem, Vol. 44, No. 3 (2014), 224 - 234 ous value, and the upper case letter or angle brackets correspond to an averaged (or constant in some cases) value. The input power is represented as P. For the symmetry operation of the branches, each of them should operate at half of the rated power: I4 = I2 = P/(2-VJ. 2 Circuit Steady-State Analysis in CCM_ Current and voltage waveforms for an idealized converter in CCM are shown in Fig. 2. The figure shows that the switching period of the converter T can be divided into four time intervals: two equal active intervals during which only one of the transistors is turned on (i.e. active states with the time duration tA each) and two inactive intervals when both transistors are not conducting (i.e. zero state, t0 each): T + T = Da + D = °-5- yo (1) where DA is the duty cycle of an active state and D0 is the duty cycle of a zero state. It is clear from (1) that Da < 0.5 and D0 < 0.5. In CCM, as well as in DCM, the current ijt) has a double switching frequency ripple. Also, in both modes ijt) always rises during active states and falls during a zero state. Figure 3a shows the equivalent circuit of the converter for the time interval t1-t2 when the transistor T1 is turned on, diode D1 is blocked and D2 is conducting. Equations (2)-(6) describe the behavior of the converter during this time interval. vC\(t) = vC2(t) - VIN > vc2(t) = VpU(t) = Lm diLMl(t) = LM ' dt(l(t) + il(t) - k ' iLf(t)) dt diLM 2(t) dt vCÎ(t) = -vp 2l(t) = -Lm = -Lm ' d (t + l4(t) + k ' 'Lf^ vc 4(t) = VIN + VC ^(t), Vs(t) = Vsi(t) + Vs2(t) = k ■ (Vc2(t) + Vcifl)) = = k ■ Lm ■ d ((t) + i2(t) - h(t) - u(t) - 2 ■ k ■ iLf(t)) (2) (3) (4) (5) (6) where va(t), vC2(t), vC3(t), vC4(t) are the capacitor voltages, vSl(t) and vS2(t) are the voltages of the corresponding secondary windings of the transformer, vS(t) is the summarized voltage of the secondary winding applied to the rectifier, i1(t), i2(t), i3(t), i4(t) are the currents of the corresponding primary windings of the transformer, LM is the magnetizing inductance of the coupled induc- tors, k is the turns ratio of the coupled inductors, and ijt) is the current of the filter inductor Lf Figure 2: Generalized converter voltage and current waveforms during the operation in CCM. During the interval t2-t3 both transistors are not conducting, diodes D1 and D2 are conducting. The equivalent circuit of the converter is depicted in Fig. 2b. Equations (7)-(11) describe the operation of the converter for that time interval. Summarized voltage of the secondary windings v5(t) is equal to zero if the voltage ripple of the qZS capacitors is negligible. diLM \(0 vci(t) = -vpii(t) = - LM d dt = -Lm ■ dt (h(t) + ii(t) - k ■ ft)) vc 2(t) = vin + vci(u Vc 3(f) = -Vp2i(t) = - Lm d diLM2(t) . dt = -Lm ' Jt ((t) + i4(t) + k ■ iLf(t)\ vC 4 (t) = VIN + vc 3(t), (7) (8) (9) (10) 226 A. Chub et al; Informacije Midem, Vol. 44, No. 3 (2014), 224 - 234 (a) (b) (c) (d) Figure 3: Equivalent circuits of the investigated converter in CCM. Vs(t) = Vsi(t) + Vs2(t) = k ■ (vc3(t) - Vci(t)) = = k ■ Lm •d(ii(t) + i2(t) - i3(t) - i4(t) - 2 ■ k ■ iLf(t)) 0. (11) dt Figure 2c depicts the equivalent circuit of the converter for the time interval t3-t4 when the transistor T2 is turned on, the diode D2 is reverse based and D1 is conducting. Equations (12)-(16) define the operation of the converter during the time interval t3-t4' vci(t) = -vPii(t) = -lm • d t diLM l(t) dt = -Lm ■d (ii(t) + h(t) + k • iLf(t)\ dt vC2(t) = VIN + Vcii*)' Vc() = Vc4(t) - Vi IN' vC 4(t) = vP2\(t) = LM d diLM 2(t) dt = LM ■ — ih(t) + U(t) - k ■ lLf(t)\ (12) (13) (14) (15) dt Vs(t) = Vsi(t) + Vs2(t) = k ■(- Vci(t) - Vc()) = d( \ (16) = k ■ Lm ■ — (h(t) + i2(t) - h(t) - u(t) - 2 ■ k ■ ft)) During the interval t4-t5 both transistors are switched off, diode D1 and diode D2 are conducting. The equivalent circuit for the fourth interval is shown in Fig. 2b. Equations (17)-(21) define the behavior of the converter for the time interval t4-t5. Summarized voltage of the secondary windings vS(t) is equal to zero if the voltage ripple of the qZS capacitors is negligible. The fourth interval differs from the second in the direction of the current ijt) via the secondary windings, i.e. iS(t) has an opposite sign. vc\(t) = -vm(t) = - lm■ d diLM 1(t) dt = -Lm ' Jt ( + i2(t) + k" VC 2(t) = VIN + vCl(t)' vC3(t) = -vP2l(t) = -LM ■ = -LM ' Jt ((t) +i4(t) - k ' ^^ diLM2(t) . dt vc 4(t) = VIN + VC 3(t), Vs(t) = Vsi(t) + Vs2(t) = k ■ (vc3(t) - vci(t)) = = k ■ Lm ■d((t) + i2(t) - i3(t) - U(t) + 2 ■ k ■ iLf(t)) 0. (17) (18) (19) (20) (21) dt At the time moments t1, t3 and t5 currents in the primary windings change by step: M2 (tl) = -Ai4(tl) = k ■ iLf (tx), Ai4 (t3 ) = -M2 (t3 ) = k • iLf (t3 ), fe ) = -Al'4 (t5) = k ■ iLf (t5 ). 227 A. Chub et al; Informacije Midem, Vol. 44, No. 3 (2014), 224 - 234 This step change could be explained by the change of the direction of the current is(t). Also, these steps are equal because ijtj = ijtj = ijtj. These steps are not reflected in the input current because the steps of currents i2(t) and i4(t) compensate each other. According to the voltage-second balance principle, the average voltage across the primary winding of the coupled inductor over one switching period equals zero. That can be used for the calculation of the average voltage across the qZS capacitors: T Vpn = {vpu(t )) = T J vpu(t)dt = 0, 0 T VP21 = {VP 21 (ß ) = T J VP2l(t )dt = 0. (22) (23) In order to solve Eqs. (22) and (23) we need to assume that the voltage across the capacitors is close to the average value over the switching period: vCi(0 » D0. Voltage is applied to the diode D2: vD2(t) = vC3(t) + a, where a = vP21(t). Voltage a is constant during this time interval. Equations (39)-(43) describe the operation of the converter during this time interval when i3(t) = i4(t) = 0. Vci(t) = Vc2(t) - VIN , (39) vC 2(t) = vPll(t) = L d M diLMl(t) . dt = Lm ■ — () + h(t) - k ■ iLf(t)) dt vp21(t) = vp22(f) = a = k ■ L ' / , n ^ • dilf(t) m dt vC 4(t) = VIN + vC 3(1), vs(t) = Vsi(t) + vs2(t) = k ■ (vc2(t)) - k ■ Lm ■ - diLf(t) dt (40) (41) (42) (43) = k ■ lM ■d (h(t) + hit) - 2 • k ■ iLf(t}) = Vc2 - a. Figure 6b shows the equivalent circuit of the converter for the time interval t'3-t4 when the transistor T2 is conducting, the diode Dt is not conducting, and the diode D2 is reverse based. Voltage is applied to the diode Df vD1(t) = vC3(t) + a, where a = vP11(t). Equations (44)-(48) describe the behavior of the converter over this time interval considering that i(t) = i2(t) = 0. vPU(t) = vpn(t) = a = k ■ L diLf(t) M dt VC 2(t) = VlN + Vci(t), vC3(t) = vC4(t) - VIN > vC 4(t) = vP22(t) = LM diLM 2O) dt = LM ■ (i3(t) + i4(t) - k ■ iLf(t)]) dt diLf(t) vs(t) = Vsi(t) + Vs2(t) = k ■{- vCA(t)) + k ■ Lm--J— = dt = k ■ Lm ■d(- h(t) - U(t) + 2 ■ k ■ iLf(t))-Va4 + dt (44) (45) (46) (47) (48) a. 3.1 DCM mode 1 If the duty cycle of the DCM state is less than the duty cycle of the zero state (0 < y < D0), the operation of the converter will remain unchanged. In this case the behavior of the converter could be described by Eqs. (2)-(6). 3.2 DCM mode 2 In case the duty cycle of the DCM state lies in the range D0 < y < 0.5, the average voltage of the qZS capacitors and the DC voltage gain of the converter should be recalculated. It can be done using Fig. 5, taking into account (22)-(31), and assuming that a is equal to zero in order to simplify the calculations: Vpn = Vc2 ■ Da - Va -(1 - Da-y+ D0 ) = = Da-(Vm + Vci)-Vci -(1.5-y-2• DA)= 0, Vci = Vc 3 = 2 • D 3 - 2•y-6•Da -V„ V _V _3-2-r-4•Da v Vc 2 _ Vc 4 _ 3 - 2-r-6 • DAVlN • (49) (50) The output voltage of the converter operated in DCM when D0 < y < 0.5 can be expressed as 1 t vout = j ji vsi(t) + vs 2(i) • dt' -k-2 T ( T • (0.5-70 J(Vo 2 + Vc3 )dt + j Vc 2 • dt \ T-(0.5-0) (51) N3 8-Da-(1 -0-DA ) Nr 3 - 2• 0-6-Da •V N The resulting DC voltage gain of the proposed DC/DC converter is G = k ■ 8 • DA (1 -Y-DA ) 3-2 Y-6•Da ' (52) In the DCM, when y = 0.5 each branch consumes current only during T/2. In this case, time t1 equals t'1, and time t3 equals t'3. The input current of the converter is in the boundary conduction mode and reaches zero twice per switching period at the time moments t1 and t3. Current steps occur due to the change of the sign of the current iS(t) at the same time moments. The condition y > 0.5 is theoretically possible when the converter needs to operate at very low input power compared to the rated power value. This mode corresponds to the discontinuous input current. It should be avoided because of high overvoltage across the power semiconductor components. This mode could be avoided practically due to the losses in the converter. Also, renewable energy systems usually require high step-up at low power, or do not require ultra-light-load operation. On the other hand, in this mode the converter needs enormous inductance at the output filter 229 A. Chub et al; Informacije Midem, Vol. 44, No. 3 (2014), 224 - 234 to satisfy the assumption about the continuous inductor current. Figure 5: Generalized converter voltage and current waveforms during the operation in DCM. 4 Experimental Verification Theoretical assumptions were verified by means of modeling. The model was rated for the power of 600 W in compliance with the topology shown in Fig. 1. Component values and given modeling conditions are listed in Table I. Simulation results are shown in Figs. 8 and 10. In the first case, the model of the converter operates in CCM (input voltage of 70 V and DA = 0.43), while in the second modeling, the converter operates in DCM (input voltage of 250 V and DA = 0.25). (a) Figure 6: Additional equivalent circuits of the investigated converter for DCM. Theoretical and simulation results were verified using a 600 W laboratory prototype, which is shown in Fig. 7. It was assembled in compliance with schematics in Fig. 1. Experimental waveforms including the input voltage are presented in Figs. 9 and 11. In the case of 70 V at the input, the converter operates in CCM. For CCM, experimental results are in good agreement with the theoretical assumption. On the other hand, when the input voltage equals 250 V, and the converter operates in DCM, the parasitic parameters in the experimental prototype cause major oscillations. Distinctions between the experimental and simulated waveforms are considerable. Figure 12 shows experimentally measured curve of active state duty cycle DA versus input voltage and DC voltage gain for constant output voltage 400 V and output power 600 W. CCM is achieved for input voltage below 150 V DC. Converter operates in DCM when input voltage is higher than 150 V DC. Measured curve has higher non-linearity in DCM, as it was expected. 230 A. Chub et al; Informacije Midem, Vol. 44, No. 3 (2014), 224 - 234 Table 1: Operating Parameters and Passive Component Values of the Converter (a) Main operating parameters Value Minimal input voltage VIN, min 70 V Maximal input voltage VIN, max 250 V Desired output voltage VOUT 400 V Nominal power P 600 W Switching frequency fsw=1/T 100 kHz Turns ratio of the isolation transformers N3:N12 1:1 Passive component values Capacitance value of the capacitors C1...C4 60 |F Magnetizing inductance of the isolation transformers LM 1 mH Inductance of the filter inductor Lf 1 mH Capacitance of the filter capacitor Cf 220 |F Figure 7: Converter prototype used for experimental verification. 5 Conclusions The paper has presented a steady state analysis of the operation of the qZS derived push-pull DC/DC converter in the continuous and discontinuous conduction mode. The mathematical analysis provides a general solution for waveforms and values of voltage and current in the passive components. Some differences between the theoretical results and the simulation and experimental results are related to an idealized model (losses in components, leakage inductance are neglected). The converter reveals that the behavior in DCM is complicated. The DCM state duty cycle appears when half of the current ripple through the primary winding, defined by the magnetizing inductance, surpasses an average primary winding current defined by the load power. This mode of operation could occur at the gain factors closer to unity. This topology is a good solution (b) (c) Figure 8: CCM simulated waveforms of the transformer primary (a), transistor (b) and qZS diode (c) at 600 W with the input voltage of 70 V for the integration of a variable voltage variable speed small wind turbine. In this case the converter operates with a lower gain at a higher power. This condition combined with the features of the converter could ensure operation in CCM in a wide range of power The mathematical analysis was verified by means of the simulation software and the experimental prototype. As shown, the results are in good agreement with the theoretical predictions. 231 A. Chub et al; Informacije Midem, Vol. 44, No. 3 (2014), 224 - 234 (a) (b) (c) (a) 15 12 < 9 Ti 6 o c 3 0 U -3 -6 1 800 > 600 a ni 400 to 200 > 0 -200 .A w/VW. 0 2 4 6 8 10 12 14 16 18 20 i iik L .........1. r*"" ' 0 2 4 8 10 12 Time (us) 14 16 18 20 Figure 9: CCM experimental waveforms of the transformer primary (a), transistor (b) and qZS diode (c) at 600 W with the input voltage of 70 V. (b) (c) Figure 10: DCM simulated waveforms of the transformer primary (a), transistor (b) and qZS diode (c) at 600 W with the input voltage of 250 V. 6 Acknowledgments The authors would like to thank the European Center for Power Electronics (ECPE) for the support of this research. This research work was co-financed by the Estonian Ministry of Education and Research (project SF0140016s11), Estonian Research Council (Grant G8538) European Social Fund and MOBILITAS Postdoctoral Research Grant (MJD391). 7 References 1. 2. J. Anderson, F. Z. Peng, "Four Quasi-Z-Source Inverters," in Proceedings of Power Electronics Specialists Conference 2008 (PESC'2008), pp. 27432749, 15-19 June 2008. C. Roncero-Clemente, S. Stepenko, O. Husev, V. Minambres-Marcos, E. Romero-Cadaval, and D. Vinnikov, "Three-Level Neutral-Point-Clamped Quasi-Z-Source Inverter with Maximum Power 232 A. Chub et al; Informacije Midem, Vol. 44, No. 3 (2014), 224 - 234 (a) (b) (c) Figure 11: DCM experimental waveforms of the transformer primary (a), transistor (b) and qZS diode (c) at 600 W with the input voltage of 250 V. Point Tracking for Photovoltaic Systems,"" Technological Innovation for the Internet of Things, vol. 394, L. Camarinha-Matos, S. Tomic, and P. Graça, Eds., ed: Springer Berlin Heidelberg, 2013, pp. 334-342. 3. Yuan Li, J. Anderson, F.Z. Peng, Dichen Liu, "Quasi-Z-Source Inverter for Photovoltaic Power Generation Systems,"" in Proceedings of Twenty-Fourth Annual IEEE Applied Power Electronics Conference and Exposition, (APEC'2009), pp. 918-924, 15-19 Feb. 2009. 0.5 0.45 < Q 0.4 o o k. 0.35 •w P TJ 0.3 (j < 0.25 0.2 DC voltage gain G 4 2.67 2 1.6 X 'H 1 50 100 150 200 Input voltage [V] 250 Figure 12: Experimentally measured active state duty cycle Da versus input voltage and DC voltage gain. 4. Liu Yushan, Baoming Ge, Fang Zheng Peng, Abu Rub Haitham, Anibal T. de Almeida, Fernando J.T.E. Ferreira, "Quasi-Z-Source Inverter Based PMSG Wind Power Generation System," in Proceedings of 2011 IEEE Energy Conversion Congress and Exposition (ECCE'2011), pp. 291-297, 17-22 Sept. 2011. 5. C. Roncero-Clemente, E. Romero-Cadaval, O. Hu-sev, D. Vinnikov, "Simulation Study of Different Modulation Techniques for Three-Level Quasi-Z-Source Inverter,"" The Scientific Journal of Riga Technical University - Electrical, Control and Communication Engineering, vol. 2, pp. 14-19, 2013. 6. Feng Guo, Lixing Fu, Chien-Hui Lin, Cong Li, Woongchul Choi, Jin Wang, "Development of an 85-kW Bidirectional Quasi-Z-Source Inverter With DC-Link Feed-Forward Compensation for Electric Vehicle Applications," IEEE Transactions on Power Electronics, vol. 28, no. 12, pp. 5477-5488, Dec. 2013. 7. Fuel Cell Handbook, EG&G Technical Services, Inc., Nov. 2004. 8. Tan, K.; Islam, S. "Optimum control strategies in energy conversion of PMSG wind turbine system without mechanical sensors"", IEEE Transactions on Energy Conversion, vol.19, no.2, pp. 392- 399, June 2004. 9. Yuan Li; Anderson, J.; Peng, F.Z.; Dichen Liu, "Quasi-Z-Source Inverter for Photovoltaic Power Generation Systems"", in Proc. of IEEE Applied Power Electronics Conference and Exposition APEC'2009, pp. 918-924, 15-19 Feb. 2009 10. D. Vinnikov, I. Roasto, "Quasi-Z-Source-Based Isolated DC/DC Converters for Distributed Power Generation,"" IEEE Transactions on Industrial Electronics, vol. 58, no. 1, pp. 192-201, Jan. 2011. 233 A. Chub et al; Informacije Midem, Vol. 44, No. 3 (2014), 224 - 234 11. D. Vinnikov, L. Bisenieks, I. Galkin, "New Isolated Interface Converter for PMSG based Variable Speed Wind Turbines," Przeglad Elektrotechnic-zny, vol. 88, no 1a, pp. 75-80, 2012. 12. D. Vinnikov, I. Roasto, R. Strzelecki, M. Adamow-icz, "Step-Up DC/DC Converters With Cascaded Quasi-Z-Source Network," IEEE Transactions on Industrial Electronics, vol. 59, no. 10, pp. 3727-3736, Oct. 2012. 13. Vinnikov, D.; Zakis, J.; Husev, O.; Strzelecki, R. "New High-Gain Step-Up DC/DC Converter with High-Frequency Isolation," 2012 Twenty-Seventh Annual IEEE Applied Power Electronics Conference and Exposition (APEC), pp. 1204-1209, 5-9 Feb. 2012. 14. Blinov, A.; Vinnikov, D.; Husev, O.; Chub, A. "Experimental Analysis of Wide Input Voltage Range qZS-derived Push-Pull DC/DC Converter for PMSG-based Wind Turbines", Proceedings of 2013 Conference for Power Conversion, Intelligent Motion, Renewable Energy and Energy Management PCIM'2013, pp. 1435-1444, 2013. 15. O. Husev, A. Blinov, D. Vinnikov, A. Chub, "Steady-state analysis of qZS-derived push-pull DC/DC converter with wide input voltage regulation range", in Proc. of 8th International ConferenceWorkshop Compatibility and Power Electronics (CPE 2013), Ljubljana, Slovenia, 2013, pp. 320325. Arrived: 01. 03. 2014 Accepted: 02. 07. 2014 234 Original scientific paper /midem Journal of M Informacije | Journal of Microelectronics, Electronic Components and Materials Vol. 44, No. 3 (2014), 235 - 241 Sneak path current equivalent circuits and reading margin analysis of complementary resistive switches based 3D stacking crossbar memories Ertugrul Karakulak1, Re§at Mutlu2, Erdem Ugar3 1Electronics Department, Vocational School of Technical Sciences, Namik Kemal University, Tekirdag, Turkey 2Electronics and Telecommunication Engineering Department, Corlu Engineering Faculty, Namik Kemal University, Tekirdag, Turkey 3Department of Computer Engineering, Trakya University, Edirne, Turkey Abstract: Sneak path currents of resistive memories is an important issue. They increase with increasing memory size and should be minimized for a usable resistive memory. The complementary resistive cells have been suggested as an alternative to one-cell resistive memories to decrease leakage currents. In literature, multilayer resistive memory topologies have also been inspected to minimize leakage currents. Recently, feasibility of 3D resistive RAMs is also inspected. However, to the best of our knowledge, no one has given equivalent leakage circuit models for complementary resistive switches based 3D resistive RAMs yet. In this study, equivalent leakage circuit models for different layers of a 3D resistive RAM with complementary resistive cells have been given and their leakage resistance and reading margins are compared to that of one layer crossbar memory. Some interesting and crucial results are obtained. Alternative complementary resistive switches based 3D resistive RAM topologies with insulating layer(s) for minimized leakage currents are suggested. Keywords: Complementary Resistive Switches, 3D Multilayer Resistive RAM, Crossbar Memory, Sneak Path Currents. Nadomestna električna vezja za analizo kvarnih tokov in analiza bralne meje pri komplementarnih uporovnih stikalih na osnovi 3-D večplastnih križnih pomnilnikov Izvleček: Velik problem uporovnih pomnilnikov predstavljajo kvarni tokovi, ki se, z večanjem pomnilnika, povečujejo. Za zmanjševanje uhajalnih kvarnih tokov so, kot alternativa enoceličnim uporovnim pomnilnikom, predlagane komplementarne uporovne celice. Nadalje lahko v literaturi, za zmanjševanje uhajalnih tokov, zasledimo večplastne uporovne pomnilniške topologije. Trenutno se raziskuje tudi 3D uporovne pomnilnike. Glede na naše znanje, trenutno nihče še ni uspel podati ekvivalentnega vezja za 3D uporovne pomnilnike na osnovi komplementarnih uporovnih stikal. V tem delu je podano ekvivalentno vezje kvarnih uhajalnih tokov za različne plasti 3D uporovnega pomnilnika s komplementarnimi uporovnimi celicami in primerjava uhajalne upornosti ter bralne meje tega koncepta in enoslojnega križnega pomnilnika. Dobljeni so bili zanimivi in odločilni rezultati. Za minimiziranje uhajalnih tokov so predlagani alternativni 3D uporovni pomnilniki s komplementarnimi uporovnimi stikali in izolacijskimi plastmi. Ključne besede: komplementarna uporovna stikala, 3D večplastni uporovni pomnilniki, križni pomnilniki, kvarni tokovi * Corresponding Author's e-mail: ekarakulak@nku.edu.tr 235 © MIDEM Society E. Karakulak et al; Informacije Midem, Vol. 44, No. 3 (2014), 235 - 241 1 Introduction Resistive switch memories are also memristive devices and they are under consideration for non-traditional memory applications [1 - 3]. Resistive switch memories may help to speed up the booting of computers, reducing their energy consumption and open the way for high density memories. Optimization and minimization of their leakage current and power consumption has emerged as an exciting new research area [4, 5]. Complementary resistive switching (CRS) memories have been suggested to minimize leakage currents in [6, 7]. Multilayer resistive memories are suggested so that the decreased number of cells in the selected layer results in less leakage current. 3D multilayer crossbar array memories are also suggested to maximize memory density [8 - 12]. Previously, 3D multilayer crossbar array memories with CRS cells are considered and their leakage is examined using simulations [10, 11, 13]. However, to the best of our knowledge, no equivalent circuit model for their leakage paths does exist in the literature yet. In this study, for the first time in literature, leakage equivalent circuits of a CRS based 3D Resistive RAM (CB-3D-ReRAM) have been given and leakage resistances and reading margin of one layer and CB-3D-ReRAM leakage currents are compared using the equivalent circuits. The paper is arranged as follows. In the second section, a CRS cell is briefly explained. In the third section, equivalent leakage circuit of one layer CRS based quadratic memory is given. In the fourth section, the CB-3D-ReRAM is briefly explained and its equivalent circuits for reading a cell at the bottom, the top and middle layers are given. In the fifth section, comparison of leakage resistance and reading margin for different layers of CB-3D-ReRAM to that of a one layer quadratic memory are given using the ratio of the maximum CRS resistance to the minimum CRS resistance when both memories have the same size. In the sixth section, alternative CB-3D-ReRAM topologies with insulating layers are suggested to minimize leakage currents. The paper is finished with conclusion section. resistive switch consists of the copper contact, the bottom solid electrolyte and the bottom platinum contact. The upper resistive switch consists of the upper platinum contact, the upper solid electrolyte and the copper contact. When the CRS is exited by an AC voltage, its zero-crossing hysteresis loop is shown in Figure 1.b. Figure 1: a) The CRS, which is made of the anti - series connected memristive elements or resistive switches U and L, b) Idealized zero crossing current - voltage hysteresis loop of the CRS cell. If a resistive switch or a memristive element has a high resistance, it is in high resistance state (HRS) and, if it has a low resistance, it is in low resistance state (LRS). When the resistive switch U is in HRS and the resistive switch L is in LRS, the CRS state is logic 0. If the resistive switch U is in LRS and the resistive switch L is in HRS, the CRS state is logic 1. RON and ROFF are the maximum and the minimum CRS resistances respectively. They are given as roff And R, on ' rhrs + rlrs ' rlrs + rlrs (1) (2) Where Rhrs is the maximum resistance of a CRS switch (either U or L). RLRS is the minimum resistance of a CRS switch (either U or L). The maximum CRS resistance, ROFF, is a little higher than RHRS and almost equal to RHRS because of the high ratio between RHRS and RLRS. In [6], it has been shown that, 2 Complementary Resistive Switches under its threshold voltage, a CRS cell behaves as if a Anti-series connected resistive switches are called complementary resistive switches and used to minimize leakage currents in crossbar arrays. A detailed explanation for CRS topology can be found in [6]. The CRS cell model in [6] is also used within this study and redrawn in Figure 1. A resistive switch can be made of a solid electrolyte sandwiched between copper and platinum electrodes as shown in Figure 1.a. The lower linear resistor with a resistance value of ROFF. When a voltage whose magnitude less than the threshold voltage Vth1 is applied and it draws a low current and does not switch its state as shown in Figure 1.b. Reading a CRS cell of logic 1 destroys the cell state and it should be rewritten again [6]. However, the states of the CRS cells in sneak path are not destroyed. Using the CRS model, reading margin and leakage resistance of a 236 E. Karakulak et al; Informacije Midem, Vol. 44, No. 3 (2014), 235 - 241 one layer quadratic memory and a CB-3D-ReRAM will be inspected in the next section and the fourth section respectively. 3 The equivalent leakage circuit of a CRS based of one-layer quadratic memory A CRS based one layer NxN quadratic crossbar memory is shown in Figures 2 and 3. Its equivalent leakage circuit, given in [11,13], is shown in Figure 4. In Figure 4, Rsel is the selected cell resistance, Rpu is the pull-up resistor, and Rleak is the equivalent leakage resistance of one layer crossbar memory. The row number of the memory is designated as N and is equal to the column number of the memory. Equivalent leakage resistance decreases with increasing memory size (N2) and it is given as RLeak (2N - 1).R (N -1)2 OFF (3) Figure 2: One layer quadratic memory with CRS. Figure 3: Reading a cell of a CRS based one layer quadratic memory. The reading voltage is applied to the row, W, and the column, B... ' j ' k Figure 4: Equivalent circuit of a CRS crossbar array [11,13]. 4 A CRS based 3D resistive RAM and its equivalent leakage circuits for different layers A CB-3D-ReRAM structure is shown in Figure 5. It has L layers. It has either common rows or common columns between adjacent layers. Neighboring layers are constructed in an inverted manner. If only one cell at a layer is read at a time, that the top and the bottom layers shown in Figure 6 must have the same leakage because of symmetry. The equivalent circuit of an L layer CB-3D-ReRAM for reading/writing a cell which is at either the top or the bottom layers is shown in Figure 6. Its leakage resistance is found as (3N -1) R vOFF Leak (N -1). (2 N -1) (4) Figure 5: A CB-3D-ReRAM structure. 237 E. Karakulak et al; Informacije Midem, Vol. 44, No. 3 (2014), 235 - 241 Figure 6: Equivalent circuit of the CB-3D-ReRAM with L layers when a cell at the top or the bottom layer is read / written. It can be said that the reason of increasing number of layers not increasing sneak-path currents so much is the rest of unselected rows and columns have floating potentials and behave as equipotential surfaces. If a cell at a middle layer of the CB-3D-ReRAM is read (2 < P < L), its equivalent leakage circuit is shown in Figure 7. Its leakage resistance is found as R R. OFF 'Leak (N -1) (5) Figure 7: Equivalent circuit of the CB-3D-ReRAM when a cell at layer P, is read. For a middle layer: 2 < P < L. 5 Comparison of leakage resistance and reading margin for different layers of the CB-3D-ReRAM to that of one layer quadratic memory Equivalent leakage circuits of the different layers of the CB-3D-ReRAM are given in the previous section. The equivalent leakage resistances of one layer quadratic memory, the top, the bottom and the middle layers of the CB-3D-ReRAM are calculated and then normalized by the maximum CRS resistance. The normalized leakage resistances are shown in Figure 8. One layer quadratic memory has highest leakage resistance (the least leakage current). The middle layer of CB-3D-ReRAM has the lowest leakage resistance (the worst leakage current). The leakage resistance of the top layer of the CB-3D-ReRAM is same as that of the bottom layer. It is higher than that of a middle layer of the CB-3D-ReRAM and less than that of one layer quadratic memory. If N>>1, Eq. (3) can be approximated as Leak ~ ' N If N>>1, Eq. (4) can be assumed as equal to 3 R Rleak — vOFF 2 N (6) (7) Figure 8: Leakage resistances normalized by the maximum CRS resistance. If N>>1, Eq. (7) is only 25% less than the leakage resistance of one layer quadratic memory with CRS of the same size. Vpu, which is the voltage across the pull-up resistor R , can be found as v = — PU R R Pu + Rleak ! ! Rsel v read Pu (8) In this study, the pull-up resistor is chosen to be equal to R and the reading margin is defined as 238 E. Karakulak et al; Informacije Midem, Vol. 44, No. 3 (2014), 235 - 241 ay y_ - v„ y read (9) Where V is the voltage across the pull-up resistor R when min ^ 11 pu the cell has minimum resistance. V is the voltage across the pull-up resistor R when max ^ 11 pu the cell has maximum resistance. Vread is the reading voltage. Reading margins of an NxN one layer quadratic memory and the top/the bottom layer and a middle layer of an NxN CB-3D-ReRAM are calculated shown in Figure 9. The ratio of the maximum CRS resistance to the minimum CRS resistance, ROFF/RON is used as a parameter for all the drawings to show that both the reading margin and the leakage resistance go up when ROFF/ Ron increases. For the same size, one layer quadratic memory has the highest (the best) reading margin, the reading margin of a middle layer of the CB-3D-ReRAM has the worst reading margin, the reading margin of the top layer of the CB-3D-ReRAM is same as that of the bottom layer of the CB-3D-ReRAM and it is higher than that of a middle layer and less than that of one layer quadratic memory. After all, if the same memory size is divided into layers, the CB-3D-ReRAM becomes advantageous. As an example, the memory size is chosen to be 4 Mbit for both the CB-3D-ReRAM and one layer quadratic memory. The layer numbers of the CB-3D-ReRAM can be chosen to be 4, 16, and 64. As a function of the layer numbers, the reading margins are shown in Figure 10. The leakage resistances normalized by the maximum top layer leakage resistance are shown in Figure 11. Increasing the layer number results in a less leakage current for the CB-3D-ReRAM than that for one layer quadratic memory or a higher leakage resistance than that for quadratic memory for the same memory size as shown in Figure 11, the CB-3D-ReRAM shows a better performance for the same memory size but it is difficult to construct. On the other hand, it would increase both reading margin and leakage resistance, it is not practical to make the layer number higher than necessary considering manufacturing difficulties and cost issues. Accordingly, for the same memory size, it could be preferable to choose the number of layers of the CB-3D-ReRAM is 4 instead of 16 or 64. 6 Alternative CB - 3D - ReRAM Topology Suggestions Based on the findings of the last sections, alternative CB-3D-ReRAM topologies with insulating layer(s) can be suggested considering that insulating layers are go- Figure 9: Reading margins of the top or the bottom layer of the CB-3D-ReRAM, a middle layer of the CB-3D-ReRAM, and a one layer quadratic memory. ? 25 J - i | i i 1 1 1 1 / i 1 One Layer % Top/Bottom Layer of 3-D Ram —A— Middle Layer of 3-D Ram / / 1 1 4 I 1 1 1 30 40 layer number, L 64 Figure 10: Reading margins of the CB-3D-ReRAM layers and one layer quadratic memory for the memory size,N2,= 4 Mbit and ROFF/RON=1000. Figure 11: Normalized leakage resistances of the CB-3D-ReRAM layers and one layer quadratic memory when the memory size, N2, = 4 Mbit and R /R=1000. ing to less expensive in the future. Since the top and the bottom layers have higher equivalent leakage resistance than the middle layers with only one cell selected for reading, the number of the middle layers must be minimized for less leakage current during 239 E. Karakulak et al; Informacije Midem, Vol. 44, No. 3 (2014), 235 - 241 operation. The suggested new topologies are shown in Figures 12-14. The 3D RAM topology seen in Figure 12 is obtained placing one insulating layer after every other two layers, there is one insulating layer between two layers. As a result, it has the lowest leakage during its operation since it does not have any middle layers. Still, it needs insulating layers whose number are almost half of the crossbar layers and it might be the most expensive to produce among the topologies shown in Figures 12-14. The 3D RAM topology seen in Figure 13 is obtained placing one insulating layer after every other three layers, there is one insulating layer between three layers. For it has only one middle layer, its leakage current increases if the middle layer is read or written. Otherwise, its leakage is same as that of the topology given in Figure 12. If the topology is used, it has less insulating layers than that of the one in Figure 12 for a high number of crossbar layers. However, it has a higher leakage current with a probability of 1/3. The 3D RAM topology seen in Figure 14 is obtained placing one insulating layer after every other four layers, there is one insulating layer between four layers. Since it has only two middle layers, its leakage current increases if the middle layers are read or written. Otherwise, its leakage current is same as that of the topology given in Figure 12. If the topology is used, it has the least insulating layer among the ones given in Figures 12-14 for a high number of crossbar layers. Yet, it has a higher leakage current with a probability of 1/2. If the technique to make insulating layers become easier and less expensive, the results of the analyses done in this study can be used to develop new CB-3D-ReRAM topologies with less leakage current and higher reading margin. Figure 12: An alternative topology obtained placing one insulating layer after every other two layers, there is one insulating layer between two layers. Figure 13: An alternative topology obtained placing one insulating layer after every other three layers, there is one insulating layer between three layers. Figure 14: An alternative topology obtained placing one insulating layer after every other four layers, there is one insulating layer between four layers. 7 Conclusion Leakage resistances of different layers of a CB-3D-Re-RAM are examined using the equivalent circuits. It has been found that reading a cell at the top or the bottom layers of the CB-3D-ReRAM results in less leakage current than reading a cell at middle layers of the CB-3D-ReRAM. Leakage currents are same for all middle layers of the CB-3D-ReRAM. Leakage current of an NxN one layer quadratic memory is less than that of an L layer NxN CB-3D-ReRAM. However, the L layer memory array has less leakage current than a one layer quadratic memory for the same memory size when the layer number is more than or equal to four. Results show that the CB-3D-ReRAM for the same memory size and using 240 E. Karakulak et al; Informacije Midem, Vol. 44, No. 3 (2014), 235 - 241 just a few layers is a promising candidate for the future memories. Alternative CB-3D-ReRAM topologies with insulating layers are also suggested to minimize leakage currents during operation and they have less leakage current than the CB-3D-ReRAM examined at first. Besides, if the technique to make the insulating layers becomes cheaper, perhaps, the alternative topologies given in this paper can be used in the future CB-3D-ReRAMs. 8 References 1. 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Arrived: 26. 12. 2013 Accepted: 02. 07. 2014 241 Original scientific paper Journal of Microelectronics, Electronic Components and Materials Vol. 44, No. 3 (2014), 242 - 253 A New FGMOS FDCCII and Filter Applications Sinem Kele§1, Firat Kagar2, Hakan Kuntman1, Fatih Kele§3 Department of Electronics and Communication Engineering Istanbul Technical University, Istanbul, Turkey, 2Department of Electrical and Electronics Engineering, University of Istanbul, Istanbul, Turkey 3Department of Computer Engineering, University of Istanbul, Istanbul, Turkey Abstract: In this work, a new floating gate MOS (FGMOS) fully differential difference current conveyor (FDCCII) is presented. Employing FGMOS transistors two important advantages are introduced compared to conventional CMOS structure; firstly the input stage of the circuit providing the arithmetic calculations gets simpler, secondly the linearity range increases due to the properties of FGMOS differential amplifier. Furthermore, the versatility of the proposed FGMOS FDCCII is demonstrated on a filter circuit example. Both the FGMOS FDCCII circuit and proposed filter circuit are simulated with SPICE simulation program by using 0.35^m technology parameters. Simulation results show that the proposed building block can be used for the design of filters with high linearly properties. Keywords: FGMOS, FDCCII, Biquad Filter, Analog Integrated Circuits Nove možnosti uporabe FGMOS FCCII in filtrov Izvleček: V članku je predstavljen nov diferencialni MOS ojačevalnik s plavajočimi vrati (FGMOS). V primerjavi s klasično CMOS strukturo ima FGMOS dve prednosti: enostavnejša vhodna stopnja aritmetičnih izračunov in izboljšana linearnost zaradi lastnosti FGMOS ojačevalnika. Vsestranskost predlaganega FGMOS FDCCII vezja je predstavljena na primeru filtra. FGMOS FDCCII in vezje filtra sta simulirana v SPICE okolju v 0.35^m tehnologijo. Simulacije nakazujejo, da je predlagana struktura uporabna za načrtovanje filtrov z visoko linearnostjo. Ključne besede: FGMOS, FDCCII, biquad filter, analogna integrirana vezja * Corresponding Author's e-mail: fkacar@istanbul.edu. tr 1 Introduction Designing circuits suitable for differential signals leads to have more versatile applications. There are lots of filter topologies in electronics literature employing the extensions of second generation current conveyor like differential difference current conveyor (DDCC) [1-2], differential voltage current conveyor (DVCC) [3-4], inverting current conveyor (ICCII) [5], current controlled conveyor (CCCII) [6-7] and dual-X current conveyor (DXCCII) [8]. Current conveyors are one of the most useful building blocks in analog design. Many efficient applications can be designed with success using CCII as basic component. Anyway, second generation current conveyors, as they have been proposed, show some drawbacks. For example, only one of the input terminals presents a high impedance level. This can be a problem if differential signals have to be handled. To overcome this, a solution using more CCIIs has been proposed [9]. A different approach can be that to implement more complicated basic blocks, one of which will be presented in this paper. Fully differential difference current conveyor (FDCCII) may be considered as the most versatile building block that can be designed starting from the basic CCII. In fact, its topology can be thought as the "natural differential evolution" of the CCII idea. FDCCII circuit block combines the advantages and versatility of DDCC and DXCCII together. It has arithmetic signal processing capability of DDCC and gives opportunity to design filters with electronically tunable characteristics by utilizing two X terminals that is similar to DXCCII. FGMOS structures are also known as multi-input MOS and their multi input advantages make it simpler to realize an arithmetic signal processing circuit. The FGMOS drain current is proportional to the square of the weighted sum of the input signals. In the last few years, 242 © MIDEM Society S. Kele§ et al; Informacije Midem, Vol. 44, No. 3 (2014), 242 - 253 FGMOS transistors have found many applications in electronic programming [10], Op-amp offset compensation [11], D/A and A/D converters [12], inverters and amplifiers [13], voltage attenuators [14], current mirrors [15] and low voltage analog circuits [15]. Recently, an increased number of publications on the use of the FGMOS in analog computational circuits have been reported voltage squarers and multipliers [16-19]. In this paper, a new FGMOS FDCCII is proposed to obtain flexibility in analog IC design. By using FGMOS transistors the input stage of the circuit providing the arithmetic calculations gets simpler, also the linearity range increases due to the properties of FGMOS differential amplifier. The proposed FGMOS FDCCII is used in a filter circuit to demonstrate the versatility of the FDCCII block. Both the FGMOS FDCCII circuit and proposed filter circuit are simulated with SPICE simulation program by using 0.35um technology parameters. Simulation results show that the proposed circuit building block can be used to design filters with linearly tunable characteristics. Rest of the paper is organized as follows. In Section II, the basic structure of the FGMOS transistor is described. The principle of operation of the FGMOS FDCCII and simulation results of the proposed circuit are presented in Section III and Section IV, respectively. Proposed filter circuit, as an application example, is shown in section V followed by conclusion in section VI. 2 The FGMOS transistor_ Floating gate (FG) MOSFETs are being utilized in a number of new and exciting analog applications [17-20]. These devices are available in standard CMOS technology because they are being widely used in digital circuits. Thus floating gate devices are now finding wider applications by analog researchers. As a result, the floating gate devices are not only used for memories but are also being used as circuit elements. FGMOS transistors are used as analog memory elements, as part of capacitive biased circuits, and as adaptive circuit elements [20]. An FGMOS can be fabricated by electrically isolating the gate of a standard MOS transistor, so that there are no resistive connections to its gate. A number of secondary gates or inputs are then deposited above the floating gate (FG) and electrically isolated from it. These inputs are only capacitively connected to the FG, since the FG is completely surrounded by highly resistive material. So, in terms of its DC operating point, the FG is a floating node [20]. The equivalent schematic for an n-input n-channel FGMOS transistor is given in Figure 1. Figure 1: n-input n-channel FGMOS transistor 3 FGMOS FDCCII Starting from the first and second generation current conveyors, many types of new topologies have been designed during the past years. FDCCII is one of the most versatile circuit blocks which presents flexibility in analog circuit design with its arithmetic signal processing capability and gives opportunity to electronically tunable characteristics in application examples. 3.1 FDCCII Circuit Building Block FDCCII is characterized by four high-impedance input terminals (Y1, Y2, Y3 and Y4), two low-impedance node (X1 and X2) and four high-impedance output nodes (Z1, Z2, Zr and Z2,). Its block scheme and matrix characteristics are summarized below. Figure 2: FDCCII block representation 243 S. Kele§ et al; Informacije Midem, Vol. 44, No. 3 (2014), 242 - 253 'VX 1 " 1 -1 1 0 0 0 V y X 2 -1 1 0 1 0 0 IY1,2,3,4 = 0 0 0 0 0 0 IZ1,Z1' 0 0 0 0 ±1 0 Jz2,Z2' _ 0 0 0 0 0 ±1 V Y1 V Y 2 VY VY 1 X 2. (1) 3.2 FGMOS FDCCII Fig. 3a shows the CMOS FDCCII circuit while Fig. 3b shows the proposed floating gate fully differential difference current conveyor circuit employing FGMOS differential pairs instead of conventional MOS pairs to improve the circuit behavior. CMOS FDCCII circuit given in [21] employs three differential pairs in order to get the relationship of VX1 = VY1 - VY2 + VY3 and VX2 = - VY1 + VY2 - VY4. In FGMOS FDCCII circuit given in Fig. 3 only two FGMOS differential pairs are used to get both VX1 = VY1 - VY2 + VY3 and VX2 = - VY1 + VY2 - VY4. It is clearly seen that by using FGMOS transistors both the input stage of the circuit providing the arithmetic calculations gets simpler also the linearity range increases due to the properties of FGMOS differential amplifier [20]. In addition to these, new Y nodes can be added to FGMOS FDCCII circuit without any new transistors by only increasing the inputs of FGMOS transistors already used in differential pairs. This also reveals the flexibility of using FGMOS transistors in circuit blocks employing arithmetic calculations. FGMOS transistors in differential pairs have three inputs which are applied through equal sized capacitors, Ci. The input signals of VY1, VY2, VY3 and the control voltage VC are applied to one of the floating gates in the differential pairs. Since the voltage at the gate is less than the input voltage the differential pair transistors can work in saturation even when large signals are applied. This leads to increase the input dynamic swing. Determining parameters of voltage and current conveying properties are the slopes of related transistors and it is achieved easily by choosing matched transistors. Impedance values of X, Y, Z nodes of the FGMOS FDCCII circuit can be seen as small at X node because of feedback and high at Z nodes because of the drain nodes of related transistors. Figre 3a: CMOS FDCCII circuit Figure 3b: FGMOS FDCCII circuit 244 S. Kele§ et al; Informacije Midem, Vol. 44, No. 3 (2014), 242 - 253 Figure 4: FGMOS FDCCII DC voltage transfer characteristics (V-V and V-V) Figure 5: FGMOS FDCCII DC voltage transfer characteristics (VX1-VY2 and VX2-VY2) Figure 6: FGMOS FDCCII DC voltage transfer characteristics (VX1 -V) 245 S. Kele§ et al; Informacije Midem, Vol. 44, No. 3 (2014), 242 - 253 4 Simulation results The proposed circuit of Fig. 3 is simulated with SPICE by using 0.35^m TSMC technology parameters. The supply voltages are ±1.5V, VC is set to VDD and bias current IB = 10^A. The input capacitor values are taken C= 16,25fF while the C„n and C^c values are calculated as FGD FGS 0.2fF and 1.63fF, respectively. The dimension for n-type transistors is W / L = 0.7^m / 0.7^m and for p-type transistors is W / L = 1.4^m / 0.7^m. Fig. 4, Fig. 5, Fig. 6 and Fig. 7 show the DC voltage transfer characteristics of the proposed circuit with respect to VY1, Y2, Y3, Y4 input DC voltages. DC voltage VY1, Y2, Y3, Y4 is swept between -1.5V and 1.5 V while the DC voltage VX1 X2 is plotted. In Fig. 5, Fig. 6 and Fig. 7 while VYi is -1.5V, VX1 and VX2 take -1.49V and 1.4V, respectively/. While VYi is 1.5V, VX1 and VX2 take 1.4V and -1.49V, respectively. As it is seen from these values, input swing is almost equal to the supply voltages. Fig. 8 shows the DC voltage transfer characteristics of the proposed FGMOS circuit and the CMOS circuit [21] together. VX1 is plotted for both circuits. As it is seen from the figure, input swing is increased by using FG-MOS transistors. Fig. 9 and Fig. 10 show the DC current transfer characteristics of the proposed circuit with respect to IB bias current. DC bias current IB is swept between -10^A and 10^A while the DC output currents IZ1 Z1,Z2 Z2, are plotted. 2.0V 1.0V 0V -1.0V f .,..-.__ MOS (255.000m,274.1 & m) _ ...... " ' FGMOS ^^ (-324.000m.-330.1 (255.000m,248.229m) FGMOS (-324.000m.-337.179m) MOS -J -2.0V -1.5V -1.0V -0.5 V -0.0V Vyl 0.5V 1.0V 1.5V Figure 8: DC voltage transfer characteristics of the proposed FGMOS circuit and CMOS circuit 246 E. Karakulak et al; Informacije Midem, Vol. 44, No. 3 (2014), 235 - 241 Figure 9: FGMOS FDCCII DC current transfer characteristics lOuA Figure 10: FGMOS FDCCII DC current transfer characteristic Figure 11: FGMOS FDCCII AC voltage transfer characteristics (VX1-VY1 Y2 Y3) 247 S. Kele§ et al; Informacije Midem, Vol. 44, No. 3 (2014), 242 - 253 l.OKHz lOKHz lOOKHz 1.0MHz 10MHz Frequency Figure 12: FGMOS FDCCII AC voltage transfer characteristics (V -VY1 Y4) l.OKHz lOKHz lOOKHz 1.0MHz 10MHz Frequency Figure 13: FGMOS FDCCII AC current transfer characteristics l.OKHz lOKHz lOOKHz l.OMHz 10MHz Frequency Figure 14: FGMOS FDCCII AC current transfer characteristics 248 S. Kele§ et al; Informacije Midem, Vol. 44, No. 3 (2014), 242 - 253 Fig. 11 and Fig. 12 show the AC voltage transfer characteristics of the proposed circuit with respect to VX1 X2 and VY1, Y2, Y3, Y4. Fig. 13 and Fig. 14 show the AC current transfer characteristics of the proposed circuit with respect to IX1 X2 and IZ1, Z2, Z1', Z2" Impedance values of X1, X2, Y1, Y2, Y3 and Z nodes have been also determined as 1.46kO, 1.78kO, 1.43TQ, 1.36TQ, 1.43TO and 1.57MO, respectively. We considered VX1 (output) against VY1(input) at 10 MHz for THD (Total Harmonic Distortions) analysis. Fig.15 shows the THD variation of the proposed FGMOS circuit and the conventional CMOS circuit together during the input voltage swing of VY1 change between 1mV and 400mV which is common input voltage gap for FGMOS and CMOS circuits. Figure 15: Total harmonic distortion (THD) values of the proposed FGMOS FDCCII and MOS FDCCII 1bp2 _ C2G1S 1in GlG1 + C2Gls + CjC2s' 1hp _ CjC2 i2 1 in g1g2 + C2Gts + C1C2 s' Ilp g\g2 i in g1g2 + C2Gls + ClC2s Figure 16: The proposed current-mode biquad filter employing FDCCII. The resonance angular frequency u0 and the quality factor Q are given by Ic1C2 5 Proposed filter as application example In this section, current-mode and voltage mode two biquad filters have been presented. First proposed circuit is current-mode a biquad filter with single-input and three-outputs, which can simultaneously realize current mode low-pass, band-pass and high-pass filter responses employing all grounded passive components. The second proposed is voltag- mode biquad filter with three-inputs single-output, which can realize current mode low-pass, band-pass, high-pass, band-stop and all-pass filter responses employing single FDCCII. The proposed current-mode filter is shown in Fig.16. Routine analysis of these circuits, which single-input three-output yields the following current-mode filter transfer functions: 1BP1 _ C2Gls G1G2 + C2Gls + C1C2 s Q = . ¡G1C1 G2C2 7 The passive sensitivities of Q and u0 are given as follows, sq =-sq = sq = -sq =1 C sy=sy =-sy C2 2 G1 G 2 C -s 2 2 9 The second filter circuit can be used three-input singleoutput voltage-mode filter is shown in Fig. 17. Circuit analysis yields the following for the output voltage can be expressed as Vo = G1G2V -C2G2sV2 + C1C2s V3 GjG2 + C2G2 s + CjC2 s2 10 Depending on the status of the input voltages V1, V2, and V3, numerous filter functions are obtained. Special- 3 4 5 6 1 2 8 2 IN 249 S. Kelej et al; Informacije Midem, Vol. 44, No. 3 (2014), 242 - 253 ization of the numerator yields the following voltage-mode filter transfer functions for the circuits. (i) LP: V, =Vin and V2 =V3= 0, (ii) BP: V2 = Vin and V1 = V3=0, (iii) HP: V3 = V and V1 =V2 =0, v ' 3 in 1 2 ' (iv) BS: V1 = V3 = Vin, and V2 =0, (v) AP: V1 = V2 = V3 = Vi , v ' 1 2 3 in Figure 17: The proposed current-mode biquad filter employing FDCCII. The resonance angular frequency u0 and the quality factor Q are given by Q = . GG \jC1C2 per G2C2 11 12 The passive sensitivities of Q and w0 are given as follows, sQ =-SQ = SQ =-SQ =1 C C2 2 S®0 = = I G G '2 C C2 2 13 14 The current-mode biquad in Fig. 16 was designed for f0 = 10 MHz by choosing R1 = R2 = 75kO, C1 =0.3pF and C2=0.15pF. Simulated response of high-pass, band-pass and low-pass filters topology shown in Fig. 18. For voltage mode filter in Fig. 17 has been design to provide high-pass, band-bass, low-pass, band-stop and all-pass responses with f0 = 9.73 MHz. The passive component values are chosen as R1 = R2 = 75kO, C1 =0.3pF and C2=0.15pF. In Fig. 19 shows the simulated frequency responses for the high-pass, band-pass, low-pass, all-pass and band-stop configurations. As can be seen, there are a good agreement between theory and simulations. Time domain analysis result is given in Fig. 20 for peak-to-peak 20 pA, 10 MHz sine wave input for current Frequency Figure 18: The simulated results of the gain-frequency responses of proposed curret-mode biquad filter 250 1 2 S. Kele§ et al; Informacije Midem, Vol. 44, No. 3 (2014), 242 - 253 OdB -20dB -40dB -60dB BP LP / (9.818M,-27.619) 300KHZ 1.0MHz 3.0MHz 10MHz 30MHz 100MHz 240MHz Frequency Figure 19: The simulated results of the gain-frequency responses of proposed voltage-mode biquad filter Figure 20: Time domain response of curret-mode filter mode low-pass, band-pass and high-pass filters configuration for the circuit in Fig. 16. Time domain analysis result is given in Fig.21 for peak-to-peak 2V, sine wave at 9.73MHz input for voltage-mode low-pass filter. The large signal behavior of the circuit was tested by investigating the low-pass response on the input signal amplitude. Fig. 22 shows the frequency response of curent-mode band-pass filter at 0°C, 25°C, 50°C and 100°C. As it is seen from the graphic frequency response of the filter almost does not change with respect to the temperature. 6 Conclusion A new FGMOS FDCCII has been designed and simulated. By using FGMOS transistors both the input stage of the circuit providing the arithmetic calculations gets simpler also the linearity range increases due to the properties of FGMOS differential amplifier. The proposed FGMOS FDCCII is used in a tunable filter circuit in order to show the versatility of the FDCCII block. We can conclude that proposed FGMOS FDCCII structure provides the circuit designer further possibilites of realizing active circuits by reducing the number of transistors and extending the linearity range. 251 S. Kele§ et al; Informacije Midem, Vol. 44, No. 3 (2014), 242 - 253 Figure 21: Time domain response of voltage-mode low-pass filter Frequency Figure 22: Frequency response of curent-mode band-pass filter at 0°C, 25°C, 50°C and 100°C 7 References 1. W. Chiu, S.I. Liu, H.W. Tsao and J.J. Chen, "CMOS differential difference current conveyors and their applications', IEE P. Circuits, Devices Syst., vol.:143, pp. 91-96, 1996. 2. M.A. Ibrahim, H. Kuntman and O. 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Arrived: 10. 03. 2014 Accepted: 22. 06. 2014 253 Boards of MIDEM Society | Organi društva MIDEM midem Executive Board | Izvršilni odbor midem President of the MIDEM Society | Predsednik društva MIDEM Prof. Dr. Marko Topič, University of Ljubljana, Faculty of Electrical Engineering, Slovenia Vice-presidents | Podpredsednika Prof. Dr. Barbara Malič, Jožef Stefan Institute, Ljubljana, Slovenia Dr. Iztok Šorli, MIKROIKS, d. o. o., Ljubljana, Slovenija Secretary | Tajnik Olga Zakrajšek, UL, Faculty of Electrical Engineering, Ljubljana, Slovenija MIDEM Executive Board Members | Člani izvršilnega odbora MIDEM Prof. Dr. Slavko Amon, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Darko Belavič, In.Medica, d.o.o., Šentjernej, Slovenia Prof. Dr. Bruno Cvikl, UM, Faculty of Civil Engineering, Maribor, Slovenia Prof. DDr. Denis Donlagič, UM, Faculty of Electrical Engineering and Computer Science, Maribor, Slovenia Prof. Dr. Leszek J. Golonka, Technical University Wroclaw, Poland Leopold Knez, Iskra TELA d.d., Ljubljana, Slovenia Dr. Miloš Komac, UL, Faculty of Chemistry and Chemical Technology, Ljubljana, Slovenia Prof. Dr. Miran Mozetič, Jožef Stefan Institute, Ljubljana, Slovenia Jožef Perne, Zavod TC SEMTO, Ljubljana, Slovenia Prof. Dr. Giorgio Pignatel, University of Perugia, Italia Prof. Dr. Janez Trontelj, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Supervisory Board | Nadzorni odbor Prof. Dr. Franc Smole, UL, Faculty of Electrical Engineering, Ljubljana, Slovenia Mag. Andrej Pirih, Iskra-Zaščite, d. o. o. , Ljubljana, Slovenia Dr. Slavko Bernik, Jožef Stefan Institute, Ljubljana, Slovenia Court of honour | Častno razsodišče Emer. Prof. Dr. Jože Furian, UL, Faculty of Electrical Engineering, Siovenia Prof. Dr. Radko Osredkar, UL, Faculty of Computer and Information Science, Slovenia Franc Jan, Kranj, Slovenia Informacije MIDEM Journal of Microelectronics, Electronic Components and Materials ISSN 0352-9045 Publisher / Založnik: MIDEM Society / Društvo MIDEM Society for Microelectronics, Electronic Components and Materials, Ljubljana, Slovenia Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale, Ljubljana, Slovenija www.midem-drustvo.si