Original scientific paper
Informacije
^efMIDEM
A Innrnal of
Journal of Microelectronics, Electronic Components and Materials Vol. 44, No. 2 (2014), 159 - 167
Voltage summing current conveyor (VSCC) for oscillator and summing amplifi^er applications
Sezai Alper Tekin
Department of Industrial Design Engineering, Erciyes University, Kayseri, Turkey
Abstract: In this paper, a voltage summing current conveyor (VSCC) as an active building block for realizing the controlled oscillator and the summing amplifier applications has been presented. The VSCC required low supply voltage as ± 0.5 V consumes low power and has a simple structure. The controlled oscillator has three passive components. The VSCC based oscillator offers using of the grounded capacitors which are suitable for IC implementation, using the less passive components, very good frequency stability and the low voltage operation. In addition, the summing amplifier has been realized using only one VSCC and a grounded passive resistor. The amplifier provides some advantages such as high accuracy and very high input impedance. The performance of the proposed circuit is simulated with SPICE to confirm the presented theory.
Keywords: Current conveyor, oscillator, voltage summing circuit, low-voltage, floating gate MOS
K^rmiljen tokovni ojačevalnik za realizacijo oscilatorjev in napetostnih seštevalnikov
Izvleček: V članku je, kot aktivni gradnik, predstavljen krmiljen tokovni ojačevalnik (VSCC) za realizacijo oscilatorjev in napetostnih seštevalnikov. Zahtevana nizka napajalna napetost ± 0.5 V zagotavlja nizko porabo in enostavno zgradbo. Krmiljen oscilator ima tri pasivne elemente. Oscilator na osnov VSCC nudi, ob uporabi ozemljenih kondenzatorjev in manj pasivnih elementov, dobro frekvenčno stabilnost in nizkonapetostno delovanje. Seštevalni ojačevalnik je realiziran le z enim VSCC in ozemljenim pasivnim uporom. Ojačevalnik nudi visoko natančnost in zelo visoko vhodno impedanco. Predlagano vezje je simulirano v SPICE okolju.
Ključne besede: tokovni ojačevalnik, oscilator, napetostni seštevalnik, nizkonapetostno vezje, MOS s plavajočimi vrati
" Corresponding Author's e-mail: satekin@erciyes.edu.tr
1 Introduction
In recent years, differential difference current conveyor (DDCC) has been reported [1]. In [2], this circuit has been improved to the differential difference complementary current conveyor (DDCCC) [3]. The differential voltage current conveyor (DVCC) was proposed in [4], which could be realized using a DDCCC (grounding terminal Y3 of a DDCCC results in a DVCC). Numerous applications employing DVCC and DDCC have been proposed earlier [5-9]. Although there are various circuit topologies using voltage summer [10-13], it has not been shown in any active block using current conveyor implementing only voltage summing. Also, the voltage summing current conveyor can be realized with using DDCC. A current conveyor providing arithmetic operations has already been presented by Kuntman [9]. The linearity range of the circuit has been increased due to the properties of the FGMOS differential pair. How-
ever, such a complex circuitry structure has not been required for voltage summing function and also, the circuit has no tunability.
The sinusoidal waveform is an important function in electronics systems. The sinusoidal oscillators are commonly utilized in signal processing circuits, communication, control and measurement systems, etc. Therefore, several sinusoidal oscillators using operational amplifier (Op-Amp) have been introduced in the literature [14, 15]. On the other hand, the op-Amp allows the limited gain-bandwidth product. Thus situated, both the condition of the oscillation (CO) and the oscillation frequency of the oscillators designed using op-Amp are negatively affected. For this reason, these oscillators are not suitable for operating at higher frequencies [16]. Lately, current-mode circuits have been attracted
attention due to having advantages such as wide bandwidth, simple circuit structure, wider dynamic range and low power dissipation [17]. In this context, there are many controllable oscillators with two or more active elements or employing only one active element such as current conveyor (CC), transconductance amplifier (OTA), current differencing transconductance amplifier (CDTA) and differential voltage current conveyor transconductance amplifier (DVCCTA) in the literature [18-22]. It can be seen that the above mentioned performance parameters of the current-mode circuits, especially total power dissipation, have been gone the worse when the more active elements have been used in the designing circuit. Although one active element has been used in design, the circuit structure using as an active element can be included a lot of components. Thus, both using less components and designing at low-voltage have been aimed recently [5, 23].
The summing amplifiers and the difference amplifiers using generally Op-Amp and the current conveyor have been presented in the previous studies [12, 24]. The circuit proposed in 2003 uses only three CCCIIs to realize the functions which are current variable by the bias currents of the conveyors [11]. It is shown that the dynamic range and the linearity of the circuit are not sufficient. Also, it has utilized a high supply voltage as ± 2.5 V. The designed circuits using Op-Amp usually suffers from having lots of passive components and restricted frequency performance of the circuit [16].
In this study, a voltage summing current conveyor (VSCC) for realizing the controlled oscillator and the summing amplifier applications has been presented. Therefore, the purpose of this paper is to introduce a proposed VSCC as a new approach and to show the usability of its applications as a controlled oscillator and a summing amplifier. The VSCC has a simple structure and a good frequency performance. Besides, this circuit required low supply voltage as ± 0.5 V consumes low power. The controlled oscillator has three passive components (one grounded resistor and two grounded capacitors). This oscillator offers using of grounded capacitors which are adorable for IC implementation in a long side eliminating parasitic capacitances, using the less passive components, very good frequency stability and the low voltage operation. Additionally, the summing amplifier has been implemented using merely one VSCC and a grounded passive resistor. The amplifier exhibits high accuracy and very high input impedance. Finally, the functionality of the proposed circuit has been confirmed by the SPICE simulations.
2 Proposed Voltage Summing Current Conveyor
The VSCC is designed by employing floating gate MOS transistors (FGMOS). The symbol and the equivalent circuit of an n-type FGMOS transistor with three inputs are shown in Fig. 1. There are several models to simulate the FGMOS transistors in [25]. The model of the FG-MOS used in proposed circuit is based on connecting capacitors in parallel with the resistors as given in [26].
Figure 1: The n-type FGMOS transistor with three inputs a) symbol, b) equivalent circuit
FG1, FG2 and FG3 are the input gate terminals of the FGMOS transistor as displayed in Fig. 1. The input capacitances are CFG1, CFG2 and CFG3 and the input gates are coupled to floating gate of the FGMOS. CFGD, CFGS and CFGB are the parasitic capacitances between the drain, source, bulk and gate, respectively. Input gate voltages and drain, source and bulk voltages affect an effective floating gate voltage in proportion to value of the coupling capacitances. CT, sum of all the capacitances between the floating gate and the other terminals can be written as
CT = CFGD + CFGS + CFGB + CFG\ + CFG 2 + CFG3
(1)
Assumed that the relation shown in Eq.1 is CFGD + CFGS + CFGB << CFG1 + CFG2 + CFG3, then the total capacitance is approximately equal to CFG1 + CFG2 + CFG3. Here, VFG is the effective floating gate voltage and it can be defined as
V _ CFG1 VFG1 + CFG2VFG2 + CFG3VFG3 (2)

The drain current IDS of the FGMOS transistor in satura-
tion region is expressed as
^DS =
k
" [Vfg - Vs - VTH
2
(3)
where VFG is the effective floating gate voltage, VS is the source voltage, IDS is the drain current and VTH is the threshold voltage of the FGMOS transistor. In addition,
kn known as transconductance parameter is .Cox. (W/L) where is the electron mobility, Cox is the gateoxide capacitance per unit area, W/L is the aspect ratio of the FGMOS transistor.
The block diagram of the voltage summing current conveyor as a new approach is demonstrated in Fig. 2.
Figure 2: The block diagram and the equivalent circuit of the VSCC.
For the VSCC, Y terminals have high input impedances. The input impedance of the port X is a parasitic resistance and the resistance value can be easily adjusted by bias current I0 of the VSCC. The Z terminals have high output impedances. The matrix equations of the VSCC are defined as follow:
(4)
The circuit structure of the active block as introduced the FGMOS transistor based VSCC is shown in Fig. 3.
Vx		Rx	1	1	0		Ix
Jyi		0	0	0	0		VY 1
ly 2		0	0	0	0		Vy 2
Jz _		± 1	0	0	0		. Vz
Figure 3: The circuit structure of the VSCC.
In Fig. 3, VFGS1 and VFGS2 are the floating gate-source voltages terminal for M1 and M2 transistors, respectively. The effective floating gate voltages of M1 and M2 transistors are VFG1 and VFG2. A loop equation written from floating gate of M2 to floating gate of M1 transistor can be expressed as
VFG 2 VFGS 2 + VFGS1 VFG1 = 0
(5)
If it is assumed that C = C = C = C , C can be ob-
hG1 hG2 hG3 FG I
tained as 3CFG shown in Eq. 6. The gate-source voltages in (5) are given as
VFGi = 3 (VY 1 + VY 2 + Vc) Vfg 2 = (Vx + Vc)
(6)
where VC is used for operating the FGMOS transistors at lower voltages. If Eq. 5 is arranged, it can be written as below.
Vfgs2 - VFGSi = 3 {Vx - Vn - Vy2)
(7)
The drain currents of transistors M1 and M2 can be written as,
1 W
3 {Vyi + VY 2 + Vc)-VTH
Id 2 =1 k„(Wi 1 (Vx + VC )-V^
2 L
TH
(8.a)
(8.b)
and are the drain currents of transistors M1 and M2, respectively. VX- (VY1+VY2) = VXY. The relationship between input voltages can be calculated as
VxY = 3
10 + Ix
^kn [W/L) i kn (W/L)
10 - Ix
(9)
where I0 is the biasing current of the differential pair. From equation (9), current IX shown in figure 3 can be written as
Ix =1 Vx^.Jk„(W/L)J2/0 -1 k„(W/L)(Vxy)'
(10)
In equation (10), it is assumed that 2I0 >> kn(W/L)(VYX)/2 for a small input voltage. Using this approximation, the output current IX of the differential pair is obtained as
Ix = 3 Vx^^ ^ k„(W/L)^2ro
(11)
From Equation (11), parasitic resistance of the circuit will be expressed as
R ~ VxY -
3
Viokn (W/L)
(12)
The parasitic resistance is easily controlled by biasing current. It is clear that the electronic tunability of the resistance is presented by this circuit.
3 Simulation results
The proposed VSCC was simulated by SPICE to confirm the theoretical approaches. The SPICE model 0.13 ^m TSMC CMOS technology parameter is used for the NMOS and the PMOS transistors. The aspect ratios of the MOS transistors, occurred in the VSCC implementation, are illustrated in Table I. The supply voltage is ±0.5 V. The value of the capacitances shown in Fig. 1 (b) as
Cfg„ C
FG2 and CFG3 can be taken as 0.07 pF.
Table 1: The aspect ratio of the MOS transistors.
Transistor	W (^m)	L(^m)
M1, M2	0.78	0.26
M3,M4,M6,M7,M8,M10,M 11,M12	2.6	0.26
M5,M9,M13,M14	6.24	0.26
Figure 4 displays the changing of the input voltage VY1 versus voltage VX for the proposed VSCC.
Figure 4: The voltage transfer curve for the VSCC.
The graph has been obtained for the different values of the voltage VY2 as shown in Fig. 4. The curve which has highly linear characterization shows that the voltage transfer gain of the VSCC (VX/(VY1 + VY2)) is equal to 0.99. This value is more satisfactory according to the some designs presented in early studies [27-29]. The changing of the input current Ix versus current Iz for the VSCC is depicted in Fig. 5.
The current gain between terminal X and terminal Z is 0.98. The current transfer curve of the VSCC has almost unity current gain (Iz / Ix). Also, the transfer of current is linear from X to Z node. Figure 6 displays the frequency response for the voltage transfer gain (VX / VY1).
Figure 5: The current transfer curve for the VSCC.
100 Hz 1kHz 10 kHz 100 kHz 1MHz 10 MHz 100 MHz 1 GHz
Frequency
Figure 6: The frequency response of the voltage transfer gain for the proposed circuit.
The frequency response of the VSCC is shown in figure 6 giving bandwidth of 80.1 MHz. The frequency response of the current transfer gain for the VSCC is shown in figure 7. This figure is valid for the all Y terminals having same inputs capacitance values.
Figure 7: The frequency response of the current transfer gain for the proposed circuit.
The cut-off frequency (-3 dB) is about 211.6 MHz as shown in figure 7. The performance parameters of the VSCC is shown in Table II.
Table 2: The parametric characteristics of the VSCC.
Parameters	Values
Supply voltage	±0.5V
Input voltage range	±300 mV
Output current range	±35^A
Voltage transfer gain (VX/(VY1+VY2))	0.99
Current transfer gain (Iz/Ix)	0.98
3 dB bandwidth Iz/Ix	211.6 MHz
3 dB bandwidth Vx/Vy1, Vx/Vy2	80.1 MHz
Rx adjustable range (Io = 1 ^A - 35 ^A)	14kQ-2.1MQ
Y1 and Y2 input resistance	10 GQ
Z Output resistance	40 MQ
Power dissipation (I0 = 25 ^A)	61 ^W
The parameters of the proposed circuit according to the Table II are reasonable values. The proposed circuit offers some advantages such as described in below.
1.	Low-voltage supply requirements about ±500 mV.
2.	Low power consumption 61 mW.
3.	Acceptable current and voltage gain bandwidth product close to 211.6 MHz and 80.1 MHz, respectively.
Electronically tunable intrinsic resistance having wide range.
Very high Z-output resistance. Simple circuit design.
A new approach which has some advantages.
4 Controlled oscillator based on VSCC
A controlled oscillator based on VSCC shown on Figure 8 is introduced to demonstrate the usability of the proposed VSCC.
Figure 8: A controlled oscillator based on VSCC.
The circuit consists of single VSCC, one passive resistor and two grounded capacitors. The characteristic equation of the proposed circuit is formulated as below
s2 + s
RxCj + RiCi — RiC 2
RXR1C1C2
+
1
RXR1C1C2
= 0 (13)
where RX is the intrinsic resistance of all the current conveyors. From figure 15, input current Iin is equal to current I2. From equation (11) the oscillation frequency of the oscillator and the condition of oscillation (CO) can be obtained as
fo =
1
RxRiCiC2
CO .	+ RxC2 < 1
RIC2
(14)
(15)
Taking into consideration both the voltage and the current tracking errors of the current conveyors, ß=1 - eV denotes voltage tracking error from X to the Y terminals; a=1 - e, denotes current tracking error from X to the Z terminal where ß and a are the voltage and the current transfer gains, respectively and eV and e, are the voltage and the current transfer errors of the VSCC, respectively. In this situation, the frequency of oscillation can be calculated as
fo =
1
ßa
(16)
RXR1C1C2
Figure 9 represents the voltage output of the oscillator.
Figure 9: Oscillator output
Controlled oscillator based on VSCC shown in Figure 8 was simulated with the following values for the passive components C1, C2 and R1 are equal to 1 pF, 5 pF and 40 KQ, respectively, using the value: 25 ^A for I0. Thus, the simulated oscillation frequency value is 2.757 MHz. When this value is theoretically calculated from Eq. 14, the oscillation frequency is obtained as the value of 2.8 MHz. This small difference results from the voltage and the current transfer errors of the VSCC. Figure 10 shows the variation of the oscillation frequency for different biasing currents.
The curves have been obtained both theoretically and simulated using the values: 10, 15, 20, 25, 30 and 35 ^A for I0. The curves shown in Figure 10 exhibit a good coherence with each other. Also, the oscillation frequency between 1.89 MHz and 3.28 MHz is easily controlled by biasing current, and further, total harmonic distortion (THD) of the proposed circuit is less than 2 %.
15 20 25 30 Biasing Current (|jA) Figure 10: Oscillator frequency versus biasing current.
5 Summing Amplifier
The proposed summing amplifier circuit is shown in Fig. 11. As it is seen from Fig. 2, the circuit whose Port X and Port -Z are connected to each other contains one passive resistor.
1.0 1.2 1.4 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 t(ns)
Figure 12: Sinusoidal voltage waveforms for the amplifier.
The transfer function of the summing amplifier shown in Figure 10 is written as,
=
Vout(t)
R2
Vi(t) + V2 (t) Rx
(17)
Figure 11: The summing amplifier with two inputs.
The simulation of the summing amplifier using VSCC shown in Fig. 10 has been done. Besides, voltage waveforms of the circuit is shown both simulation and theoretical in Fig. 12. The value of the passive resistor is 31 KQ and the intrinsic resistance R is taken as 15.5 KQ. As
x
shown in Figure 12, voltage v1(t) and voltage v2(t) are chosen at 1 MHz 30 mV and 20 mV, respectively.
Sum of the voltages is named vout(t) as shown in Figure 12. On the other hand, the voltage gain of the amplifier can be obtained as 2. The simulation results almost correspond with theoretical results. Maximum error of the gain is about 1 % for Vout = ± 300 mV. However, the error of the gain is 0.1 % for -100 mV < Vout < +100 mV. Additionally, DC output offset voltage and total power dissipation of the amplifier are 329 ^V and 79.8 ^W, respectively. The frequency responses of the amplifier for
Table 3: The comparison between this study and the others.
Parameters	This study	[30]	[31]	[32]	[33]
Supply voltage	± 0.5 V	± 1.35 V	± 2.5 V	± 15 V	5 V
Input voltage range	± 250 mV	-2.5 V, + 5.5 V for Vs* = +5 V	NA	± 10 V	NA
Output voltage range	± 300 mV	(+Vs) - 0.35 V (-Vs) + 0.3 V	± 280 mV	± 10 V	NA
DC offset voltage	329 ^V	250 ^V	25 mV	100 ^V	150 mV
Total voltage noise	13.89 nV/VHz	87 nV/VHz	NA	60 nV/VHz	212 nV/VHz
Power dissipation	79.8 ^W	NA	40 mW	NA	1068 mW
Bandwidth	61.3 MHz	800 kHz	NA	1 MHz	20 kHz
Gain Error	1 %	0.1 %	NA	NA	NA
Input impedance	10 GQ	80 kQ	NA	1 MQ	NA
Electronically Tunability	Yes	No	No	No	No
*VS : Supply voltage
different biasing current are displayed in Figure 13. The biasing current is changed from 20 ^A to 30 ^A step by step with 5 ^A. The cut-off frequencies of the considered amplifier have been obtained as 54.5 MHz, 61.3 MHz and 66.4 MHz for 20 ^A, 25 ^A and 30 ^A, respectively.
Figure 13: Frequency responses of the amplifier for different biasing current (V z/Vy1+Vy2).
A noise analysis of the summing amplifier was performed in SPICE. Therefore, with respect to SPICE results, the noise curve belonging to the total output voltage of the amplifier is given in Fig. 14. Total voltage noise of the proposed circuit can be obtained as 13.89 nV/VHz for I0=30 ^A.
Figure 14: The total output voltage noise versus frequency.
When the literature is investigated, it has been seen that there are a lot of Op-Amp based summing amplifier as an IC structure. Their summing amplifier IC products and proposed amplifier displayed in Table III are compared with each other.
The frequency performance of the presented circuits is restricted as shown in Table III. The circuits have no electronically tunability. Also, these circuits have low input impedance of about KQs. On the other hand, the proposed amplifier has high input resistance. The obvious advantage is the high input resistance of the proposed circuit reducing the loading on the input signal sources, and therefore affords better signal accuracy
and linearity. When the low value input resistors are used, the input leakage currents to the amplifiers significantly are higher than the lowest input signal currents available such that the accuracy of the summing amplifier is not preserved. The multi-input summing amplifier which has four inputs shown in Figure 15 can be given as an example.
Figure 15: The multi-input summing amplifier.
The voltage output of the circuit can be calculated as below.
Vout(t) = [vi(t) + V2 (t) + V3(t) + V4 (tj\ (18) Rx
The voltage gain of the circuit can be controlled by intrinsic resistance Rx shown in Equation 18. This situation is an important advantage in the electronic circuit design.
6 Conclusion
In this paper, a new approach called voltage summing current conveyor for realizing controlled oscillator and summing amplifier applications has been presented. Simulation results done by SPICE confirm the validity of the theory and demonstrate the use of the VSCC in the controlled oscillator and the summing amplifier applications. FGMOS based the proposed circuit which has highly linear characterization shows that voltage transfer gain and current transfer gain are equal to 0.99 and 0.98, respectively. These values are admirable. Moreover, the frequency responses of the VSCC are acceptable levels. This VSCC is designed in 0.13 ^m CMOS process and has ± 0.5 V supply voltage. The linear electronically tunable intrinsic resistance can be tuned for the resistive value from 14 kQ to 2.1 MQ. The simulation
results show that this design is powerful sufficient to be utilized in the proposed circuit to achieve low-voltage and low-power. The controlled oscillator used as an application has a stable sinusoidal output. Furthermore, the oscillation frequency value can be controlled by the biasing current. As another application, the summing amplifier having high input resistance and controllable gain has been introduced.
Finally, such an active element is rather proper for low-voltage and low-power IC realizations of which results in decreasing of power consumption. That's why it is clearly shown that the proposed circuit can be used in general electronic circuit design as an active element which has different features such as voltage summing operation.
V
7
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Arrived: 13. 11. 2013 Accepted: 11. 02. 2014