DEBUG AND DIAGNOSIS: MASTERING THE LIFE CYCLE OF NANO-SCALE SYSTEMS ON CHIP Hans-Joachim Wunderlich, Melanie Elm, Stefan Holst Institut für Technische Informatik, Universität Stuttgart, Stuttgart, Germany INVITED PAPER MIDEM 2007 CONFERENCE - WORKSHOP ON ELECTRONIC TESTING 12.09. 2007 - 14.09. 2007, Bled, Slovenia Key words: Diagnosis, Debug, Embedded Test Abstract: Rising design compiexity and shrinl1 Model: A B & cs@l condition(cs@l) = A+B Fig. 1: Example of a conditional stuck-at fault Among all the approaches to describe malfunctioning designs by fault models, there is no fault model matching every possible design fault. The last step in implementation is the final layout of a design. Layouts are verified by extracting a netlist and debugging the extracted netlist with the same design debug methods used before. 2.3 Prototyping With the masks from the implementation phase, first chips are produced. Due to various unknown effects, not all of the prototypes produced will work properly. This problem is getting more severe with shrinking structures, as now systematic and random variations are increasing. In consequence, the actual behavior of physical chips gets more and more difficult to predict and simulate /11/, and additionally it is harder to decide whether a device works within a given specification or not /12/. A physical disorder which leads to a behavior different from the implementation is called a defect. Systematic defects must be identified and avoided by altering the design or the process parameters. The new behavior of the internal signals due to a present defect is called a fault. In recent technologies, the complexity and variety of possible faulty behaviors is increasing, and fault models cannot reflect reality any more. The increasing variations in nano-scale silicon lead to complex defect mechanisms, hence the actual behavior of faulty chips and designs becomes not only difficult to predict but also difficult to model /13/, /14/, /15/. Rising variations for instance lead to lower signalto-noise ratios, to complex defect mechanisms and indeterministic behavior. Stuck-at, delay, bridging and statistical fault models are used today in commercial tools. However there are strong efforts towards a fault model independent diagnosis. Defects can also be expressed in conditional stuckat faults as long as they result in a combinational malfunction. Figure 2 shows an example of a bridge or short. However like in design debug, a fault model which can describe all possible defect mechanisms is unknown. Fault models must be determined by the diagnosis algorithm itself to describe the defect mechanisms. As an additional precondition for diagnostic algorithms, a high diagnostic resolution has to be provided to find exact defect mechanisms to guide the physical inspection accurately. Faulty circuit: l^odel: A A Condition: B=1 Condition: A=1 B 2.4 Manufacturing "Time-to-volume" and "time-to-market" are essential for the economic success of a product. "Yield ramping" is a traditional application area of diagnosis as it is used to find yield limiters. Modern manufacturing processes strongly interact with the design characteristics. This necessitates yield learning for each new design. Adapting process and product requires analysis of root causes for failures and outliers /16/, /17/. The extracted knowledge is used to support yield ramping and yield learning in advanced process technologies by improving design for manufacturability /16/. Prior to expensive diagnosis and physical failure analysis, spot defects must be ruled out by volume diagnosis. In volume diagnosis, test data of a large number of failing chips are recorded and analyzed to find yieldlimiting systematic defects and design issues. Diagnostic data from a single chip is not sufficient since systematic problems need to be differentiated from sporadic random defects. First attempts to establish standards in volume diagnosis have been made /18/. Research in this area is quite mature, nevertheless with growing design complexity again new problems arise. Complex designs need more patterns to test and testing time is a crucial cost factor. Additionally in modern designs many cores are deeply embedded and test access is a severe problem. The test-solution developed aiming at this issue is built-in self test (BIST). BIST reduces traffic and helps cutting testing time, and many chips can be tested in parallel on one tester. However, classic BIST infrastructures may limit the visibility from outside and gathering diagnostic data may become more difficult. Often, only very limited diagnostic information is available like the number of the first failing pattern. 2.5 Support Even after successful manufacturing, diagnostic techniques are needed to detect and locate defective modules /19/ before repair. As customer satisfaction and warranties are a strong economic factor, the diagnosisinfrastructure of a silicon product facilitating diagnosis in field is also of great importance. Fig. 2: Example of a conditional stuck-at fault modeling a resistive bridge On a chip, there can be faults in combinational logic, in scan chains or in the clock tree. Finding possible defect locations in random logic based on the observed behavior of the chip is called logic diagnosis. Logic diagnosis together with scan chain diagnosis and interconnect (bus, network) diagnosis forms the precision diagnosis. 3 Logic debug and diagnosis Logic debug and diagnosis is concerned with finding the most reasonable root causes within a random logic network that explain the failing flip-flops of this circuit as good as possible. This circuit can either be a design containing errors or a core on a chip with defects. The only difference is that the root causes are induced by different defect or error mechanisms. The traditional way to tackle these root causes first to create simple fault and error models to cut on the complexity of the problem, and then to develop special debug and diagnosis algorithms for each of these models. Due to rising complexity of possible defect mechanisms, new approaches are currently explored which are not restricted to a specific fault or error model. Such algorithms are based on the observation, that simple, local defect mechanisms are more reasonable root causes than complex, distributed ones. An easy metric for resonability is provided by the number of conditional stuck-at faults needed to explain all failures. This observation holds for both, design errors and physical defects. Therefore fault model independent approaches are suitable for both, design debug and logic diagnosis. Design debug and logic diagnosis have the common goal of not only deriving possible root causes but also to keep the number of suspects as low as possible: The lower the number of returned suspects, the higher the achieved diagnostic resolution. The applied test set itself determines the achievable resolution by the number of faults which cannot be distinguished any further /20/, /21 /, /22/. The effectiveness of pattern response analysis algorithms is evaluated by comparing the achieved diagnostic resolution to the resolution of the test set. Pattern response analysis algorithms are divided into cause-effect and effect-cause approaches. These two fundamental paradigms will be discussed in the next two subsections. Most debug and diagnosis methods employ at least one of these approaches and some even combine pattern analysis with diagnostic ATPG to provide maximum diagnostic resolution. This concept is called adaptive diagnosis and is covered in the third subsection. 3.1 Cause-Effect Analysis In cause-effect analysis, a fault model is chosen to enumerate all possible root causes in a circuit. Fault simulation is performed on each fault in the model, and the behavior is matched with the failing responses observed /23/, /24/. To cut on simulation time, the erroneous output for each fault and each pattern is stored in a dictionary /25/ but depending on the complexity of the chosen fault model and the size of the circuit, such a dictionary may explode. Significant research effort has been spent for reducing the size of fault dictionaries /26/, /27/. The size can be reduced by omitting the erroneous output and storing only pass-fail information for each pair or by limiting the diagnostic resolution of the dictionary and performing fault simulation for each case to distinguish the remaining candidates /28/. Dictionary based cause-effect approaches today can handle industrial-sized designs /29/ but the main drawback-the dependency on simplistic fault models like stuck-at or bridges—remain. However, some advanced methods still use cause-effect analysis as a final stage in the diagnosis process to improve diagnostic resolution. 3.2 Effect-Cause Analysis In effect-cause analysis, possible defect locations are derived directly from the observed failing outputs by taking the logic structure of the circuits into account /30/, /31/. This approach does not depend on the enumeration of all possible faults, thus it can be used to implement fault model independent diagnosis. As mentioned above, such algorithms assume a certain locality of the root cause. The most simple effect-cause algorithms rely on the strongest locality possible: the so-called single fault assumption or single fix condition. This assumption states, that there is a single signal within the circuit which value needs to be altered to explain all failing patterns. Based on this, algorithms were proposed which are based on the intersection of input cones of failing outputs /32/ or backtrace critical paths from failing outputs to focus on delay faults /33/. After finding such a signal in an erroneous design, its logic behavior can be extracted and rectified /34/. The 'Single Location At a Time' (SLAT) approach introduced by /35/, /36/ relaxes the single fault assumption. This approach determines for each pattern single stuck-at faults that can explain the failing response by fault simulation. Those explaining faults can be different for each failing pattern and are used to derive more complex faults. Hence SLAT is a fault model independent approach which merely uses the stuck-at fault model in fault simulation to localize the suspicious region of the circuit. The main drawback of the SU\T paradigm is the fact that information for fault location is only extracted from patterns which fulfill the single fix condition. All the other patterns are not taken into account, neither failing nor passing ones. To overcome this limitation, many algorithms work in two passes: First, a fast effect-cause analysis like SLAT is performed to constrain the circuits region where possible culprits may be located. Second, for each of the possible fault sites, a cause-effect simulation is performed for identifying those faults, which match the real observed behavior/23/, /24/. 3.3 Adaptive Diagnosis There is no concise test set which provides the best resolution for every possible faulty behavior. Since the maximum achievable diagnostic resolution is determined by the test set, many approaches already employ diagnostic or focused ATPG to distinguish remaining suspects or extracting defective behavior completely /23/, /34/. By integrating pattern generation more tightly into the whole diagnosis process, fault location can be even more powerful. This general idea of alternating pattern analysis and pattern generation steps is called adaptive diagnosis /37/. Here, faulty and fault free responses are used in order to guide the automatic generation of new patterns for increasing the resolution. A pattern analysis step extracts informa- tion from responses of the DUD and accumulates them in a knowledge base. This knowledge in turn guides an automatic test pattern generator (ATPG) to generate relevant patterns for achieving high diagnostic resolution. The loop ends, when an acceptable diagnostic resolution is reached (Fig. 3). The definition of the exact abort criterion depends on the number and confidence levels of fault candidates. done Fig. 3: Adaptive diagnosis flow One way to implement such an adaptive diagnosis flow is by the generalization of the SLTXT paradigm. Where SLAT only considers perfect matches for each pattern, a measure can be defined to quantify how well a stuck-at signal explains a response of the circuit under diagnosis /38/. Let FM(f) be a fault machine, i.e. the circuit with stuck-at fault f injected. For each test pattern t g T, the evidence e(f, t) = (Act, Alt, Axt, Ayt) is defined as as tuple of numbers where Aot is the number of failing outputs f can explain. Ait is the number of additional failures f induces, Axt is the number of failing outputs not explained by f (see fig. 4), and Ayt is the minimum of Aat and Ait. A failing pattern t which is completely explained by a stuck-at signal f will lead to evidence e(f, t) = (Aot > 0, 0, 0, 0). So the SLAT approach is only a special case in this notation. Note, that Aot will be maximum for all evidences of t. e{f,T) = (ctt, t-T; TT,rr), with (Ty = I'T = ^ ^l-t- t£T teT tt = ^ Ar^ and 7'r = ^ A7,. teT idT \ If Aa was maximum for a stuck-at signal f and each t e T, a is also maximum. In addition, a candidate is more suspicious if it causes less additional failures in places where the observed response shows the correct values. So the ranking is derived by sorting evidences first by a and then by I . Table 1 provides an example of such a ranking. Table 1: A ranking with fi as the best candidate. stuck-at sig. ar I'T TJ' Tr /1 42 0 0 :h 42 35 0 ./3 42 35 0 f'l 42 35 0 h 42 38 0 k 23 22 19 h 23 23 19 This ranking shows, that f is the only stuck-at signal, which can explain every observed failure and induces no additional ones. Hence, all pattern responses analyzed so far can be explained by this single stuckat fault in the circuit under diagnosis. The failures of stuck-at signal f is a proper superset of the observed failures because a is maxi-mumandi is positive. Moreover since y is 0 for this stuck-at signal, f explains all failing pattern t e Tf c T completely (Aa maximum, Ai = 0) but not every passing pattern (Aa = Ax = 0 and Ai > 0 for some t e Tp c T). This leads to the only conclusion, that f can explain all the responses as a conditional stuck-at fault. Table 2 shows suspect evidences for some classic models. If i , t and y are all zero, a single stuckat fault explains the DUD behavior completely. With I =y = 0, such a stuck-at fault explains a subset of all fails, but some other faulty behavior is present in the DUD. If x and y are zero, a faulty value on a single signal line under some patterns T' c T provides complete explanation. With only y = 0, a faulty value on the corresponding single signal line explains only a part of DUD behavior. If only x is zero, the suspect fails are a superset of DUD fails. If all suspects show positive values in all components i , x , y , all simplistic fault models would fail to explain the DUD behavior. Table 2: Fault models and evidence forms for e(f, T) with ot>0 Fig. 4: Definition of evidence e(f, t) = (Aat, Au, Azt, Ayt) The evidence of a fault f and a test set T is simply the sum of all evidences for f: classic model iT Tt 7t single stuck-at 0 0 0 stuck-at, multiple lault sites 0 > 0 0 single conditional stuck-at > 0 0 0 Cond, stuck-at, multiple foult sites > 0 > 0 0 delay fault, i.e. long paths fail > 0 0 > 0 By simple iteration over the ranking, pairs of suspects f®, f'' are identified with equal evidences e(f®, T) = eif*^, T). In table 1, the stuck-at signals f2, fa and f4 are not distinguished yet. To improve the ranking, fault distinguishing patterns are generated /20/, /21/ and applied to the circuit. During analysis of these responses, different values will be added to the evidences under consideration and the ranking will improve. However, this may also introduce other sets of equal evidences, the approach iterates until all remaining pairs of equal evidences can not be distinguised by diagnostic ATPG. To reduce the number of suspects and the region under consideration further, diagnostic pattern generation algorithms have to be employed which exploit layout data /23/. This generalization of SLAT provides a consistent, single-pass adaptive diagnosis algorithm which extracts evidence from every pattern and the diagnostic results are very encouraging /38/. The consideration of every pattern is important especially if there is only limited failure information available. 4 Design for debug and diagnosis Diagnostic capabilities are needed during the whole life cycle of a system /9/. Besides the techniques and algorithms to find the actual locations of faults or defects there is the need to provide access to the internal states of a device and to record and evaluate diagnostic data. The fulfillment of this tasks is done by Design for Debug and Diagnosis (DDD). Two major problems have to be overcome by DDD: 1) Diagnostic data may reach an enormous bandwidth, due to the requirement of high diagnostic resolution. 2) The diagnosis or debug of so-called hard-to detect faults requires long observation periods. Generally the problem complexity can be broken down by the same means as applied for design-for-testability: scan-design to provide access to internal states, compression and compaction to reduce the data-volume. To guarantee the correctness of a scanned out diagnosis response, the diagnostic equipement has to be faultfree. The diagnosis of shift-registers respectively scanchains is nowadays quite mature /39/, /40/, /41/, /42/. Figure 5 shows the embedded test equipement reused for diagnosis and a schematic of volume diagnosis reusing the multi-site test structure. Compaction of diagnosis responses on the other hand is and will be a major research topic. 4.1 Compaction Techniques Special precautions are necessary to gain more valuable information while keeping the traffic as low as possible. As detailed knowledge on the diagnosis responses is not available, compaction techniques have to be applied to reduce the amount of necessary tester channels on the outputs of the circuit. Compactors can be classified due to different properties. The simplest classification separates timeand space compactors. Space compactors reduce the amount of output channels of a circuit by employing parity trees. Thus space compactors preserve the length of a test response. Time compactors reduce the length of a response vector by compaction of several shift-out cycles and employing memory cells. Combinations of time- and space compactors consisting of a space compaction stage and attached to this a time compaction stage can also be employed to reduce both, response length and width. Compaction may discard valuable information for diagnosis and may reduce diagnostic resolution. Unknown values in the response vectors, caused by buses or uninitialized logic, may additionally cause faultcancellation and -aliasing after compaction. Special compactors were proposed to preserve diagnostic resolution and capability of X-tolerance. Parity check matrices of error correcting codes were employed to con- /|>j -•H Scan Chains Scan Chains £ S 5a E S 51 Scan Chains ATE ..............-____________________________________ Scan Chains E 3, 5 a Fig. 5: Multi-Site Test 240 struct space compactors able to tolerate a certain amount of X-states and able to detect and locate a certain amount of errors. The first approach implementing this was proposed in /43/. Nowadays a large variety of extensions to this approach and similar approaches is available. A popular representative is the X-Compact compactor proposed in /44/. Besides the pure employment of coding theory, the interaction of compactor design with the ATPG was proposed. I-Compact for instance /45/ first employs coding techniques to gain X-tolerance and further enhances X-toler-ance by storing all possible X-positions in addition to the fault-free response vectors calculated during ATPG. By reusing the parity check matrix this can be done very space-efficiently. A different approach uses the ATPG to determine scan-chains, which have to be switched off by a selection logic on scan-out. This can be used on the one hand to enable error propagation for any error /46/ and in more recent work to allow for X-tolerant compaction /47/, /48/. The different compactor designs are already integrated in commercial tools. Despite all the enhancements in compaction the problem of error-masking is not solved completely and will increase with growing circuits. Application of coding theory and the interaction with ATPG will reach its limits with growing cicuits and the demand of fault-model independent or adaptive diagnosis. 4.2 Trace Buffers Contrary to the scan-design method in prototypes, forsys-tem-level debug and silicon debug (fault location before destructive probing) a different approach is often applied. Trace buffers are an on-chip instrumentation supporting at-speed sampling and a low bandwidth connection to external debug sof^yvare which for instance uses a JTAG interface /49/. This approach was influenced by software debugging used in embedded systems /50/. Trace buffers can be classified in special purpose trace buffers designed for a special architecture-e.g. /51/-or generic trace buffers applicable to any SoC /52/. In contrast to scan-chains trace buffers monitor only a subset of internal signals. They are implemented on chip using the available memory to store failing pattern responses. This is area efficient on the one hand, but affects diagnostic respectively debug capabilities on the other hand as the buffer's size limits the observation window. In consequence the window might be too small to locate faults manifesting themselves only after a long execution time. One of the most recent approaches to overcome this problem was proposed in /53/. In cases where the debug experiment can be repeated a cyclic debugging used to zoom into the interesting intervals is employed. 5 Conclusion Today's challenges in diagnosis and debug can be seen in two different areas. First shrinking structures may cause unpredictable circuit behavior. This fact requires diagnosis algorithms and test pattern generation independent of an underlying fault model to enable reliable test and diagnosis. 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Nicolici, "Low cost debug architecture using lossy compression for silicon debug." in Proceedings 2007 Design, Automation and Test in Europe (DATE '07), 16-20 April 2007, Nice, France, 2007, pp. 225-230. Hans-Joachim Wunderlich, Melanie Elm, Stefan Holst Institut fur Technische Informatik, Universifat Stuttgart, Pfaffenwaldring 47; D-70569 Stuttgart, Germany email: (wu, elm, holst}@iti.uni-stuttgart.de Prispelo (Arrived): 15.07.2007 Sprejeto (Accepted): 01.09.2007