UDK 621.3:(53+54+621 +66)(05)(497.1 )=00 ISSN 0352-9045 Strokovno društvo za mikroelektroniko elektronske sestavne dele in materiale k j 3-1994 Časopis za mikroelektroniko, elektronske sestavne dele in materiale Časopis za mikroelektroniku, elektronske sastavne dijelove i materijale Journal of Microelectronics, Electronic Components and Materials INFORMACIJE MIDEM, LETNIK 24, ŠT. 3(71), LJUBLJANA, september 1994 II JI Žužemberk, Slovenia Ceramic Capacitor Factory INFORMACIJE MIDEM 3° 1994 INFORMACIJE MIDEM LETNIK 24, ŠT. 3(71), LJUBLJANA, SEPTEMBER 1994 INFORMACIJE MIDEM GODINA 24, BR. 3(71), LJUBLJANA, SEPTEMBAR 1994 INFORMACIJE MIDEM VOLUME 24, NO. 3(71), LJUBLJANA, SEPTEMBER 1994 Izdaja trimesečno (marec, junij, september, december) Strokovno društvo za mikroelektroniko, elektronske sestavne dele in materiale. Izdaja tromjesečno (mart, jun, septembar, decembar) Stručno društvo za mikroelektronlku, elektronske sastavne dijelove I materiale. Published quarterly (march, june, september, december) by Society for Microelectronics, Electronic Components and Materials - MIDEM. mag. Iztok Šorii, dipl.ing., MIKROIKS d.o.o., Ljubljana Glavni in odgovorni urednik Glavni i odgovorni urednik Editor in Chief Tehnični urednik Tehnički urednik Executive Editor Uredniški odbor Redakcioni odbor Executive Editorial Board Časopisni svet Izdavački savet International Advisory Board Naslov uredništva Adresa redakcije Headquarters Janko Čolnar, MIDEM, Ljubljana Doc. dr. Rudi Babic, dipl.ing., Tehniška fakulteta Maribor Dr.Rudi Ročak, dipl.ing., MIKROIKS d.o.o., Ljubljana mag.Milan Slokan, dipl.ing., MIDEM, Ljubljana Zlatko Bele, dipl.ing., MIKROIKS d.o.o., Ljubljana Miroslav Turina, dipl.ing., Zagreb mag. Meta Limpel, dipl.ing., MIDEM, Ljubljana Miloš Kogovšek, dipl.ing., Iskra INDOK d.o.o., Ljubljana Prof. dr. Slavko Amon, dipl.ing., Fakulteta za elektrotehniko in računalništvo, Ljubljana, PREDSEDNIK Dr. Jean-Marie Haussonne, C.N.E.T. Centre LAB, Lannion Dr. Marko Hrovat, dipl.ing., Inštitut Jožef Stefan, Ljubljana Prof. dr. Zvonko Fazarinc, dipl.ing., CIS, Stanford University, Stanford, USA Dr. Marija Kosec, dipl.ing., Inštitut Jožef Stefan, Ljubljana Prof.dr.Drago Kolar, dipl.ing., Inštitut Jožef Stefan, Ljubljana RNDr. DrSc. Radomir Kužel, Charles University, Prague Dr. Giorgio Randone, ITALEL S.I.T. spa, Milano Prof.dr. Stane Pejovnik, dipl.ing., Kemijski inštitut Boris Kidrič, Ljubljana Dr. Wolfgang Pribyl, SIEMENS EZM, Villach, Österreich Dr. Giovanni Soncini, University of Trento, Trento Prof.dr. Janez Trontelj, dipl.ing., Fakulteta za elektrotehniko in računalništvo, Ljubljana Dr. Anton Zalar, dipl.ing., IEVT, Ljubljana Dr. Peter Weissglas, Swedish Institute of Microelectronics, Stockholm Uredništvo Informacije MIDEM Elektrotehniška zveza Slovenije Dunajska 10, 61000 Ljubljana, Slovenija (0)61 -316 886 Letna naročnina znaša 7000,00 SIT, cena posamezne številke je 1750,00 SIT. Člani in sponzorji MIDEM prejemajo Informacije MIDEM brezplačno. Godišnja pretplata iznosi 7000,00 SIT, cijena pojedinog broja je 1750,00 SIT. Članovi i sponzori MIDEM primaju Informacije MIDEM besplatno. Annual subscription rate Is DEM 100, separate issue Is DEM 25. MIDEM members and Society sponsors receive Informacije MIDEM for free. Znanstveni svet za tehnične vede I je podal pozitivno mnenje o časopisu kot znanstveno strokovni reviji za mikroelektroniko, elektronske sestavne dele in materiale. Izdajo revije soflnanci rajo Ministrstvo za znanost in tehnologijo in sponzorji društva. Scientific Council for Technical Sciences of Slovene Ministry of Science and Technology has recognized Informacije MIDEM as scientific Journal for microelectronics, electronic components and materials. Publishing of the Journal is financed by Slovene Ministry of Science and Technology and by Society sponsors. Znanstveno strokovne prispevke objavljene v Informacijah MIDEM zajemamo v: * domačo bazo podatkov ISKRA SAIDC-el, kakor tudi * v tujo bazo podatkov INSPEC Scientific and professional papers published in Informacije MIDEM are assessed into: * domestic data base ISKRA SAIDC-el and 'foreign data base INSPEC Po mnenju Ministrstva za informiranje št.23/300-92 šteje glasilo Informacije MIDEM med proizvode Informativnega značaja, za katere se plačuje davek od prometa proizvodov po stopnji 5 %. Grafična priprava In tisk BIRO M, Ljubljana Grafička priprema i štampa Printed by Naklada 1000 izvodov Tiraž 1000 primjeraka Circulation 1000 issues UDK621.3.(53+54+621 +66),ISSN0352-9045 Informacije MIDEM 24(1994)3,Ljubljana R. Ročak: Državna podpora raziskovalno-razvojni dejavnosti v Sloveniji 150 R. Ročak: About State Stimulations of R&D in Slovenia ZNANSTVENO STROKOVNI PRISPEVKI PROFESIONAL SCIENTIFIC PAPERS A. Fincato, S. Lorenzotti, P. Nugent, G. Parafioriti, G. Randone: Tehnologija stekla na silicijevem substratu za izvedbo 151 A. Fincato, S. Lorenzotti, P. Nugent, G. Parafioriti, G. Randone: Glass on Silicon Technology for Optical Interconnections and Optoelectronic Hybrid Integration Z. Živife: Večplastni čip varistor:Prihodnost zaščite proti prehodnim pojavom in napetostnim sunkom, I. del - Izdelava in lastnosti 161 Z. Živič: A Multilayer Chip Varistor: The Future in the Low Voltage Transient Suppression, Part I - Fabrication and Characteristics J. Pirš, S. Kopač, R. Lukač, 8. Marin: Planirano tekoča kristalno optično stikalo za optične komunikacije 172 J. Pirš, S. Kopač, R. Lukač, B. Marin: Planar LC Optical Switch for Optical Communications S. Šoba, D. Belavič, M. Horvat, B. Pavlin, A. Simončič: Senzorji tlaka realizirani s pomočjo debeloplastne tehnologije 178 S. Šoba, D. Belavič, M. Horvat, B. Pavlin, A. Simončič: Pressure Sensors Realized by Thick Film Technology Z. Bele: Testne kartice - pomemben dejavnik pri testiranju današnjih kompleksnih mikroelektronskih vezij 182 Z. Bele: Probe Card - An Essential Factor in Testing of Today's Complex Integrated Circuits B.Praček: Karaktorizacija v vakuumu naparjenlh tankih plasti Al na Si rezine 187 B.Praček: Characterization of Thin AI Films Deposited on Si Substrates ELEKTRONSKE KOMPONENTE ELECTRONIC COMPONENTS M. Zdešar: Visokovoltni aluminijasti elektronski kondenzator 193 M. Zdešar: High Voltage Aluminium Electronic Capacitor PREDSTAVLJAMO PODJETJE Z NASLOVNICE REPRESENT OF COMPANY FROM FRONT PAGE KEKO, Žužemberk 194 KEKO, Žužemberk KONFERENCE, POSVETOVANJA, SEMINARJI, POROČILA CONFERENCES, COLLOQUYUMS, SEMINARS, REPORTS M. Hrovat: NATO delavnica "Keramični MCM in materiali za elektroniko" 198 M. Hrovat: NATO Advanced Workshop on " Advances in Ceramic MCM and High Performance Electronic Metarials" VESTI 200 NEWS KOLEDAR PRIREDITEV 204 CALENDAR OF EVENTS TERMINOLOŠKI STANDARDI 205 TERMINOLOGICAL STANDARDS Slika na naslovnici: Proizvodni program firme KEKO, Žužemberk, Slovenija Front page: Production Program of the Company KEKO, Žužemberk, Slovenia ABOUT STA TE STIMULA TIONS OF R&D IN SLOVENIA In the last issue of the Journal the data on Slovenian state stimulation for the study of young researchers was published. Ministry for Science and Technology of Republic Slovenia is financing also other aspects of R&D activities in Slo venia. First of all Ministry is financing completely the fundamental research and the public scientific and research institutes. To the research institutes Ministry is paying 75% of the cost of a R&D project which is ordered by at least two companies or if the research is performed by a mixed group composed of researchers from an institute and research department of a company at maximum 50% relation, 50% of the project cost for the projects ordered by a company if this company guaranties the transfer of the project result in the industrial application. Ministry is covering 50% of an R&D project cost to a company in the case of a research group with researchers from two different companies and 25% if the researchers are from only one company. For hired researchers the Ministry covers 50% of the labour cost for these researchers. 50% of the interests for the bank loans for R&D equipment and infrastructural investments are also subject of Ministry stimulation. A company can get 50% of labour cost for a new Phd applicant in the company for the first year of employment, and 25% for the second year. Ministry is willing also to finance a part of cost for technology centres or parks. In spite of all goodwill of the Ministry there is a question if enough money for the need of Slovenian R&D is available. In any case the actual experience of the applicants for the state stimulation in Slovenia shows that any bigger industrial project can expect drastically financial reduction by a lack of financial 7 possibilities. Great surprise in the R&D area was caused by the Slovenian Ministry of Finance. This Ministry interprets the R&D activity as a technical service with a 5% tax on income (financing). So, the money given by the Ministry of Science and Technology is in 5% value immediately taken by the tax office. Although logic for state income this is an absurd. All proclamations of state incentives for R&D expenses of a company are false. In the balance tax declaration the company can detract the R&D expenses but in this case this can not be accounted for as company's outcome, on the other hand it can not be detracted. And what is the sense of such tax stimulation? It will be interesting to learn something on this subject from other countries. I am asking our members from abroad to give a comment or their experience on the subject. MIDEM Society President Dr. Rudolf Rocak 150 UDK 621,3:(53+54+621 +66), ISSN0352-9045 Informacije MIDEM 24(1994)3, Ljubljana GLASS ON SILICON TECHNOLOGY FOR OPTICAL INTERCONNECTIONS AND OPTOELECTRONIC HYBRID INTEGRATION A. Fincato, S. Lorenzotti, P. Nugent,G. Parafioriti and G. Randone, Italtel, Central Research Laboratories Castelletto d i Settimo Milanese, Milano, Italy Key words: optoelectronics, glass on silicon, optical interconnections, optoelectronic integrations, hybrid integrations, optical communications, optical telecommunications, information processing, optical guides, self aligning procedures, cost reduction Abstract: Optoelectronic integration has been widely recognised as a very important step to further increase the competitiveness of optical technologies in communication and information processing. Despite the impressive development effort on a monolithic technology, based on semiconductor InP and GaAs substrates, which has been carried out until now with quite promising feasibility results, it is still quite far in its present implementation from being suitable for economic product development. Therefore, a less ambitious target may be set by choosing an hybrid approach, where optical interconnects can be realised on a specific substrate and active components (Lasers and PINs) are mounted on this substrate by a die attach process, eventually aligned to the optical guides with self aligning procedures. The Glass on Silicon technology developed by Italtel, which will be described in this paper, is an example of this approach, and could be applied very quickly to the development of specific components and modules for optical telecommunications system, with many clear advantages in terms of cost reduction and mass production capability, with the support of very efficient CAD tools for the design of complex, multifunctional optical subassemblies1 Tehnologija stekla na silicijevem substratu za izvedbo optinih povezav in optoelektronske hibridne integracije Ključne besede: optoelektronika, steklo na siliciju, povezave optične, integracije optoelektronske, integracije hibridne, komunikacije optične, telekomunikacije optične, procesiranje informacij, vodi optični, procedure samonastavljive, zmanjšanje stroškov Povzetek: Veliko ljudi že priznava optoelektronsko integracijo kot zelo pomemben korak k povečanju konkurenčnosti optičnih tehnologij v komunikacijah in obdelavi informacij. Navkljub prepričljivemu razvoju monolitne tehnologije na osnovi polprevodniških InP in GaAs substratov, ki je potekal do sedaj z obetajočim uspehom, je le-ta na sedanji stopnji razvoja že dokaj daleč od tega, da bi bila primerna za razvoj ekonomičnega proizvoda. To pomeni, da si v tem trenutku lahko zastavimo manj ambiciozen cilj, to je hibridni pristop, kjer optične povezave izdelamo na specifičnem substratu, dodamo pa aktivne komponente (laserje in PIN diode) v čip obliki, ki jih pritrdimo na ta substrat in poravnamo z optičnimi vodniki s samonastavljivimi poravnalnimi postopki. Tehnologija stekla na siliciju, ki jo je razvila firma ITALTEL, in ki jo opisujemo v tem prispevku, je primer takega hibridnega pristopa. To tehnologijo lahko hitro uporabimo za razvoj specifičnih komponent in modulov za optične telekomunikacijske sisteme z jasnimi prednostmi glede zmanjševanja stroškov in možnosti velikoserijske proizvodnje ob uporabi zmogljivih CAD orodij za načrtovanje zamotanih večfunkcijskih optičnih podsestavov. 1. INTRODUCTION Packaging and assembly processes still make up a large part of the manufacturing cost in the fabrication of optoelectronic components and subsystems. Besides high cost, which is limiting the penetration of optical fibres in the distribution network, available technologies do not efficiently support the batch fabrication of complex opti-. cal interconnection schemes, which are increasingly needed for optical switching and multiwavelength networks in order to become practical applications. Monolithic integrated optics has been considered for a long 1 This paper is the second of a series, which will be presented in MIDEM during 1994, concernig advanced topics in optical technologies and systems. The first contribution has been devoted to optical amplifiers and the last one will discuss a specific application to multiwavelength transport networks time a main research and development road to overcome these difficulties, by considering the analogy with the microelectronics case. Unfortunately, until now, encouraging results are still largely confined to laboratory feasibility, due to the intrinsic complexity and low yields of the required technologies, which put the economic convenience of the huge investments needed to implement a true high volume manufacturing capability for optical integrated circuits somewhat at risk. Even from a conceptual point of view, it became clear that a fundamental difference exists between integrated optics and electronic integrated circuits: for a VLSI chip only one basic building block is required (a silicon transistor), which relies on a well known and mature substrate technology; instead, the substrate for an integrated optic device may be chosen from a large variety of options (GaAs, InP, Silicon, glass, LiNb03, to mention the most popular choices), and the building blocks may include light sources and photodetectors, optical waveguides, 151 Informacije MIDEM 24(1994)3, str. 151-159 A. Fincato, S. Lorenzotti, P. Nugent, et. ai.: Glass on Silicon Technology for Optical Interconnections and ... passive optical components and light modulators, each one realised with a specific design and technology, generally with very limited, or none at all, mutual process compatibility. Therefore, apart from a very limited number of cases (the PIN photodetectorwith integrated FET preamplifier, for instance), the performance of integrated optoelectronic devices is generally worse than their discrete assembled equivalent version. In fact, elementary optical functions integrated on a monolithic chip are far less optimised due to process compatibility reasons, with respect to the same functional result achieved with discrete devices. By considering the above aspects, a more realistic and practical approach than monolithic integrated optics may be based on the choice of a substrate material optimised for optical passive waveguide fabrication, on which discrete active optoelectronic devices may be mounted by a suitable hybrid assembly procedure and easily selected for a specific application. In our case, a silica layer deposited on a silicon substrate by a chemical vapour deposition technique was selected for waveguide formation; on the same silicon substrate, well known dry and wet etching, dielectric and metallic thin films deposition processes and photolithography can be used for waveguide patterning and metallic mounting pads formation. The final result is an hybrid assembly platform, suitable for a large variety of optical and electrical interconnection schemes and micromechanical alignment for efficient optical coupling, which could give to the photonic applications the same flexibility in product development, which was allowed by the introduction in the electronic design and manufacturing by the well known printed circuit board. The Glass on Silicon technology (GoS), which will be described in the following, has been developed by Italtel in cooperation with AT&T-Bell Laboratories, during a two years joint development agreement which has been just terminated in June 1994. In the framework of this agreement, Italtel holds a full manufacturing license for products based on the glass on silicon process technology, including those processes which were originally developed by AT&T alone. Most of the work described in this : Lowerl'CladdlngTS uml ■ BjjfferflayerclP urrv i a , Fig. 1: Cross-section of silica waveguide grown on Silicon substrate paper has been carried out by a joint team from ATT and Italtel, in the ATT- Microelectronic and Bell Laboratories research facilities, in Breinigsvilie (PA) and Murray Hill (NJ). 2. GLASS ON SILICON TECHNOLOGY 2.1 Waveguide deposition A typical waveguide structure is formed on a 4" silicon substrate 0.5 mm thick; a 10 |im thick SiOž buffer layer is deposited first, by an high pressure oxidation process (High Pressure Oxidation, HIPOX), to avoid any optical leakage into the silicon substrate. The first cladding layer of the planar waveguide (5(j.m, P doped SiOž) is deposited next, by a low pressure chemical vapour deposition, followed by a 1000°C annealing for densification and to remove the residual stress in the layer. The core waveguide layer (5|im) is then deposited by a similar process; the required refractive index for the core layer is controlled by varying the Phosphor doping and the deposition temperature. The silicon wafer is then processed through a photolithography and a dry etching process for two dimension rectangular waveguide patterning, followed by a 900°C annealing which rounds the waveguide corners and improves the layer optical characteristics. Finally, an upper cladding layer is deposited, which completes the waveguide structure (Fig. 1) The waveguide shape is roughly a semi-circle, with a 5(im diameter; the refraction index step is of the order of 0.5 %, and intrinsic losses as low as 0.01 dB/cm have been measured; other typical waveguide parameters are reported in Table 1. Table 1: Glass on Silicon waveguide parameters index of refraction step, An/n (%) 0.5 core size diameter ((am) 5 waveguide loss (dB/cm) 0.03 fiber coupling loss (dB) 0,1 bend radius (mm) 15 coupler excess loss (dB) 0.2 Coupling length (mm) 2 + 0.3 2.2 Wafer processing and micromachining In addition to the waveguide fabrication, other wafer processes have been developed, in order to obtain a number of basic building blocks for a flexible implementation of complex functionalities. Most of these processes are readily available with little or no modifications from silicon microelectronics technology, and can be implemented on high throughput processing machines. In particular, current development work is under way on 4" silicon wafers, but all the machinery is already equipped with jig adapters suitable for handling 6" wafers. In addition to the already mentioned CVD process, 152 A. Fincato, S. Lorenzotti, P. Nugent, et. al.: Glass on Silicon Technology for Optical Interconnections and ... Informacije MIDEM 24(1994)3, str. 151-159 which will use two 4-stack BTLJ furnaces for doped SiC>2 and polysilicon deposition, standard processing facilities Include Reactive Ion Etching, Plasma Enhanced CVD, for thick and low temperature oxide deposition, dielectric and metal thin film sputtering and metal deposition equipment. Micromachining of the silicon substrate by using selective and anisotropic wet etching allows to reach submi-cron fabrication tolerances for the creation of 3D features on the substrate (steps, recesses, holes and V-grooves for instance), which may be used as mechanical references for self- alignment of various optical components (lasers, photodetectors and optical fibres) with the waveguides grown on the substrate. Afew simple results already achieved in this area will be described below, as a good example of the potential of this process technology. It should be noted that, since the etching depth generally required for these applications is an order of magnitude larger than in the microelectronic case, little or no help is available from established specific silicon technology, and therefore new process development has been carried out. 2.3 Packaging Packaging issues have always been a critical factor in optical and optoelectronics devices development, in particular with respect to cost targets and volume production capability. Therefore, an important long term objective for the GoS technology is to achieve complete automation in the assembly and packaging procedures, in particular without any need for active alignment for optical coupling; as a necessary condition for high production volume and low manufacturing cost. While substantial development work is still required to achieve this goal, some guidelines have already been established and tested with an encouraging degree of success; in particular: cesses In Silicon to be placed in correspondance with chip positions on the substrate. The lid cover is then mounted in place by a selective die attach process on the hybrid optical circuit to achieve an high optical and electrical crosstalk immunity. The lid also allows for an hermetic seal of active devices and reduces outside electromagnetic interference. Moreover, most of the remaining work on the hybrid circuit (the fiber attachement for instance) can be carried out with delicate components on the circuit well protected and safeguarded, in such a way as to achieve high yield in testing and packaging operations. 4. the use of a plastic housing, allowed in conjunction with the hermetic silicon lid, as a final package, may further reduce the cost and increase the possibility of using different standard packages while mantaining the quality and reliability level mandatory for telecommunication applications. The above mentioned steps clearly indicate that the glass on silicon technology holds the potential for achieving a breakthrough in optoelectronic assembly and packaging technologies; in particular, the intrinsic high yield batch process technology could be used to obtain a very low cost high volume production capability for simple devices (A packaged laser or photodetector), or to achieve an industrial standard for manufacturing complex multifunctional optoelectronic modules, with high yield and reasonable cost. A simple sketch of the potential described above is illustrated in fig. 2, which refers to a bidirectional optical transceiver, capable of using two carrier wavelengths for sending and receiving data signals simultaneously on the same optical fibre; all the functions described in fig.2, with the exception of the integral mounting of the laser source, are already available as engineered building blocks for the implementation of GoS hybrid integrated optic devices. 1. a batch procedure has been defined, by a selective metallisation scheme, which allows the self-positioning of a semiconductor chip (Laser or photodetector) on the silicon substrate during the die attach, with better than 1 jim tolerance in position and less than 10 mrad misalignment of the chip edge with respect to a selected direction, starting with a relatively loose tolerance of the initial placing (20- 30jim in position, and 20° - 30° degree for the chip edge) 2. a quite complex procedure has been developed to etch a 45° degree mirror for vertical extraction of optical radiation from planar waveguides; in combination with the above process 1., then it has been possible to self-align a PIN photodetector directly with the waveguides by a batch process at the wafer level, as a good example of a truly hybrid optical integration. FIBER ATTACHMENT ■ WAVEGUIDE TERMINATION 3. a simple and economic lid cover technology has p/g_ been developed to fabricate by etching specific re- Example of a Glass on Silicon integrated optoelectronic module 153 Informacije MIDEM 24(1994)3, str. 151-159 A. Fincato, S. Lorenzotti, P. Nugent, et. al,: Glass on Silicon Technology for Optical Interconnections and ... 3. PASSIVE COMPONENTS DESIGN Key functions in integrated optic devices are supported by passive optical components; in fig. 2 for instance the wavelength demultiplexing function, by which the incoming wavelength is sent to the photodetector, is implemented by the use of a planar waveguide structure" well known in classical optics as a Mach-Zehnder interferometer. Complex passive components may be realised starting from several elementary optical elements: the straight and curved waveguide are the simplest examples of elementary passive optical component together with 3 db Y couplers and splitters. It should be noted that the bending radius of a curved waveguide is a critical design parameter/1//2/, since (for a fixed refractive index step between core and cladding in the waveguide) the radiation losses increase exponentially with decreasing bend radius. Therefore a compromise should be found between the optical circuit dimensions and the acceptable radiation losses; in our case, a bend radius of 15 mm is sufficient to keep radiation losses below 0.1 dB/cm. An important development issue therefore is how to increase the refractive index step in the guiding structure. Typical measured losses as a function of the bending radius for a curved waveguide are reported in fig.3, and the advantage of a higher index step may be clearly seen. - high Inciox atop (0.75%) • low Intiox stop (0.50%) 0 2 4 6 8 10 12 14 16 18 20 Radius of curvature (mm) Fig. 4: 2X4 splitter for ribbon cable depends on waveguide parameters (around 30° degrees for this specific example) 3.1 Directional couplers When two waveguides come into close proximity (at a distance of the order of magnitude of the guided wavelength) for a certain length, an energy transfer takes place between the waveguides; the effect is the optical equivalent of the directional coupling well known to microwave engineers, and is controlled (Fig. 5) by the operating wavelength, the coupling length L, and the waveguides spacing d. In a directional coupler the input and output waveguides should be single mode while the central zone should be bimodal at the wavelengths of Port 3 XI X2 Port 4 Fig. 5: Schematic of a directional coupler Fig. 3: Bend losses of curved waveguides measured at the 1550 nm wavelength (TM mode) Even with simple elements it is possible to design quite complex optical interconnection schemes, which may offer relevant advantages in terms of quick design, simple manufacturing, reliable'operation and very low cost. An example is shown in fig 4, which illustrates a 2 X 4 splitter for four fibre ribbon cable, designed and developed by Italtel for the Italian Public Operator TELECOM Itaiia, to be used in Passive Optical Network field trials, currently under way in Turin and Rome. The integrated splitter will replace a bulky and fragile distribution box using fused fibre couplers and fusion splices manually assembled. It is interesting to note the use of waveguide intersections, which does not causes any measurable signal cross-talk, provided that the intersection angle is higher than a minimum value, which interest. Due to the small branching angle, light is adia-batically coupled from the input branch into the double waveguide section. The two modes excited at a particular wavelength have different effective refractive indices and thus propagate at different velocities in this section. As these two modes interfere with one another the energy in the central zone oscillates from one waveguide to the other as the resulting phase difference between the two modes changes. Taking account of the distributed coupling in the input and output sections, this phase difference is given by: central zone + A0 branching zones = Ap l + Jap dz (1) By ignoring the second term in this equation we can derive an expression for the coupling length in the central zone: 154 A. Fincato, S. Lorenzotti, P. Nugent, et. al.: Glass on Silicon Technology for Optical Interconnections and ... Informacije MIDEM 24(1994)3, str. 151-159 —— Port 3 (Prediction) —— Port 4 (Prediction) ° Port 3 (Exp. data) a Port 4 (Exp. data) 1.2 1.25 1.3 .35 1.45 1.5 1.55 1.6 Wavelength (micron) Fig. 6: Design prediction and experimental results of a WDM Le (X) = 2 (noo ■ n0ij (2) Multi/demultiplexing between two wavelengths may be achieved by choosing the length of the two waveguide section to be an even multiple of Lc at one wavelength and an odd multiple of Lc at the other. The spectral characteristics of a directional coupler WDM are shown in fig.6, where excellent agreement is obtained between design prediction and experimental results. 3.2 Wavelength Division Multiplexers The directional coupler principle can be used in a more complex structure (Fig. 7) based on two input ports, two 3-dB directional couplers, and a central section where one of the waveguide is longer by AL, in order to give a wavelength dependent phase shift between the two arms, and two output ports. The resonance conditions required for the multi/demultiplexing of two specific wavelengths are (at the output of the interferometer): n(M). AL = m. 11 r\(X2). AL = (m ± 0.5). M where n(X) is the refractive index and m is an integer.(the order of the interferometer). Port 3 -xi X2 Fig. 7: 3 dB couplers Mach-Zehnder interferometer Port 4 The power from the input port divides between the two output ports in such a way that a specific wavelength can be adressed to each port. Therefore, the transmission characteristic of the Mach Zehnder interferometer allows the realisation of a wavelength division multiplexer or demultiplexer (WDM) where many optical carriers are being transmitted on a single fibre in a transmission network. While this principle was well known and applied for quite a long time, the new opportunity offered by the glass on Silicon technology is the full support from a computer aided design capability, which directly generates the photolitographic masks needed to implement the required design, with high accuracy and reproducibility. Moreover, the use of CAD tools would make it relatively easy to implement complex structure starting from more simple building blocks already designed and tested; for example, a four channel multiplexer, shown 155 Informacije MIDEM 24(1994)3, str. 151-159 A. Fincato, S. Lorenzotti, P. Nugent, et. al.: Glass on Silicon Technology for Optical Interconnections and ... ferometer arms. If this difference could be varied externally, a tuning capability would be added to the interferometer. In the case of devices built on an electrooptic material such as LiNbC>3, this effect is achieved by applying an electric field. In the GoS case, similar results has been experimentally demonstrated by NTT by using a thermo-optic effect/3/. In practice, a thin film NiCr strip heather is metallised on top of one interferometer arm, whose optical path length can be controlled by a ther-morefractive effect due to current heating of the NiCr strip. Even if this effect is relatively slow, with response time of the order of milliseconds, it can be very useful in the development of complex multiwavelength networks as it would provide an economic solution to many wavelength control and routing problems, where only low speed processing capability is generally needed. 3.3 Multifunctional devices More complex passive optical devices are at present under study to be implemented in the GoS technology; two examples will be shortly described here in order to give a simple demonstration of the potential of the approach. Both devices have already been tested in terms of feasibility in the ATT and NTT Laboratories. With glass on silicon technology it is possible to implement waveguide patterns of NxM star couplers/4//5// (N and M up to 256) as shown in fig 10. The input power from any one of the 256 channel waveguides in the input array is radiated to a slab region and received by the output array. The uniformity of the optical power distri- 1520 1525 1530 1535 1540 1545 1550 Wavelength (nm) Fig. 9: Measurement of a 4 channel WDM with 5 nm channel spacing Fig. 8: Four channel WDM schematic in fig. 8, is composed of three Mach Zehnder interferometer elements. The power from the input port divides among the four output ports, as a function of the selected wavelengths, the spectral characteristic of the four channels WDM is shown in fig.9. The precise differences in path length required for the multiplexer design is easily controlled by the the mask fabrication process. With normal tolerances available in microelectronic masks, it would be possible to design multi channel WDM with channel spacing as low as 0.1 nm, the only limitation in channel number being the available wafer size. The Mach-Zehnder interferometer is a basic building block in the design of a variety of optical control functions based on the splitting and combining of optical beams, normally as a function of their wavelength, which is controlled by the different optical length of the two inter- -B- ~ Ch. 1 - Ch. 2 --«- - Ch. 3 - Ch. 4 156 A. Fincato, S. Lorenzotti, P. Nugent, et. al.: Glass on Silicon Technology for Optical Interconnections and ... Informacije MIDEM 24(1994)3, str. 151-159 Fig. 10: NxN star coupler bution was obtained by optimising the coupling conditions between adjacent waveguides in the input waveguide array. This device has the added advantage of being wavelength independent it properly designed. Fig. 11: NxN switching matrix 4. HYBRID ACTIVE INTEGRATED COMPONENTS Another complex device which has been realized using this technology is the NxN (N < 8)switching matrix, as developed by NTT171 and illustrated in fig 11. This device allows the routing of an optical signal to any one of N output fibres. The routing is realised using a composition of N2 elementary switches each of which is based on a symmetric Mach-Zehnder interferometer thermally tuned by an electrode. Both arms of the interferometer are of equal length (no geometrical path difference) and the optical path difference is varied by modifying the effective refractive index in one of the two arms by means of the thermooptic effect. This effect is generally slow (» 1 ms) but still quick enough for most routing applications. Assembly of active devices, such as lasers and photode-tectors, on the Silicon substrate, with self alignement features with respect to passive elements (Fibres and planar waveguides) is another critical step to achieving a practical optical integration capability. Therefore, two basic processes have been established to develop the elementary building blocks for such functions. 4.1 Integrated photodetector (PIN-PAC) The basic version of the integrated photodetector consists of a PIN photodiode mounted on a silicon submount and coupled to an optical fibre pig-tail (fig. 12). Fig. 12: PIN-PAC integrated photodetector 157 Informacije MIDEM 24(1994)3, str. 151-159 A. Fincato, S. Lorenzotti, P. Nugent, et. al.: Glass on Silicon Technology for Optical Interconnections and ... The basic characteristics of the PIN-PAC are: 1. the use of a 45° degree mirror to reflect the incoming light from the fiber pig-tail to the bottom illuminated photodetector soldered above it. 2. the use of anisotropic etching through a thick SiN or Si02 mask to form deep "V-grooves" in the Silicon substrate to house and fix the fibre pig-tail, with process reproducibility capable of achieving a 1(j.m tolerance in the position of the fibre, without any active alignement procedure. 3. the use of a particular metalisation pattern on the Silicon substrate and on the photodiode which makes possible the self-centering of the photodiode die with respect to the turning mirror position during the die-attach soldering process. This process can be done in a single step at the wafer level for hundreds of PIN devices simultaneously. Therefore the PIN-PAC device is made without the need for individual optical alignement; the process is suitable to achieve both high production volume and very low cost. The assembly shown in fig 12 is a discrete device, which offers a very competitive trade-off between performance, cost and overall quality, with respect to currently available standard alternatives. In the case of an integratable photodetector, a similar but somewhat more complex process technology has been developed, in which the turning mirror is directly etched in the glass waveguide. In conclusion, the optical receiver function can be considered fully available for an hybrid integration in a Glass on Silicon optical IC. requires an active alignement procedure. Moreover, the Laser-PAC structure is not suitable for hybrid integration, even if a very simple coupling procedure can be used to join a fibre pig-tail of a few millimeters from the Laser-PAC to a "V-groove" on a separate Silicon substrate. 5. OPTOELECTRONIC MODULES APPLICATIONS While most of the effort under way on the Glass on Silicon prograrn is still focused on implementing process technology, and on achieving a good control of design tools and characterisation of basic building blocks described above, a few optoelectronic module prototypes have already been developed for specific applications, by using a combinations of available active and passive optical functions 5.1 Integrated optical transmitter and front-end receivers The compact and reliable structure of PIN-PAC and Laser-PAC is ideally suited for realising an hybrid optoelectronic IC, by mounting on the same substrate, or on a ceramic support, the required electronic circuits. In the case of the receiver, the structure (fig.14) includes a PIN-PAC photodetector and a custom IC for preamplifier, AGC and clock recovery functions: 4.2 Integrated photoemitter (Laser-PAC) Intermediate results have been achieved so far in the case of the optical transmitter. A similar structure for a discrete device (Laser-PAC) (Fig. 13) has been developed, which already offers distinct advantages in terms of performance and manufacturing procedures with respect to standard laser modules, (the use of an integral microheather for the soldering of a metallized fibre pig-tail to the silicon submount, forinstance) but still Laser Fig. 13: Laser PAC Fig. 14: SDH receiver Housing is provided by a2x 1 cm package with a pig-tail. The transmitter includes a Laser-PAC mounted on a ceramic substrate with a custom IC for laser driver and supervisory and control functions, in the same housing as above. Both units'specifications are compatible with STM1 Synchronous Digital Hierarchy standard for 155 Mbit/s operation. For stand alone PIN- PAC and Laser- 158 A. Fincato, S. Lorenzotti, P. Nugent, et. al.: Glass on Silicon Technology for Optical Interconnections and ... Informacije MIDEM 24(1994)3, str. 151-159 Motallizalio; i, Solder, Solder Dams, Healers Fig. 15: Bidirectional operating module PAC devices bandwidths in excess of 1 GHz have been measured, essentially identical to the laser and PIN original bandwidth characteristics. 5.2 Bidirectional optical transceiver Bidirectional transmission of two carrier wavelengths on the same optical fibre has been considered by several RACE projects to be a viable solution for reducing cost in the implementation of the Broadband Access Network. Bidirectional transmission may be considered as a specific case of WDM principle, and therefore the development of an integrated bidirectional module has been chosen as a significant test vehicle to validate the Glass on Silicon technology with respect to the process capability of hybrid integration of several functions. At present, these functions are the wavelength demultiplexing, the monitor photodiode, the line receiver photo-diode, the "V-groove" coupling of the output/input optical fibre and do not include the laser transmitter. A Laser-PAC equipped with a very short (a few mm) pig-tail can be coupled to a "V-Groove" etched into the module. The structure of the bidirectional module (apart from the transmitter side), is very similarto the scheme illustrated in fig. 2, and it is shown in fig. 15. The optical bidirectional link is equipped with two complementary transceivers for each line termination. In particular data from the network (upstream) side should be transmitted at 1300 nm wavelength and data from the customer access (Downstream) side at 1500 nm wavelength. Also the data rate may be asymmetrical. (622 MBit/s upstream and 155 MBit/s downstream) The WDM function is realised by a Mach-Zehnder interferometer, which provides enough isolation from optical cross-talk (>20 dB) to achieve the required Bit Error Rate on the line terminal; one of the WDM branches also provides the signal for the monitor photodiode. Electronics functions (Laser driver, PIN preamplifier and control circuitry) are realised with bare IC chips, mounted near the optoelectronic module on a ceramic thin film substrate. Layout design to mount these ICs directly on the Glass on Silicon substrate is under study, in particular to evaluate electrical cross-talk problems. The hybrid integrated circuit, including electronic functions, is housed in a 24 pin Dual in Line package. 6. CONCLUSIONS Features of a new approach to the development of hybrid integrated optical circuits have been presented, taking into account material deposition processes, packaging and assembly aspects, and preliminary results on prototype design and characterisation. Main achievements reported to date include the simulation and design of several passive optical components, whose performance has been experimentally tested with good overall results. A sufficient set of CAD rules and basic building blocks have been established and experimentally assessed to make possible quick end efficient design of more complex functionalities. On the other hand, the high degree of process reproducibility, tested with good statistical accuracy, makes us confident that the technology is sufficiently stable and controlled to allow a pilot production line deployment, which would be in full operation by mid 1995. To our knowledge, this is the first industrial initiative in Europe for a product development which may lead to a significant breakthrough in the field of optoelectronic component manufacturing and optical communication system technology. 159 Informacije MIDEM 24(1994)3, str. 151-159 A. Fincato, S. Lorenzotti, P. Nugent, et. al.: Glass on Silicon Technology for Optical Interconnections and ... ACKNOWLEDGMENTS The Authors wish to acknowledge the work done by all the Colleagues of the GoS Group, and in particular the outstanding contribution to the results described here given by S. Doneda, G. Iseni and G. Preve. REFERENCES /1/ "New technology for reduction in cost and size of silica guided wave component", K.lmoto and A.Hon, Electronics Letters Vol.28 No. 17, 13th August 1992. /2/ "Optimum planar bends", C.Dragone, Electronics Letters Vol.29 No. 12, 10th June 1993. /3/ "A four channel optical waveguide multi/demultlplexer for 5 GHz spaced optical FDM transmission", Kyo inoue et al, Journal of Lightwave Technology Vol.6 No.2, February 1988. /4/ "Efficient multichannel integrated optics star coupler on silicon", C.Dragone et al, IEEE Photonics Technology Letters Vol.1 No.8, August 1989. /51 "Efficient NxN star couplers using Fourier optics", C.Dragone, Journal of Lightwave Technology Voi.7 No.3, March 1989. /6/ "Efficient NxN star couplers based on Fourier optics", C.Dragone, Electronics Letters Vol.24 No.15, 21st July 1988. Ill "Silica based optical matrix switch with intersecting Mach-Zehnder waveguides for larger fabrication tolerances", M.Kawachi et al, OFC/IOOC '93. A. Fincato, S. Lorenzotti, P. Nugent,G. Parafioriti and G. Randone, Italtel, Central Research Laboratories Castelletto di Settimo Milanese, Milano, Italy tel. + 39 4388 7320 fax + 39 4388 7989 Prispelo (Arrived): 15.08.94 Sprejeto (Acepted): 20.09.94 160 UDK 621,3:(53+54+621+66), I-SSN0352-9045 Informacije MIDEM 24(1994)3, Ljubljana A MULTILAYER CHIP VARISTOR: THE FUTURE IN THE LOW VOLTAGE TRANSIENT SUPPRESSION Part I: Fabrication and Characteristics Zm a s v ■ ¿&L9V10 KEKO, Žužemberk, Slovenia Keywords: voltage transients, protective devices, protection components, SMT, surface mount technology, multilayer chip varistors, MLV chip varistors, ZNO varistors, thin sheet laminating technology, ceramic technology, leakage currents, surge currents, response times, nonlinear coefficients, surge absorptions, electrical breakdowns, fabrication processes, electrical properties Abstract: A low voltage ZnO multilayer chip varlstor for surface mounting was developed using tape casting and green sheet laminating ceramic technology. Differently sized chip varistors with breakdown voltage ranging from 4 V to 100 V were realised, featuring low leakage current, high nonlinear coefficient in a wide current range, very high surge current withstand capability (> 2000 A) and response time shorter than 5 ns. Very good stability on repetitive pulse of high amplitude and high energy level was also recorded. All these characteristics make multilayer chip varistor a very promising low voltage protection device. Večplastni čip varistor: Prihodnost zaščite proti prehodnim pojavom in napetostnim sunkom I del: Izdelava in lastnosti Ključne besede: pojavi prehodni napetostni, naprave zaščitne, elementi zaščitni, SMT tehnologija montaže površinske, MLVchip varistorji večslojni, chip varistorji, ZNO varistorji, tehnologija nalivanja plasti tankih, tehnologije obdelave keramike, tokovi uhajavi, tokovi udarni, časi odzivni, koeficienti nelinearni, absorpcije udarov, preboji električni, procesi proizvodni, lastnosti električne Povzetek: Nizko napetostni ZnO večplastni čip varistor za površinsko montažo je bil razvit s pomočjo keramične tehnologije nalivanja tankih plasti. Narejeni so čip varistorji različnih dimenzij, s prebojnimi napetostmi v obsegu od 4 V do 100 V, z naslednjimi lastnostmi: nizki tok puščanja, visoki nelinerni koeficient v širokem tokovnem področju, sposobnost absorpcije tokovnih sunkov višjih od 2000 A in čas odziva krajši od 5 ns. Zelo dobra stabilnost proti tokovnim sunkom visoke amplitude ter visokih energij je tudi bila ugotovljena. Vse te lastnosti kažejo da je večplastni čip varistor zelo obetavna nizko napetostna zaščitna komponenta. 1. Introduction Electronic and electrical circuits can be subject to severe and sudden impulse voltage transients generated by lightning, switching and electrostatic discharge accumulated on the human body. A contemporary development in the field of electronics and especially microelectronics requires miniaturised, highly integrated and low power consumption devices. As a result of this, the requirements for reducing device sizes and operation at low voltages are becoming extremely important for all electronic components including protective or surge absorbing devices. Namely, lowering of the device geometrical dimensions, or scaling down principle, is widely used to improve * - This paper presents a part of the results accomplished within the project titled "Multilayer Electronic Ceramic Components", no. B-669, which was partially financially supported by Slovene Ministry of Science and Technology from 1991 -93. CMOS IC's performances as: speed, density, complexity, reliability and cost. The dimension lowering is followed by operating voltage lowering as well. At the same time, internal protection devices built into IC's (typically containing monolithic connected diffused resistor with two or four Zener diodes) have been reduced in size to minimise their impact on speed and circuit area. Therefore, protection efficiency of the internal protection decrease, so CMOS IC's become more sensitive to damage or malfunctions caused by supply voltage transients and electrostatic discharges. As a solution, electronic designers can either overspe-cify the circuits or use external protection. Final stability and quality of systems as well as economic balance call for the use external protection, not only of the whole systems or subsystems but of the individual sensitive components as well. Transient voltage overstress protective devices can be divided into three categories: filters ( R-C, R-L-C, etc.), crowbars such as gas discharge tubes or thyristors and low voltage clamps like varistors and Zener diodes. As 161 Informacije Ml DEM 24(1994)3, str. 161-171 Z. 2ivi<5: A Multilayer Chip Varistor: The Future in the _Low Voltage Transient Suppression - Part I:... far as low voltage surface mount devices are concerned only multilayer chip varistor (MLV) and Zener diode will be discussed. Both exhibit the necessary voltage - current relationship: at low voltages the current is very small, but when the applied voltage exceeds some predefined value (threshold), the device impedance decreases drastically and dissipates the excess energy which would be absorbed by the active component being protected. AZnO MLV as well as Zener diode have this property although the operating physical principles and technology are different as shown in Table 1. Both planar Si processing technology and pn-junction physics as a basis of Zener diode functioning are very well covered in literature1,2. Shallow pn- junction depletion region directs the operation of Zener diode. Its breakdown mechanism is tunnelling and avalanche multiplication one. Zener diode breakdown voltage is regulated by the depletion layer width, i.e. by the charge carrier concentration on both sides of pn-junction as well as by its geometry. When the diode is in breakdown, the greatest part of the energy is dissipated exactly in the shallow depletion layer. In the case of varistor the physical model of its operation is not so 'clear', which will be one of the subjects of the discussion to follow. Table 1\ General differences between Zener diodes and multilayer varistor General Characteristics Zener Diode MLV Basic material Si ZnO Structure Monocrystal Polycrystal Physical mechanism Tunneling & avalanche multiplication Thermoionic emission & hot carrier injection effect Barrier type Abrupt junction Double Shotky barrier Technology Planar Si Ceramic-thin sheet laminating 2. Fundamental Characteristics of ZnO Varistors 2.1. Basic material While Zener diode is semiconductor component made on monocrystalline Si, varistor is polycrystalline semi-conductive electronic component on ZnO. Semiconducting ZnO of wurzite crystallographic structure is basic varistor material amounting to more than 90 % wt. This structure is relatively 'open' allowing easy building-in of dopants and influencing the nature of defects and diffusion mechanism3. The most common defect in ZnO is the metal ion in the open interstitial site, leading to a nonstochiometric metal excess N-type semiconductor with band gap of 3.3 eV. Within the band gap there are donor and acceptor levels occupied by thermally induced intrinsic defects as shown in Fig. 1. 3.15 > CJ 2.8" cn a 01 1.2- c o L- 0.7- a a 0 -- 2.8 eV Figure 1: Energy - band diagram of ZnO3 2.2. Varistor Microstructure Varistor is realised by homogenisation of ZnO powder with the oxide additives of Bi, Sb, Mn, Co, Cr, Ni, Al, etc. Forming of such a composite is performed by one of the ceramic procedures (dry pressing for example). After sintering, final polycrystalline ceramic structure, characterised by unique grain boundary properties that contribute to the nonlinear l-V varistor characteristics is obtained. As the flow of the electric current is controlled by electrostatic potential barrier of the grain boundaries, its electrical activity and microstructure can be adapted to provide the desired special properties of the material. For this reason many material scientists have been extensively studied ZnO varistor mictrostructures, especially those of the grain boundaries4"6. Their main concern was to investigate various crystalline phases, their 50 um EZ3 Pore □ ZnO PyrochlQre Spinel \'V/\ B'Srnuth oxide Figure 2: Actual structure of ZnO varistor7 162 Z. 2ivi<5: A Multilayer Chip Varistor: The Future in the Low Voltage Transient Suppression - Part I:... Informacije Ml DEM 24(1994)3, str. 161-171 Compound 2 3 Bi^O 2 3 Chemical formulation 3 4 Doping element Location ZnO ZnO Spinel Zn-jSbjOjj Pyrochlore Bi2 < Zn^-jSbj/3 )06 Bi-rich phases 12Bi203 • Cr2°3 liBijOj • Cr,0 2 3 6-Bi203 i-BijOj 12Bi203 • Si02 Co, Mn Grains Co, Mn, Cr Intergranular phase Co, Hn, Cr Intergranular phase Zn, Sb Triple point Figure 3: Microstructural components of the ZnO varistoi8 chemical formulation and dopants in various phases comprised in varistor structure on the one hand, and their influence on electrical characteristics on the other hand. Schematic view of the real ZnO varistor micro-structure is shown in Fig. 2., which illustrates ZnO grains surrounded by spinel, pyrochlore and several Bismuth phases including intra- and intergranular porosity. The major findings of the mlcrostructure analyses are summarised in Fig. 3.. When the grain is etched out with acid, intergranular phases appear as a three dimensional network, which is electrically conductive under certain conditions (high field, high temperature, etc.) Microstructural study resulted in a vary important conclusion. The primitive varistor or basic building block of a ZnO varistor is a boundary between two grains, being formed during sintering. Different chemical elements and ZnO intrinsic defects are being distributed during sintering so that the grain boundary region becomes highly resistive (Rgb 1012 ncm) and the grain interior highly conductive (Rg =1-10 £2cm). Abrupt conductivity change on the grain boundary suggests the existence of the potential barrier and the depletion layer on both sides of the boundary inside the ZnO grain. It should be pointed out that each grain boundary in doped ZnO shows a nonlinear l-V characteristics, except in the cases, where one of the grains has high symmetry (e.g. basal plane), showing special electrical properties4. Several studies have indicated the presence of a thin (<20A) and homogeneous layer of Bi3,9 and excess oxygen at the grain boundary as shown in Fig.4. The role of Bi in grain boundary activation is very interesting. On the one hand, no varistor effect is obtained without Bi doping. On the other hand Bi concentration at the grain boundary stays unchanged in the cases of postsintering annealing or electric loading, when l-V CONCENTRATION [rtl. unit j ] qO -- ro oi ^ en > ? w 3J 0 X 1 5 m D ui m •o Figure 4: ZnO varistor grain boundaries AES chemical analysis characteristic in the prebreakdown region changes its shape10. Similarly, no correlation has been found between net charge stored at the grain boundary and Bi concentration. That's why it is generally assumed that absorbed Bi ions create some intrinsic interface defects which are capable of capturing an excess electron. Unlike Bi ions, O ions are completely mobile10, their concentration on the grain boundary being in the direct correlation to the l-V characteristic change, i.e. to the potential barrier height and the net charge stored at the grain boundary11. 2.3. Varistor Physics Several physical models have been proposed in the past to explain conductive mechanism in varistor12,13. Their inadequacy was in the fact that they could explain just 163 Informacije MIDEM 24(1994)3, sir. 161-171 Z. Zivic: A Multilayer Chip Varistor: The Future in the Low Voltage Transient Suppression - Part i:... some of the experimental results. Advances in micro-structural analysis at the atomic level and a wide range of electrical and spectroscopical measurement techniques helped Pike to establish the most comprehensive model, being later refined by Greuter and Blatter11,15. The model is based on the fact that a net interface charge at the grain boundary results from the trapping of an excess electron (or hole) by the appropriate interface states. The interface charge Qi is screened by the ionised bulk defects N0, associated with intrinsic defects such as Zinc interstitial or Oxygen vacancies, in order to establish the overall charge neutrality. Visualising this process in an energy band diagram corresponds to the formation of a double Schottky potential barrier at the grain boundary as shown in Fig. 5. The current flowing across the grain boundary is controlled by the applied bias and the temperature dependent height of the potential barrier 0b (V, T). Solving the Poisson equation, several authors12,13,14 obtained that the potential barrier height is 0.9-1.0 eV. It should be pointed out that an increase in Qi results in a larger 0b, whereas a higher No reduces 0b. Applying thermoionic emission model, current flow through the grain boundary can be described by the equation: J = AT2 exp (-(e0s - e„)/kT) (1 - exp(-eV/kT)), where A is a constant containing Richardson's constant, en= Ec - Ef and V is the applied voltage. The existence of the following four current components on the interface is obvious: the thermally emitted electrons travelling from the left to the right and backwards (being suppressed by the factor exp(-eWkT)) and small current of the electrons being trapped and remitted from the interface states. The two last currents are responsible for the updating of Qi, and actually control the main current flowing over the barrier15. When a bias is applied to the junction (V< 3 V), 0b will rapidly decay for a fixed Qi. However, if through the lowering of 0b new empty interface states can be filled, Qi increases and 0b is efficiently stabilised keeping the leakage current low. This is usually referred to as a pinning of b by the interface states. The strong pinning leads to a concentration of the voltage drop within a 1000A wide region on the positively biased side of the junction. Nearthe top of the barrier, electric fields as high as 1 MV/cm can build up. Under this condition some electrons can get enough kinetic energy (became "hot") to create minority carriers by means of the impact ioni-sation. The holes created in this way, diffuse back to the interface (tt < 10"10 s), partly compensate Qi and abruptly lower 0b initiating the breakdown. Energy-band diagram of "hot" electron-hole induced varistor breakdown, different trajectories of "hot" electrons and the creation by impact ionisation are shown in Fig. 6. As the optical-phonon scattering at low energies (0.1 -0.4 eV) is the dominant loss mechanism in ZnO, a high starting field near the interface is the most important to overcome this critical energy range. On the basis of the Figure 6: Energy-band diagram of a grain boundary barrier illustrating the hole induced breakdown 164 Z. 2ivi<5: A Multilayer Chip Varistor: The Future in the Low Voltage Transient Suppression - Part I:... Informacije Ml DEM 24(1994)3, str. 161-171 PRINTING J r LAMINATING Slip: homogenous, ¡flow materials : ZnO, Bi203,... MILLING low viscosive prganic system: acrylic binder 1 ~ I solvents,... CASTING j Green sheets: 1 30 + 1 Jim j Ag Pd electrode Ink ¡I ELECTRODE ( I,CHIP CUTTING Ag or Ag Pd ink i ELECTRODE j [TERMINATING j FIRING TESTING Figure 7: MLV fabrication process steps data on threshold energy for electron-hole pair creation in ZnO (Eth» 3.7 eV) and the yield of the hole production and using the described model Greuter et. al.15 estimated single grain boundary junction breakdown to be Vb = 3.3-3.8 V, which is in a very good agreement with the experimental results. Besides, "hot"-electron-hole induced avalanche breakdown model can explain most basic experimental observations such as: high coefficient of nonlinearity (a > 40) and its dependence on doping, small negative signal capacitance at large bias, voltage overshoot effect under the excitation with fast pulses, electroluminescence phenomena observed at grain boundaries and many other11. 3. Multilayer Chip Varistor Ceramic tape casting and especially green sheet lamination technology have been very intensively developing during the last twenty years, in the first place owing to the development of the multilayer ceramic capacitor and hybrid integrated circuit substrates. These technologies set the basis for the development of the multilayer chip varistor. Although the first article was published by Shohata et. al.16 in 1981 there has been little published about this new protection component, which became commercially available not more than two years ago. 3.1. Technology 3.1.1. Fabrication Process Green sheet lamination process applied in presented MLV production experience is shown in Fig. 7. Varistor processing was based on fine particle high purity ZnO and other dopants. They were mixed in a nonaqueous system based on an acrylic binder in a ball mill for 15-20 h. The homogeneous low viscosity ceramic slip was tape cast into 30-100 thick sheets. Tape cutting was followed by AgPd internal electrode screen printing and their stacking into 10 x 10 cm large green ceramic blocks. Ceramic blocks were then laminated and cut into chips sized 2.5 x 1.5 mm, 3.2 x 2.5 mm and 5.7 x 5.0 mm, which are popular SMD dimensions. After binder burn out, chips were sintered in an air atmosphere furnace at the temperature of 950-1100°C. Finally, external AgPd electrodes were attached and fired to make contact with comb-like inner electrodes as shown in Fig. 8.. Fig. 9 illustrates the outside view and final dimensions of realised chips while Fig. 10 shows optical microscope photographs of the microstructure of the cross sectioned MLV. 165 Informacije MIDEM 24(1994)3, str. 161-171 Z. Zivic: A Multilayer Chip Varistor: The Future in the _Low Voltage Transient Suppression - Part I:... Fired Ceramic Internal External Electrodes Electrodes Figure 8: A cross sectional illustration of a MLV 0 ' ? * 5 Figure 9: Outside view of differently sized ML Vs I V y/ JÇ ' 'ta- Jv- , ^^ ■ .■ >o v. f ■ ; / ' //¿ITM * ' V' Figure 10: Microstructure photographs of a cross section of an MLV 3.1.2. Varistor Compositions Shohata et. al.17 concluded that the utilisation of Bi2C>3 in MLV ceramic system is not possible because it easily reacts with any metal used for internal electrodes, destroying the multilayer structure. That's why, instead Bi203, they especially developed and suggested the usage of borosilicate-lead-zinc glass. Microstructural analysis of the ceramic- electrode interface18 showed increased concentration of Bi in the case of low sintering temperatures (950°C), while at higher temperatures (1100°C) a iamelar reaction product, identified as PdBi204, was observed only in the "pockets" of a melt at the interface. TEM/EDS studies of the interface confirm that the reaction layer is neither continuous nor monophase. Due to that and opposite to the statements in17, it was shown in19 and it will be shown in this paper that usage of Bi2C>3 is possible in varistor system without consequences either to the electrical characteristics or varistor reliability. Having this in mind, special varistor composition was designed20,21, comprising ZnO (>92 wt %) and oxide additives such as BÎ203, MnO, CoO, Sb203, etc. As the composition presents one of the design parameters, the care was also taken of the fact, that some differences exist in the case of the bulk varistors and MLV, the final ceramic layer thickness being both small and comparable to the grain size in the later. Two such examples are illustrated in Fig. 11. and Fig. 12.. They show the dependence of nonlinearity coefficient and specific voltage on sintering temperature in the case of MLV (layer thickness « 17 ¡im) and bulk varistor (d = 1 mm), realised with the same composition. Figure 11: Nonlinear coefficient - a Versus sintering temperature 1000 1050 T (°C) 1150 Figure 12: Specific voltage versus sintering temperature 166 Z. 2ivi<5: A Multilayer Chip Varistor: The Future in the Low Voltage Transient Suppression - Part I:... Informacije Ml DEM 24(1994)3, str. 161-171 3.1.3. Ceramic Foil Presently, it is possible to use two processes for thin ceramic foil formation: extrusion & stretching process and doctor-blade tape casting process. We applied both processes to form varistor ceramic foil. The results of the second process will be shown in this paper. Nonaqueous tape casting system, containing acrylic binder, solvents, defloculants, plasticiser and some other additives, was used, enabling formation of homogeneous, stabile, low viscosity slurry, during homogenisation of varistor ceramic system. After homogenisation, the slurry travels on the carrier surface beneath the blade of the knife, that controls the thickness of the out-coming layer. When the solvent evaporates, the fine solid particles coalesce into a relatively dense flexible film that may be stripped from the carrier surface in a continuous sheet. Foils obtained in such a way have good mechanical firmness (enabling simple manipulation) and no pin hole defects. Besides, in the whole range of thicknesses no "skin" effect has been observed as illustrated in Fig. Figure 13: SEM photograph of the tape cast foil surface 13., showing the appearance of the surface of the varistor tape cast foil. 1000 1050 T ( °C ) 1100 1150 Figure 14: Breakdown voltage versus sintering temperature for different sheet thicknesses As seen in Fig. 8. inner electrodes are set parallel to each other, where each second electrode is displaced to the same side, so that one group of electrodes is electrically connected to the end termination on one side and the other to the end termination on the other side of the chip. This finger- or comb-like electrode structure enables optimum usage of material volume and shows the whole array of other advantages. Inner electrodes ? r , f t ' te, , « f., " » . ■•.->. », * ■ K-trV ' \ i- '"V.?- y- - T V. «*- . _ . ' » »» " -»' ' ' . » * "v ^ . „ .... . - • •' SS * ' 3.2 Chip Design and Structure Based on considerations in #2.3. the overall varistor breakdown voltages could be calculated as n x 3.6 V, n being the mean number of grain boundaries along the shortest linear path between electrodes. Following this principle a low voltage MLV can be designed combining the ratio of the ceramic foil thickness and ZnO grain size. However, this procedure is limited by the opposing requirements for certain electrical characteristics, processing and surface mount technology. Fig. 14. shows the breakdown voltages (at 1 mA) dependencies on sintering temperature with green sheet thickness as a parameter, while Fig. 15. shows the photograph of a) 4 V and b) 56 V sectioned MLV at the same magnification. liiÂiïl ill»» M»iP . ' Y-.'.'FV.Vi.^ ^ ' - ■ " " v-r t - • .•;«■■-:• v"-. :• - ? - , t' s o.*'-è Figure 15: Photograph of cross-sectioned 4 V and 56 V MLV 167 Informacije Ml DEM 24(1994)3, str. 161-171 are encircled with varistor ceramics, so that there are no parasitic structures between adjacent electrodes, meaning that there are no paths causing surface leakage currents or enabling flash-over breakdown. Moreover, this way of electrode design enables their relatively large active surface with respect to chip volume. This is especially evident when compared with the bulk varistor. This electrode disposition enables very uniform current and energy volume distribution, avoiding "hot" spots in the structure, which is of great importance when stability and reliability are concerned. Beside inner electrode surface, their periphery is important as well. Being very long it facilitates peripheral electrode current injection, similarly as with high current power transistors and acts as an "amortiser" of extremely high current surges. Being good heat conductors inner electrodes have dual positive role, in the case of ambient heating, they minimise large temperature differences between chip sides, helping uniform microstructure formation and prevent defect diffusion and electrical characteristic degradation. In this case they act as ideal internal heaters. On the other hand, during internal heating due to DC, AC or pulse loading, they conduct heat outwards and act as coolers. This provides fast varistor heat dissipation through the volume, shifting failure mechanism toward higher temperatures. This is one of the reasons that MLV is the only varistor capable of operating at +125°C, whereas the maximum operating temperature of other varistors is +85°C. 3.3. Electrical Properties 3.3.1. Current-Voltage Characteristics MLV s with breakdown voltage in the range from 4 V to 100 V were realised in the above described way. It should be emphasised, that 4 V breakdown is practically, the lowest theoretically possible breakdown in ZnO varistor (see #2.3.). Achieved result illustrates that, it is possible to realise controllable microstructure, such, that in the cross section between the adjacent large surface electrodes there is only one grain boundary on the average, i.e. the whole structure acts as one large equivalent monobarrier. Fig. 16 a) and b) shows symmetrical AC l-V characteristics of 4 V and 56 V varistor respectively. The sharp breakdown knee is typical for these high devices with a clearly defined threshold voltage. This is even more evident in Fig. 17, presenting measured l-V relationships. Wide current range measurements were provided using DC technique up to 10 mA and the pulse (8/20 jus) technique above this value. In both cases characteristics show distinct difference between the prebreakdown and breakdown region, which extends over six (for 4 V MLV) to seven (for 56 V MLV) orders of magnitude of current. Typical values of the nonlinear coefficient a measured Z. 2ivi<5: A Multilayer Chip Varistor: The Future in the _Low Voltage Transient Suppression - Part I:... mmm HQ 111 Figure 16: AC current-voltage characteristics of the a) 4 V and b) 56 V MLV by the ALPHA meter in the current range from 1-10 mA usually exceeds 25 and in some cases reaches values over 50. It is especially important that a has so high value within the whole breakdown region. Fig. 18. illustrates the example of 33 V MLV (5.7 x 5.0 mm), where a has the value >15 in the current range up to 1000 A, above which its value decreases and correlates with upturn region on the l-V characteristics. Protection level coefficient, defined as the ratio of clamping voltage for any specified current and the breakdown voltage at 1 mA, has the value < 2.5 up to the current value of 1000 A, increasing for the higher currents. It means that MLV provides very effective protection in the wide current range. In the prebreakdown region MLV shows very low leakage current (typically < 5 jliA), meaning at the same time, a low DC watt loss upon steady state operating voltage, typically set between 75-85 % of the threshold voltage. Although the leakage current increases with temperature, as shown in Fig. 19., for the case of 4 V MLV measured at Vdc = 3 V, it holds relatively low value even for the temperatures as high as +125°C, enabling its normal operation in that temperature range as well (see #3.2.). The linear relationship between current and temperature in semilogarithmic scale confirms the th'er-moionic emission mechanism, i.e. the validity of physical model described in #2.3.. The measured threshold voltage temperature coefficient is much lower than 0.01 %/°C in the temperature range from +25°C to +85°C. 168 Z. Zivic: A Multilayer Chip Varistor: The Future in the Low Voltage Transient Suppression - Part I:... Informacije MIDEM 24(1994)3, sir. 161-171 1E + 04 1E + 03 1E + 02 1 E + 01 1E + 00j 1E-01 1E-02 1E-03 1E-04 1 E-05 1 E-06_ j 1 1 E-07 j 1 E-081 1 1 1E-09 j 1E-10 Vn = 4 V Vn - 56 V I I MUM i I I :i 0.1 1.0 10.0 V ( V i 100.0 1000.0 1 E-05 1 E-07 4-0 75 T i °C 150 Figure 17: Current-voltage characteristics of 4 V (3.2 x 2.5 mm) and56 V (5.7x5.0 mm) MLV Figure 19: Temperature dependence of DC stand-by current (Vtic = 3 V) of the 4 V MLV 3.3.2. Capacitance and Response Time Dielectric constant of ZnO is relatively small (=10), while the effective dielectric constant of the varistor ceramics is about 100 higher as the consequence of intergranular barriers and their nature (see #2.3.). Capacitance of MLV with different breakdown voltages measured at 1 kHz, ranged from 0.5-40 nF, depending on the chip dimensions, layer thickness and their number. MLV capacitance is relatively stable over a wide frequency range, up to 1 MHz, as shown in Fig. 20.. The same figure shows bell shaped frequency-loss factor characteristics with the minimum value typically at 10 kHz. , The capacitance temperature change, in the temperature range from +25° to +85°C, is < 15 %. Such a medium MLV capacitance value, which to a certain extent can be designed is especially desirable in specific applications to be discussed in the Part II: Advantages and Applications. MLV chip has very low inductance, typically < 1.5 nH. The voltage response overshoot effect, being controlled by inherent parasitic lead inductance, is typically not observed in the case of 8/20 ja.s pulse, as illustrated in Fig. 21.. This figure shows 54 V pulse response charac- , 1E-07; 1E+00 « :1E-01 co 1 E+01 1E +02 1E+03 1E+04 1E+05 1E+06 1E+07 Frequency ( Hz ) . Figure 18: Nonlinear coefficient~a and protective level versus current Figure 20: Capacitance and loss factor variation with frequency of the 8 V MLV 169 Informacije Ml DEM 24(1994)3, str. 161-171 Z. 2ivi<5: A Multilayer Chip Varistor: The Future in the _Low Voltage Transient Suppression - Part I:... ri/d\u IRfl at Vri: Ci iiE/.'dli : 30 j V Figure 21: Pulse absorption characteristics of 33 V MLV (8/20 20 A; Hor. : 10 ps/div, Ver. : 351 x 25 mV/div) teristics of a 33 V MLV after triggering with 20 A of 8/20 las pulse. Our present equipment has enabled us to estimate the response time of MLV to be definitely < 5 ns, being adequate for protection in electrostatic discharge environment. 3.3.3.Stability and Reliability MLV stability and reliability are especially important regarding the fact that it is intended to be protective device. To estimate its stability and reliability a number of tests were performed. The result of high current amplitude and high energy surge withstand capability tests are shown in Fig. 22 and 23.. Standard surge pulse shapes of 8/20 ¡is and 10/1000 |as were used. The relative threshold voltage change is plotted as a function of the number of surges. It is evident in Fig. 22. that in the case of 8/20 (is pulse threshold voltage increases somewhat faster during the first 10 surges, the change being slower afterwards. The change is lower than 5 %, even after 500 surges. The value of this result can be fully evaluated, having in mind that threshold voltage change of 33 V standard 20 mm disc varistor is higher than 10 % already after 100 to 150 surges. Similar results were obtained in the case of 10/1000 s pulse as shown in Fig. 23. It illustrates excellent stability of MLV pulse = 500 A 6-4-2- ~4--6--8- Vn =33 V Chip size = 5.7 x 5.0 mm T = 25 °C Pulse 8/20 jis 10 too Number of surges Figure 22: Repetitive pulse capability (30 s between pulses) 1000 I pulse = 120 A Il pulse = 12.5 J v 1 pulse = 60 A ■ : = 33 V T = 25 °C ' Chip size = 5.7 x 5.0 mm Pulse 10/1000 |im 10 100 Number of surges Figure 23: High energy repetitive pulse capability (30 s between pulses) even in the case of 12.5 J pulses. During this test 33 V MLV was cumulatively absorbing the energy of more than 6 kJ in the period of 4 h, without substantially changing its characteristics. Similar threshold voltage change in the cases of different MLV pulse loading, suggests activation of the same failure mechanism, with no regard to the pulse duration or its shape. As, varistors are, generally speaking, very sensitive to DC loading in the prebreakdown region, a continuous power dissipation life test was performed on 4 V MLV. The DC applied voltage was higher than the threshold voltage, i.e. the 4 V MLV was subjected to a 10 mA and 30 mA current. A stability that can not be obtained with any low voltage disc varistor is apparent in Fig. 24. Even after 80 min of loading with current of 30 mA, the threshold voltage change was not higherthan 15%. This result, as well as all the others, again confirms the consideration in #3.2. and proves the possibility of realising of a very homogeneous and ordered mictrostruc-ture by means of thin ceramic layer technology. (+) (+) Idc = 10 mA idc = 30 mA Figure 24: Continuous power dissipation life test of 4 V ML V. The marks (+) and (-) indicate the Vn change in the same and the opposite polarity with DC bias. 170 Z. 2ivi<5: A Multilayer Chip Varistor: The Future in the Low Voltage Transient Suppression - Part I:... Informacije Ml DEM 24(1994)3, str. 161-171 4. Conclusion A low voltage MLV was developed using tape casting and green sheet lamination technology. Obtained electrical characteristics showed that the utilisation of Bi203 is possible in MLV ceramic system. Namely, MLV has high nonlinearity coefficient in the whole breakdown range, i.e. low clamping level, providing high protection efficiency. It was also shown that with respect to its planar surface MLV can withstand pulse density loading higher than 7000 A/cm2, being far higher than in any protective device known today. Besides, leakage current in prebreakdown region has relatively small value even in the temperature range around +125°C. Very low inductance of chip MLV enables response time shorter than 5 ns, eliminating to a great extent voltage response overshoot effect. Life test results, and especially repetitive pulse capability tests show MLV excellent capability to withstand great number of short high voltage surges as well as long high energy surges. Practically all static and dynamic characteristics as well as MLV stability lead to the conclusion that and MLV is favourable low voltage protective device. Acknowledgement The author would like to thank Dr. M. Kosec, Dr. M. Trontelj and Prof. Dr. D. Kolar and D. Ročak from the Institute Jožef Stefan in Ljubljana for helpful discussions and advice and the colleague and spouse A. Živič for encouragements and many valuable suggestions throughout this work as well as to all colleagues from KEKO for their support. References 1. S. M. Sze, "Physios of Semiconductor Devices", Wiley, N. Y. 1981, pp.63-133 2. A.S. Grove, "Physics and Technology of Semiconductor Devices", Wiley, N. Y. 1967, pp.1-208 3. F. A. Kroger, "Chemistry of Imperfect Crystals ", Wiley, N. Y. 1974, Vol. 2, p. 752 4. D. R. Clarke, "The Microstructural Location of the Intergranular Metal RROxide Phase in a Zinc Oxide Varistor", J. Appl. Phys. 49 (4), pp. 2407- 11, 1978 5. A. T. Sauthanam, T. K. Gupta, W. G. Cavison, "Microstructural Evaluation of Microcomponent ZnO Ceramics", Appl. Phys., 50 (2), pp. 852-59, 1979 6. J. Wong, W. G. Morris, "Microstructure and Phases in Nonohmic Zn0-Bi203 Ceramics", Am. Cer. Soc. Bull. 53, pp.816, 1974 7. A. Lagrange, "Present and Future of Zinc Oxide Varlstor", El. Cer., Ele sevier, London, 1991, pp.1-27 8. T. K. Gupta, "Application of Zinc Oxide Varistors", J. Am. Cer. Soc. 73(7), pp. 1817-1840, 1990 9. E. Olsson, G. L. Dunlop, R. Osterlund, "Interfacial Barriers to Electrical Conduction in ZnO Varistor Materials", Proc. of the Sec. int. Varistor Conf., pp.65-72, Schenectady, N. Y. Dec. 5-6, 1988 10. F. Greuter, G. Blater, M. Rossinelli, F. Stucki," Conduction mechanism in ZnO Varistors : An Overview", Proc. of the Sec. Int. Varistor Conf., pp. 31-53, Schenectady, N. Y. Dec. 5-6, 1988 11. F. Greuter, G. Blater, "Electrical Properties of Grain Boundaries in Polycrystalline Compound Semiconductors", Semic. Sei. Tech-nol. (5), pp. 111-137, 1990 12. L. M. Levinson, H. R. Philip, "ZnO Varistors - A Review", Cer. Bull. 65(4), pp. 639-646, 1986 13. R. Einziger, "Metal Oxide Varistors", Ann. Rev. Mater. Sei. 17, pp. 299- 321, 1989 14. G. E. Pike, "Electronic Properties of ZnO Varistors : A New Model", Mater. Res. Sei. Proc. 5, pp. 369-78, 1982 15. F. Greuter, G. Blater, "Current Control by Electrically Active grain Boundaries ", Proc. of the Int. Symp. of Polycrystalline Semiconductors - Grain boundaries and Interfaces, pp. 302-314, Malente, Germany, Avg. 29- Sept. 1988 16. N. Shohata, T. Matsumuka, K. Utsumi, T. Ohno, "Properties of Multilayer ZnO Ceramic Varistor", pp.349-358, in Advances in Ceramics, Vol. 1, Ed. L. M. Levinson, Am. Ceram. Soc., Columbus, OH, 1981 17. N. Shohata, M. Nakanishi, K. Utsumi, "Multilayer Ceramic Chip Varistor", pp.329-337 in Advances in Ceramics, Vol. 3, Ed. L. M. Levinson, Am. Ceram. Soc., Columbus, OH, 1989 18. M. Trontelj, Z. Živič, G. Dražič, Z. Samardžija, "The Microstructure of a Multilayer Varistor", Proc. of Conf. MIEL-SD'93, Bled, Sept. 1993, pp. 143-148 19. Z. Živič, M. Kosec, "Properties of a 4 V Multilayer Varistor", Proc. of Conf. MIEL-SD'92, Portorož, Sept. 1992, pp.419-424 20. Z. Živič, "Universal Composition for Varistor Production", Pat. No. 9200421, Slovene Patent Bureau, LJubljana, 1992 21. Z. Živič, "Low Leakage Current Varistor Composition", Pat. No. 9300426, Slovene Patent Bureau, Ljubljana, 1993 Zoran Živič, M.S.E.E. KEKO, d.d. Ceramic Capacitor Factory Grajski Trg 15 68360 Žužemberk Slovenia tel. + 386 68 87 230 fax+ 386 68 87 315 Prispelo (Arrived): 15.08.94 Sprejeto (Accepted): 20.09.94 171 Informacije MIDEM 24(1994)3, Ljubljana UDK621.3:(53+54+621+66), ISSN0352-9045 PLANAR LC OPTICAL SWITCH FOR OPTICAL COMMUNICATIONS J. Pirš, S. Kopač, R. Lu kač and B. Marin Jožef Stefan Institute, Ljubljana, Slovenia Key words: optical communications, optical switches, LC planar technology, liquid crystals, LC, nematlc liquid crystals, electronical fields, refractive indexes, optical waveguides Abstract: A planar electrooptical light switch and crossbar interconnection network specifically designed for optical fiber communications is described. It is based on the use of the homogeneously aligned nematic liquid crystals acting as the active elements for light beam splitting and redirecting. Several possibilities based on electrically controlled birefringence in nematic LC are described and the estimate on the dimensional limitations based on the calculations of the electric control field are given. The presented LC optical crossbar can be addressed electrically and can be miniaturized. This makes it particularly interesting anywhere where large number of interconnecting switching of optical light signals is required (i.e. telephone centrals,...) Planarno tekoče kristalno optično stikalo za optične komunikacije Ključne besede: Komunikacije optične, stikala optična, LC tehnologije planarne, LC kristali tekoči, LC kristali tekoči nematični, polja električna, količniki lomni, valovodi optični Povzetek: Opisano je planarno tekočekristalno optično stikalo, kije posebej primerno za optične komunikacije. Stikalo uporablja homogeno urejeno plast tekočega kristala, ki se mu z električnim poljem lahko spreminja lomni količnik - električno kontrolirana dvolomnost. Opisane so različne možnosti uporabe tega efekta v nematskih tekočih kristalih.Na osnovi izračuna električnega polja znotraj tekočekristalne celice je podana ocena maksimalnih možnih dimenzij takega optičnega stikala. Prednosti tekočekristalnega optičnega stikala so predvsem v majhnih dimenzijah in možnosti električnega krmiljenja z nizkimi napetostmi, zato je posebej zanimiv za uporabo povsod, kjer je zahtevano veliko število optičnih stikalnih elementov (npr. telefonske centrale,...) INTRODUCTION A number of different technical solutions using liquid crystals for switching the light signals between different optical fibers has been made so far1,2,3,4. They are based on different electrooptic mechanisms in liquid crystals from electrically controlled refractive index variations causing light coupling between optical waveguides5, total light reflection6, electrically controlled birefringence and electrically controlled light scattering7. Most of these solutions require the use of expensive optic elements (prisms, polarization beamsplitters,..), their construction is nonplanar and they cannot be miniaturized. In this paper we propose a construction of an LC switching device based on the fact that LC itself can be used as a waveguide as first pointed out by Giallorenzi et al.9 and later by M.Kawachi et al.4. Moreover, using a light, the electrically controlled birefringence of LC can be used to generate electrically induced light guide be- •iOUNRARY GLAS;: /PLATE -( ::K'-;AT:C liquid 5=? Z' CRYSTAL ■ i r::?iJT ? IÏRE ELECTEOLES Figure 1: Schematic presentation of the electrically induced optical waveguide in the homogeneously aligned nematic LC 172 J. Pirè, S. Kopac, R. Lukac, B. Marin: Planar LC Optical Switch for Optical Communications_______ Informacije MIDEM 24(1994)3, str. 172-177 tween the properly shaped electrodes (see Fig. 1) in a standard, homogeneously aligned nematic LC cell. If the polarization of the propagating light is perpendicular to the boundary glass plates of the homogeneously aligned nematic LC (positive dielectric anisotropyl) cell, than the applied electric field between the electrodes on the boundary plates causes, that the refractive index (ne) of the LC between the electrodes becomes greater than in the area without the electrodes as well as greater than the refractive index of the boundary glass plates. So the conditions for optica! waveguiding are met and an electrically induced waveguide is formed within the LC layer between the electrodes. The difference between the ordinary and extraordinary refractive index determines the numerical aperture of this waveguide and imposes the limitations on its maximum curvature. With the appropriate design of the electrodes different electrooptical switching devices can be made consisting of several electrically induced optical LC waveguide segments. So electrooptical directional elements, cros-spoints and even a complex matrix of such switches can be made (see Fig. 2, 3, 6). ;n/out X X \ /" V A x x X X X in/o X \ A { V A/\ vX A / \ i \ X -----A' X X ---------B' Figure 3: LC matrix 8x8 crossbar switch 1,2,6,7 electrically induced light guides 3/i,5 switching light guide segments 0,9,10 eiectrodes for inner light guide segments Figure 2: 2x2 Optical cross-bar switch 173 Informacije Mi DEM 24(1994)3, sir. 172-177 J. Pirs, S. Kopac, R. lukac, B. Marin: Planar LC Optical __Switch for Optical Communications EXPERIMENTAL The concept of electrically induced optical waveguide switches was verified by means of different homogeneously aligned LC cells with appropriate electrode configurations. The cells were made in a more less conventional way. ITO covered glass plates were used. After photolithografic formation of the required electrode pattern, the glasses were covered with thin Nylon orienting layer and rubbed to provide for the homogeneous orientation. Ten micron thick cells were made and filled with F.Hoffmann-La Roche nematic liquid crystal ROTN 0530 (n0=1.513, ne=1.718). The following electrode patterns were used: 1 .Half plane electrodes - determination of the angle of total reflection (see Fig. 4a,b,c) 2.Straight 50-micron wide lines - basic concept of the electrically induced optical waveguide; numerical aperture determination (see Fig. 5) 3.Directional switch (see Fig. 6a,b,c) - evaluation of the switching performances, light losses, etc... The signal light beam was simulated by a He-Ne laser that was coupled to the LC optical switch by a focusing lens and a precision x-z stage. The traveling of the light signal within the LC optical switch was monitored by observing the light scattered by the order parameter fluctuations under the low amplification microscope by means of the CCD camera coupled to a PC computer. RESULTS AND DISCUSSIONS The results of the evaluation of the electrically induced optical waveguide switch concept are shown on figures 4 through 6. ■■IIH mm/mm fflmmšmmmsMsmšmmmmm ¡¡¡¡I msKimM^mai »»^^H ammÊÊSÊÊÈÊÊÊÊËÊIm Figure 4: Signal light beam reflection on the electrically induced "refractive index barrier": a.) Schematic presentation of the light beam and half plane electrodes b.) Signal light beam propagation without electric field c.) Signal light beam reflection at the electrically induced refractive index barrier 174 J. Pirè, S. Kopac, R. Lukac, B. Marin: Planar LC Optical Switch for Optical Communications_ Informacije MIDEM 24(1994)3, str. 172-177 Figure 5: Electrically induced optical waveguide: the signal light beam is traveling along 50 ¡im wide straight LC waveguide. Since the incidence angle is different from zero but smaller than the one determined by the angle of total reflection, the light beam is reflected back and forth, but stays within the waveguide. in order to evaluate the limitations and performances of this optical signal switching concept, a detailed computer analysis of the average refractive index variations based on the computer simulation of the nematic director fields within the LC optic waveguide switch was made. The refractive index was calculated for the biréfringent medium according to the formula: nef (©) ne n0 Vno+ - no J sin2© (1) The nematic director fields were obtained as a result of the numerical solution of the relaxation equation for the director fields: 3 Vi = k 'Ji + JL' ydx2 + dy2J n, + AeEi ^ EjOj + Xnj (2) j=i where E is the electric field, Ae dielectric anisotropy and X is a normalization constant. Figure 6: LC optical directional switch: a.) Schematic presentation of the electrode pattern b.) Signal light beam propagation with the switching segment turned off c.) Signal light beam propagation with the switching segment turned on 175 Informacije MIDEM 24(1994)3, sir. 172-177 J. Pirs, S, Kopac, R. Lukac, B. Marin: Planar LC Optical __Switch for Optical Communications This relaxation equation was coupled to the equation for the electric field: E= -gradV; div(£(x,y) gradV(x,y)) = 0, where: e = e^ + Aen^. Aenxny in LC and £ = eo outside. Aen^riy e -f Aeal (3) I / / I / / / / /-- —/ -■>■ / / / / / / -/ I I -/ / I '/ I I -/ I I -/ I I I I / I --/ / / / / / / / I I I I I I I I I I I I / / aJ Assuming strong anchoring conditions at the boundary surface, this relaxation equation was solved numerically using SOR method (Simultaneous over-relaxation)00'. The results for a segment (Fig. 7) between two parallel electrically induced wave guides are shown on the Fig. 8 and Fig. 9. A v=u ::LO: CeH:: v=o a x / / / / / / / / / ////// / I —— ------- / ////// I 1 — / 1 1 1 I I I 1 I 1 --"---// / /MM/ /// / //Ml/ / 1 / — / 1 I 1 1 1 1 /11/ — 1 1 1 I 1 I I I 1 ---'// J 1 1 1 1 ! 1 / I / — '--"'/ / I 1 1 1 1 I 1 / / / / /1/111 III/// /// -—• / / / / / ---l ////// / / — / / / I//////I I ////// / //////// ////// ////// II///! I / / / / / ////// ////// ////// / I / I / I •/ / I / / / Figure 7: Shematic presentation of the waveguide segment These results, which are also well confirmed by the experimental data (see Fig 4, 5, 6), clearly show, that: 1. The electrically induced waveguides are well separated if the electrode distances are more than two LC cell gaps apart. In this case one cannot expect much of the crosstalk between them. 2. If the electrodes are closer than one LC cell gap apart, the light signal passes from one waveguide to another almost without any light loss. 3. The switching waveguide segments of the LC light switch have to be wider than two LC cell gaps and should be located closer than one cell gap to assure good switching. The anisotropy of the refractive index (ne -n0) in modern nematic LC materials can be as high as = 0.25. This c.) Figure 8: Plot of the director fields for different spacing of the electrodes: a.) spacing is equal to four LC cell gap b.) spacing is equal to two LC cell gaps c.) spacing is equal to one LC cell gaps imposes a limit to the maximum curvature of the electrically induced optical waveguides. So an optical crossbar switch (Fig. 2) has to be = 200 |im long. Since order parameter fluctuations in nematic LC are causing relatively strong light scattering (light loss!), the area of the total optical switching array is limited to 600x600 )j.m. This means that the 8x8 switch array (Fig. 3) is the maximum, that one can expect from the nematic optical switches as described in this paper. 176 J. Pirs, S. Kopac, R. Lukac, B. Marin: Planar LC Optical Switch for Optical Communications__ Figure 9: Plot of the refractive index between the electrodes for different electrode spacings (b): b=1 LC cell gap, b-2 LC cell gaps, b=4 LC cell gaps REFERENCES 1. M.R,Meadows, M.A.Handschy, N.A.Clark, Appl.Phys.Lett., 54, 1394 (1989) 2. R.A.Kashnow, C.R.Stein, Appl.Opt., 12, 2309 (1973) Informacije MIDEM 24(1994)3, str. 172-177 3. Y.Fujii, Appl.Opt. 28, 4968 (1989) 4. M.Kawachi, N.Shibata, T.Edahiro, Jap.J.Appl.Phys, 21, L162 (1982) 5. US patents: 4,720,174, 4,278,372, 4,773,136 6. US patents: 4,385,799, 4,720171, 4,737,019 7. US patents: 4,775,038, 4,478,494 8. R.BIinc, J.W.Doane, B.Marin, I.Musevic, J.Pirs, S.Pirs, S.2umer, S.Kopac: "Liquid crystal light valve array optical cross-bar", US pat appl.# 289 476 9. Gialorenzi et al. "Liquid crystal waveguide", US Patent 3,963,310 10. W.H.Press, B.P.FIannery, S.A.Tenkolsky, W.T.Vetterling, Numerical Recipes (Cambridge Univ.Press, New York, 1989) Janez Pirš, Samo Kopač, Renato Lukač and Bojan Marin Jožef Štefan Institute, Jamova 39, 61111 Ljubljana, Slove nía tel. +386 61 125 91 99 fax+ 386 61 126 1026 Prispelo (Arrived): 01.09.94 Sprejeto (Accepted): 20.09.94 177 Informacije MIDEM 24(1994)3, Ljubljana UDK 621.3:(53+54+621 +66), [SSN0352-9045 SENZORJI TLAKA REALIZIRANI S POMOČJO DEBELOPLASTNE TEHNOLOGIJE S. Šoba, D. Belavič, M. Hrovat , B. Pavlin, A. Simončič ^ Iskra Hipot d.o.o., Šentjernej, Slovenija Institut Jožef Stefan, Ljubljana, Slovenija Ključne besede: senzorji tlaka, senzorji piezoupornostni, senzorji industrijski, mikroelektronika, tehnologije debeloplastne, pretvorniki tlaka, senzorji multipleksni, NTC termistorji, inovacije tehnološke, doravnavanje, doravnavanje lasersko, tolerance ozke Povzetek: Zastavljeni namenski cilj razvojnega projekta - povečanje tržnega deleža na področju senzorjev tlaka - je dosežen. Razvili smo skupino industrijskih senzorjev tlaka. Posebej bi omenili multiplex senzor in družino senzorjev ter pretvornikov za različna tlačna področja. Poleg tega smo osvojili različna znanja in razvili nove tehnološke postopke, ki so uporabni tudi za druge izdelke. Poudarili bi tehnološke inovacije pri debeloplastnem senzorju sile, doravnavanju debeloplastnih NTC termistorjev do ozkih toleranc in zapiranja mehansko občutljivih debeloplastnih vezij v plastična ohišja. Pressure Sensors Realized by Thick Film Technology Keywords: pressure sensors, piezoresistive sensors, industrial sensors, microelectronics, thick film technologies, pressure transducers, multiplex sensors, NTC termistors, techological innovations, trimming, laser trimming, narrow tolerances Abstract: The purpose of research and development project - an increased pressure sensor market share - has been achieved. The group of Industrial pressure sensors (multiplex sensor, the family of sensors and transducers for different pressure etc.) was developed. The various "know-how" were acquired and new technological processes usable also on other fields, have been developed. As examples thick film strain gauge, laser trimming of thick film NTC thermistors to narrow tolerances and encapsulation of stress sensitive thick film circuits could be mentioned. Uvod V letih 1991 - 1993 je potekal projekt "Senzorji tlaka realizirani s pomočjo debeloplastne tehnologije", ki ga je z 20% deležem sofinanciralo Ministrstvo za znanost in tehnologijo Republike Slovenije. Naročnik projekta je bila ISKRA HIPOT, Tovarna elektronskih elementov in opreme, d.o.o., Šentjernej, Trubarjeva 7, izvajalci projekta pa Institut Jožef Štefan in Iskra Razvojno raziskovalni inštitut lEZE RO HYB Šentjernej ISKRE HIPOT. Projekt je bil zastavljen na podlagi uspešne realizacije 01 23456789 10 Slika 1: Senzor za merjenje krvnega tlaka za enkratno uporabo in redne velikoserijske proizvodnje senzorja za merjenje krvnega tlaka za enkratno uporabo (slika 1). Omenjeni senzorje aplikacija piezoupornostnega silicijevega senzorja tlaka (slika 2) na debeloplastnem kompenzacijskem vezju, narejenem na keramičnem substratu (slika 3). Dobro obvladovanje proizvodnje senzorja krvnega tlaka je dajalo utemeljeno podlago za razmišljanje o uporabi podobne in še bolj dodelane tehnologije za razvoj novih izdelkov s področja senzorjev tlaka. Zastavljen je bil projekt, čigar končni cilj je bil Slika 2: Piezoupornostni silicijev senzor tlaka na debeloplastnem kompenzacijskem vezju 178 S. Soba, D. Belavič. M. Hrovat, B. Pavlin, A. Simončič: Senzorji tlaka realizirani s pomočjo debeloplastne ... Informacije MIDEM 24(1994)3, str. 178-181 HITI 1 1111 j! 111JIUI j 111MIII i j 1111J i! 111111 i j I i11 j i O 1 Slika 3: Keramična ploščica s 16 piezoupornostnimi silicijevimi senzorji tlaka na debelo- plastnem kompenzacijskem vezju Slika 4: Multiplex senzor (modul z 8 silicijevimi senzorji tlaka za tlačno področje do 1 bar in dvema 4-kanalnima CMOS multiplexerjema) razširiti tržni delež na področju senzorjev tlaka. Na podlagi analize trga smo se odločili za naslednje seg-mentne cilje projekta: — industrijski senzorji in pretvorniki z uporabo debeloplastne tehnologije — kompenzirani senzorji tlaka ža uporabo v procesni industriji v različnih izvedbah — aplikacije senzorjev in pretvornikov za uporabniška vezja — debelopiastni senzor sile z različnimi aplikacijami — medicinski senzorji tlaka (možganski senzor tlaka, senzor krvnega tlaka nove generacije Predstavljamo rezultate raziskovalnega dela, ki se kažejo v osvojitvi novih trgov, novih proizvodih in novih proizvodnih postopkih, tehnoloških inovacijah in patentih. Predstavitev rezultatov projekta Rezultate projekta lahko uvrstimo v tri skupine glede na doseženo stopnjo uporabe in prenosa v proizvodnjo. V prvi skupini predstavljamo raziskovalne dosežke iz vseh segmentnih ciljev projekta, ki so prišli v redno proizvodnjo in ki jih uspešno tržimo. S temi izdelki je bila dosežena Osvojitev novih trgov Na področju Industrijskih senzorjev je bil za proizvod multiplex senzor narejen kompleten razvoj proizvoda od ideje do tržne realizacije. Proizvod je v redni proizvodnji. Multiplex senzorje aplikacijsko vezje, ki se sestoji iz 8 silicijevih senzorjev tlaka za tlačno področje do 1 bar in dveh 4-kanalnih CMOS multi-plexerjev (slika 4). Namenjen je uporabi v sistemu, kjer je potrebno hitro preletavanje točk merjenega pritiska. Krmiljenje (CMOS logika) in kompenzacija Slika 5.6: Plošča s 15 moduli multiplex senzor s skupno 120 senzorji tlaka; plošča vključno z vsemi cevkami in priključki merjenih vrednosti iz senzorjev se opravlja računalniško oz. mikroprocesorsko. Za kupca smo razvili tudi ploščo s tiskanim vezjem, na katerem je 15 modulov multiplex senzor s skupno 120 senzorji tlaka. Tiskano vezje je načrtovano tako, da 179 Informacije MIDEM 24(1994)3, str. 178-181 S. Soba, D. Belavič. M. Hrovat, B. Pavlin, A. Simončič: Senzorji tlaka realizirani s pomočjo debeloplastne ... bustno ohišje. Vsi pretvorniki so kompenzirani v temperaturnem področju 0 - 70°C. Od faze ideje do prototipa so bili razviti naslednji proizvodi, ki jih iz različnih razlogov zaenkrat še ni v redni proizvodnji, nekatere rezultate iz razvoja teh izdelkov pa že uporabljamo v drugih proizvodih iz redne proizvodnje senzorjev. nnnniinrrinnm lili! Slika 7: Senzor tlaka za diferencialni tlak 0-1 bar oz. O-Sbar omogoča hitro preletavanje vseh senzorjev in zapis meritev v računalnik. Tudi to ploščo vključno z vsemi cevkami in priključki redno proizvajamo (slika 5, slika 6). Na področju kompenziranih senzorjev tlaka za uporabo v procesni industriji je v redni proizvodnji senzor tlaka za diferencialni tlak 0-1 bar oz. 0-5bar (slika 7). Gre za sorazmerno cenen kompenzirani senzor narejen iz podobnih materialov kot velikoserijski senzor krvnega tlaka. Senzorski element tega senzorja je na sliki 2. Med kompenziranimi pretvorniki tlaka za uporabo v procesni industriji smo s pomočjo računalniškega modeliranja vezja razvili za nemškega partnerja družino pretvornikov tlaka v tlačnem področju 20mbar - 5bar (20mbar, SOmbar, 10Ombar, 350mbar, 1 bar, 2bar, 5bar - vsi relativni in 1 bar absolutni). Vsi pretvorniki so v redni proizvodnji (slika 8). Skupna za vse pretvornike je enaka napajalna napetost (najmanj 4.8V) in enak električni odziv (0.5 - 4.5V) glede na izbrano tlačno področje in majhno ter ro- Novi proizvodi in novi proizvodni postopki Pretvornik tlaka 0-150mbar je podoben prej omenjenemu kompenziranemu pretvorniku tlaka, le da je narejen s cenejšimi materiali (slika 9). V njem je uporabljen senzor, ki ga uporabljamo za velikose-rijsko proizvodnjo krvnega tlaka. Namenjen je uporabi v izdelku za trg široke potrošnje. «I* mjr ^¡p 1 r 8_ H^™1.;1 0 1 2 3 4 5 Slika 9: Pretvornik tlaka 0-1 SOmbar V okviru projekta smo imeli nalogo razviti tudi senzor sile za tehtnico z merilnim obsegom od 10 g do 3 kg in točnostjo +-2% polnega obsega. Glede na zahteve smo razvili in izdelali prototipe senzorja sile ter jih testirali in izmerili njihove lastnosti. HCXM020D6V 134 Medicinski senzor tlaka - nova verzija glede na obstoječega v redni proizvodnji. Za ta senzor so bila v sodelovanju z domačim partnerjem razvita vsa orodja za ohišje, izboljšani pa so bili postopki zapiranja mehansko občutljivega senzorskega dela. ![[!jllll|!!ll|l|[||lllljil 2 3 4 Slika 8: Družina pretvornikov tlaka v tlačnem področju 20mbar - 5bar (20mbar, 50mbar, 100mbar, 350mbar, 1bar, 2bar, 5bar- vsi relativni in 1bar absolutni) Možganski senzor tlaka - z miniaturnim silicijevim senzorjem v kovinskem ohišju. Namen pri tem senzorju je bil ohraniti čim več dobrih lastnosti senzorja krvnega tlaka ob hkratni maksimalni miniaturizaciji vezja. V toku izvajanja projekta je prišlo do razvoja več tehnološko različnih postopkov, ki predstavljajo Tehnološke inovacije tehnologija izdelave relativnih kompenziranih senzorjev tlaka v področju pritiskov 100 - 5000 mbar, 0 180 S. Soba, D. Belavič. M. Hrovat, B. Pavlin, A. Simončič: Senzorji tlaka realizirani s pomočjo debeloplastne ... Informacije MIDEM 24(1994)3, str. 178-181 -70°C v debeloplastni tehnologiji z uporabo piezou-pornostnega silicijevega senzorja tlaka; tehnologija izdelave pretvornikov tlaka v področju pritiskov 20 - 5000 mbar, 0 -70°C, v debeloplastni tehnologiji, z različnimi aktivnimi izhodi (0-5V, 0-12V, 4-20mA, itd.); tehnologija zapiranja mehansko občutljivih debelo-plastnih vezij v plastično ohišje; tehnologija izdelave medicinsko atestiranega ko-nektorja in kalibracijske tipke na medicinskem senzorju tlaka za enkratno uporabo; patentiran postopek laserskega doravnavanja de-beloplastnih NTC termistorjev do ozkih toleranc; tehnologija izdelave senzorja sile na osnovi piezou-pornostnega efekta debeloplastnih uporov z dopustno deformacijo 1000 um/m. Možne so aplikacije elementa senzorja sile za merilno področje od 10g -500kg (odvisno od nosilnega elementa) oz. za meritev pritiska od 1 bar navzgor, odvisno od dimenzij membrane. ZAKLJUČEK Zastavljeni cilj projekta - povečanje tržnega deleža na področju senzorjev tlaka - je dosežen. Na področju medicinskih senzorjev smo najmanj ohranili tržni delež navkljub povečani konkurenci. Uspešno pa smo vstopili v trg industrijskih senzorjev, za večji prodor na ta trg pa moramo vzpostaviti redno velikoserijsko proizvodnjo industrijskih senzorjev, kar planiramo za leto 1995. Naročila za te senzorje že imamo. Rezultati projekta so plod skupnega dela raziskovalnega dela raziskovalcev Instituta Jožef Štefan, Iskra RRI IEZE RO HYB in ISKRA HIPOT Tovarna hibridnih vezij,d.o.o. Del rezultatov je že prenešen v proizvodnjo, del rezultatov je pripravljen za prenos v proizvodnjo. Prenos rezultatov v proizvodnjo je delo raziskovalcev Iskre Hi-pot. BIBLIOGRAFIJA Objave: Marko Hrovat, Darko Belavič, Aleš Markošek, Slavko Bernik, "Lastnosti" kombinacij NTC in debeloplastnih uporovnih past, IJS delovno poročilo, DP-6284, 1991 Marko Hrovat, Darko Belavič, Stojan Šoba, Aleš Markošek, Thick film resistor materials for strain gauges, Proc. 20th Int. Conf. on Microelectronics / 28th Symp. on Devices and Materials MIEL-SD 92, Portorož, 1992, 343-348 Marko Hrovat, Darko Belavič, Aleš Markošek, Characteristics of thick film NTC/resistors combinations, Proc. 20th Int. Conf. on Microelectronics / 28th Symp. on Devices and Materials MIEL-SD 92, Portorož, 1992, 355-358 Marko Hrovat, Darko Belavič, Aleš Markošek, Overlapping of thick film NTC thermistors and resistors: a way to optimise laser trimming of narrow tolerance NTC thermistors, Hybrid Circuits, (32), (1993), 16-20 Marko Hrovat, Darko Belavič, Stojan Šoba, Thick film resistors for strain gauges fired on multilayer dielectrics, Proc. 21st Int. Conf. Microelectronics MIEL-93 / 29th Symp. on Devices and Materials SD-93, Bled, 1993, 91-95 Marko Hrovat, Darko Belavič, Silvo Mojstrovič, A new approach to laser trimming of thick film NTC thermistors, Proc. 21 st Int. Conf. Microelectronics MIEL-93 / 29th Symp, on Devices and Materials SD-93, Bled, 1993, 97-101 Patent: Marko Hrovat, Darko Belavič, Aleš Markošek, Postopek laserskega doravnavanja debeloplastnih NTC termistorjev do ozkih toleranc pod 1%, Št. patenta P - 8300417 Stojan Šoba, dipl. ing. Darko Belavič, dipl. ing. Božidar Pavlin, ing. Alojz Simončič Iskra Hipot d. o. o. 68310 Šentjernej Tel.: +68 42020, Fax +68 42 370 dr. Marko Hrovat, dipl. ing. Institut Jožef Stefan 61000 Ljubljana, Jamova 39 Tel.: +61 1259 199, Fax.: +61 219 385 Prispelo (Arrived): 01.09.94 Sprejeto (Accepted): 20.09.94 181 Informacije MIDEM 24(1994)3, Ljubljana___UDK621.3:(53+54+621+66), ISSN0352-9045 TESTNE KARTICE - POMEMBEN DEJAVNIK PRI TESTIRANJU DANAŠNJIH KOMPLEKSNIH MIKROELEKTRONSKIH VEZIJ Z. Bele MIKROIKS d.o.o., Ljubljana, Slovenija Ključne besede: mikroelektronika, vezja mikroelektronska, IC vezja integrirana, preskušanje vezij, kartice preskusne, BLADE kartice preskusne, EPOXY kartice testne, sonde preskusne, konice sond, impedance karakteristične, prilagajanje impedanc, rezine polprevodniške, preskušanje rezin, vernost signalov Povzetek: Članek podaja problematiko testnih kartic pri testiranju kompleksnih mikroelektronskih vezij in osnovne značilnosti obeh izdelavnih tehnologij. Probe Cards - an Essential Factor in Testing of Today's Complex Integrated Circuits Key words: microeletronics, microelectronic circuits, integrated circuits, IC, circuit testing, testing cards, BLADE testing cards, EPOXY testing cards, testing probes, probe needles, characteristic impedances, impedance matching, semiconductor wafers, wafer testing, signal fidelity Abstract: In the paper, main technical characteristics,advantages and disadvantages of two main probe card types are presented. BLADE probe cards are more robust while EPOXY probe cards are less susceptible to different noise, their characteristic impedance can be easier matched, as well as they can be built with more pins. Company MIKROIKS d.o.o. is a manufacturer of BLADE and EPOXY type probe cards. At the same time these probe cards are used in its test center for R&D and production testing of LSI and VLSI integrated circuits on silicon wafers. UVOD Testne kartice postajajo, čeprav velikokrat neupravičeno zapostavljene, bolj in bolj ključnega pomena pri testiranju današnjih kompleksnih mikroelektronskih vezij, ko se ie-ta nahajajo še na rezini. S hitrim naraščanjem stopnje integracije in hitrosti delovanja teh vezij, postaja obvladovanje izdelave in ustreznega vzdrževanja testnih kartic imperativ, če želimo zagotoviti zares kvalitetno testiranje mikroelektronskih vezij na rezini. Tega se zavedamo tudi v podjetju Mikroiks, ki v svojem Testnem centru v Stegnah obvladuje tako tehnologijo izdelave obeh tipov testnih kartic (BLADE, EPOXY), kot njihovo vzdrževanje in uporabo tako za lastne potrebe kot tudi za zunanje naročnike. OSNOVNI PARAMETRI TESTNIH KARTIC Osnovni parametri testnih kartic so: - tip testne katice - vernost signala - šum na napajalnih sponkah - vrsta materiala konic - pritisk konic na kontaktne blazinice in sila na konico - kontaktna upornost Tip testne kartice V splošnem ločimo dva tipa testnih kartic: BLADE in EPOXY. Testne kartice obeh tipov, ki jih izdelujemo v Testnem centru Mikroiks in njihovi sestavni deli so prikazani na sliki 1. Pri testnih karticah tipa BLADE gre za posebno oblikovane konice, ki se posamično prispajkajo na nosilno tiskano ploščico, seveda tako, da s predpisano silo sedejo točno na kontaktne blazinice mikroelektronskega vezja, ki ga testiramo. Pri karticah tipa EPOXY pa najprej konice, ki imajo obliko navadnih iglic na koncih ustrezno ukrivimo in nato pritrdimo na poseben obroček z epoxy lepilom. Tudi pri teh morajo seveda biti konice zelo natančno pozicionirane na kontaktne blazinice tes-tiranega vezja. V zadnjem času vedno bolj prevladujejo testne kartice tipa EPOXY zaradi nekaterih bistvenih prednosti, ki jih imajo v primerjavi s karticami tipa BLADE, kot so: - bistveno manjša susceptibilnost za motnje. BLADE konice namreč delujejo kot majhne antene, ki sprejemajo RF šum tako od svetilnih teles kot raznih instrumentov in podobno. Še pomembneje pa je, da so kapacitivnosti med prevodnimi linijami na tiskani ploščici za BLADE testne kartice tudi do 1.5-krat 182 Z. Bele: Testne kartice - pomemben dejavnik pri testiranju kompleksnih mikroelektronskih vezij Informacije MIDEM 24(1994)3, str. 182-186 Slika 1: Testne kartice tipa BLADE in EPOXY večje kot pri EPOXY kartici irt to še merjeno brez pritrjenih konic. — možnost prilagoditve impedanc. Zaradi neuniformne širine prevodnih linij pri BLADE karticah je prilagoditev impedanc pri teh karticah praktično nemogoča. — EPOXY testne kartice potrebujejo bistveno manj opreme za popravilo in vzdrževanje (za BLADE testne kartice potrebujemo npr. posebno postajo). — bistveno večja gostota konic. BLADE kartice so omejene na maksimalno 60 konic, pretežno zaradi prostorskih omejitev pa tudi upogibanja same tiskane ploščice. — z EPOXY testnimi karticami je moč testirati vezja s precej bolj kompleksnimi vzorci kontaktnih blazinic. — večja stabilnost samih konic. Kljub temu pa imajo predvsem zaradi fleksibilnosti izdelave in lažjega vzdrževanja v posameznih primerih prednost testne kartice tipa BLADE. Vernost signala Testna kartica ima zelo pomemben vpliv na vernost signala med testnim sistemom in testiranim mikroele-ktronskim vezjem. Prvi moment je vsekakor impe-dančna usklajenost oz. neusklajenost med testno kartico in testnim sistemom, kar lahko povzroči refleksijo signala. Refleksija signala na adresnih in/ali urinih sponkah pa lahko povzroči, da testni sistem merjeno vezje izloči kot slabo. Amplituda reflektiranega signala je odvisna od velikosti neusklajenosti karakteristične imped-ance med testnim sistemom in testno kartico ter frekvence oz. frekvenčne vsebine signala. Glede na to, da gre razvoj mikroelektronskih vezij v smeri vedno hitrejših vezij, postajata problem akutnejši, rešitev pa je v čim večji usklajenosti karakterističnih impedanc testnega sistema in testne kartice. Karakteristična imped-anca Z0 prevodne linije na testni kartici je odvisna od dimenzij te linije (višina, širina), oddaljenosti linije od ozemljitvene površine in dielektrične konstante osnovnega materiala (glej sliko 2 I). Odvisnost karakteristične impedance in kapacitivnosti med prevodno linijo in ozemljitveno površino od širine prevodne linije prikazujeta sliki 3 in 4. Iz omenjenih 183 Informacije MIDEM 24(1994)3, str. 182-186 Z. Bele: Testne kartice - pomemben dejavnik pri testiranju kompleksnih mikroelektronskih vezij j ».j w CONDUCTOR MK * H t PVVB DIELECTRIC S GROUND PLANE mmmimimm Zo 87 V4 In 5.98 H 0.8W + T [er+ 1.41] kjer so: Zo ... Karakteristična impedanca v ohmih £r ... dielektrična konstanta osn. materiala (PWB) W,H,T ... dimenzije prevodne linije Slika 2: Karakteristična impedanca prevodne linije na tiskani ploščici 20 30 ' • 40 T-1-1- . -50 . . 60 LJNEWIDTH (mils) " 70 80 90 i T i 100" . 110 UNEWIDTH (mm) 0 10 20 30 40 $0 70 80 .' SO 100 110 UNEWI0TH (mil*) Slika 4: Kapacltivnost med prevodno linijo in ozemljitveno površino kot funkcija širine prevodne linije, = 4.7, T = 38.1 \xm „ CONDUCTORS -DIELECTRIC CONDUCTOR X -DIELECTRIC CONDUCTOR Slika 3: Karakteristična impedanca kot funkcija širine linije, tr = 4.7, T = 38.1 p m krivulj lahko enostavno določimo potrebne parametre za določeno karakteristično impedanco. Drugi degradacijski faktor za vernost signala je vsekakor presluh med dvema prevodnima linijama, bodisi sosednjima ali prekrivajočima, zaradi kapacitivne povezave, kot je to prikazano na sliki 5. Presluh med prekrivajočima linijama lahko učinkovito znižamo ali celo odpravimo z vmesno ozemljitveno Slika 5: Kapacitivna povezava med sosednjima Unijama (zgoraj) in prekrivajočima se linijama (spodaj) površino, katera tudi precej poenostavi impedančno prilagoditev in zmanjša prehodne efekte na ozemljitveni sponki (slika 6 zgoraj). Stranski presluh med sosednjima linijama pa lahko zmanjšamo, če povečamo (čim bolj je možno) razdaljo med obema linijama, ali še bolje, če med vsako signalno linijo vstavimo še ozemljitveno linijo (slika 6 spodaj). 184 Z. Bele: Testne kartice - pomemben dejavnik pri testiranju kompleksnih mikroelektronskih vezij Informacije MIDEM 24(1994)3, str. 182-186 Slika 6: Odprava presiuha med linijama Seveda sta obe rešitvi prostorsko omejeni. Najboljši učinek pa seveda dosežemo s kombinacijo prve in tretje rešitve. ima nekaj pomembnih prednosti nasproti Cu-Be in pa-ladiju. Predvsem je izredno odporen proti oksidiranju in zelo trden, kar pomeni daljšo življensko dobo konic. Njegova največja pomankljivost pa je v relativno visoki kontaktni upornosti. Volframova konica zaradi svoje strukture med testiranjem "pobira" silicijev oksid s kontaktnih blazinic tako, da lahko kontaktna upornost preseže 5 ohmov, kar lahko občutno vpliva na kvaliteto testiranja in seveda izplen rezine. Nasprotno ima Cu-Be izredno nizko osnovno kontaktno upornost, ki pa se praktično ohranja med testiranjem, saj se silicijev oksid nanj ne prijemlje. Je pa bistveno mehkejši kot volfram, kar pomeni, da potrebujejo testne kartice s konicami iz tega materiala več vzdrževalnih posegov pa tudi njihova življenska doba je precej krajša. Po drugi strani pa je to moč kompenzirati z večjim in ponovljivejšim izplenom na račun nižje kontaktne upornosti. Pritisk na kontaktne blazinice in sila na konico Pritisk na kontaktne blazinice ima vsekakor velik vpliv na izplen pri testiranju. Od njega je odvisno, kako dober kontakt ustvarimo med konico in kontaktno blazinico, pri tem pa ne sme priti do morebitnega preboja zelo tanke aluminijeve plasti, ki tvori kontaktno blazinico. Velikost pritiska določata tako dodatni pomik mizice navzgor (overtravel) od točke, ko konice dotaknejo rezino, kakor tudi površina oz. premer same konice. Sila na samo konico pa je odvisna od vrste materiala iz katerega je konica, dolžine vrha konice in dodatnega pomika. Šum na napajalni in ozemljitveni sponki V splošnem je ta problem najteže rešljiv, vsekakor pa je eden najpomembnejših. Šum je večji, čim večja je hitrost vezja. Pri današnjih vezjih pa gre trend ravno v tej smeri. Primer vezij, pri katerih je ta problem še poudarjen so npr. dinamična spominska vezja, pri katerih je generacija šuma pogojena predvem z nabijanjen in praznenjem notranjih kapacitivnosti. Pri teh vezij lahko opazimo tudi zelo hitre tokovne konice reda nekaj 100 mA na napajalni in ozemljitveni sponki, kar vsekakor pomeni precejšnja nihanja napajalnih napetosti v vezju. Poleg primernega načrtovanja izdelave testne kartice pa je relativno enostaven način odprave šuma na napajalnih sponkah uporaba "bypass" kondenzatorja. Vrednost takega kondenzatorja je izkustveno v območju med 0.001 in 0.1 |iF, njegovo točno vrednost pa je najbolje določiti na podlagi opazovanja signala in efekta "bypass" kondenzatorja na širokopasovnem osciloskopu. Vrsta materiala za konice Konice za testne kartice so v splošnem iz treh vrst materiala: volframa, zlitine baker-berilij (Cu-Be) ali pa-ladija. Daleč največ uporabljan material je volfram, ki Kontaktna upornost Kot že rečeno, kontaktna upornost je predvsem odvisna od vrste materiala iz katerega je konica in dodatnega pomika (overtravel). Pri tem je seveda dodatni pomik omejen, saj če je prevelik poškoduje površino kontaktne blazinice, zaradi upogibanja pa lahko konica celo zleze izven kontaktne blazinice. Obstajajo posebni izračuni, s pomočjo katerih je moč kar se da točno določiti potrebni dodatni pomik, ki je običajno med 50(im in 100|im. Slika 7: Odvisnost kontaktne upornosti od dodatnega vertikalnega pomika mizice 185 Informacije MIDEM 24(1994)3, str. 182-186 Z. Bele: Testne kartice - pomemben dejavnik pri testiranju kompleksnih mikroelektronskih vezij Odvisnost kontaktne upornosti od dodatnega pomika za tipično konico premera 50|o.m in dolžine 500|j.m podaja slika 7. Osnovne značilnosti tehnologij izdelave testnih kartic v Testnem centru Mikroiks Osnovne značilnosti obeh tehnologij, ki jih uporabljamo pri izdelavi testnih kartic v Testnem centru Mikroiks so: a) Tehnologija EPOXY: — material konic: volfram (99. 99%) — razdalja med konicama: 0. 005" (127|im) — velikost kontaktne blazinice: 0. 0025"-0. 0030" (63.5 - 76.2 um) — sila na konico: 2-4 g/mils (2-4 g/ 25.4 um) — planarizacija: +- 0. 0007" (17.8 um) — premer konice: 0. 0015"-0. 0025" (38.1 - 63.5 jxm) — oblika vrha konice: raven — dolžina konice: 0. 007"+-0. 001" od krivine (177.8 ± 25.4 n_m) — tiskane ploščice: C48-1 (dolžina 4.5" (114.3 mm), 48 konic, pravokotna) C70-1 (dim. 4. 5"X7. 35" (114.3x 186.7 mm), 70 konic, pravokotna) C70-2 (premer 2" (50.8 mm), 70 konic, okrogla) b) Tehnologija BLADE: — material konic: volfram (99. 99%) — razdalja med konicama: 0. 005" (127 um) - velikost kontaktne blazinice: 0. 0025"-0. 0030" (63.5 - 76.2 um) - sila na konico: 2-4 g /mils (2-4g/ 25.4 |jm) - planarizacija: +- 0. 0007" (17.8 um) - premer konice: 0. 0015"-0. 0025" (38.1 - 63.5 jim) - oblika vrha konice: raven - dolžina konice: 0. 007"+-0. 001" od krivine (177.8 ± 25.4 um) - tiskane ploščice: C48-1 (dolžina 4.5", (114,3 mm), 48 konic, pravokotna) ZAKLJUČEK Testne kartice postajajo vedno pomebnejši dejavnik pri testiranju kompleksnih mikroelektronskih vezij, saj lahko pomembno vplivajo na kvaliteto testiranja s tem pa prek izplena na celotno stroškovnost izdelave vezja. Zato so proizvajalci mikroelektronskih vezij praktičo prisiljeni temu segmentu posvečati vedno več pozornosti, tako v smislu vlaganj v vedno bolj sofisticirano opremo za izdelavo in vzdrževanje testnih kartic in tudi kadre, ali pa se posluževati profesionalnih uslug specializiranih firm za to področje. Zlat ko Bele, dipl. ing. Mikroiks d. o. o. Dunajska 5 61000 Ljubljana tel. +386 61 312 898 fax+ 386 61 319 170 Prispelo (Arrived): 01.09.94 Sprejeto (Accepted): 20.09.94 186 UDK 621.3:(53+54+621+66), ISSN0352-9045 informacije MIDEM 24(1994)3, Ljubljana KARAKTERIZACIJA V VAKUUMU NAPARJENIH TANKIH PLASTI Al NA Si REZINE B. Praček Inštitut za elektroniko in vakuumsko tehniko, Ljubljana, Slovenija Ključne besede: mikroelektronika, tehnologija polprevodniška, plasti tanke, rezine silicijeve, naparevanje vakuumsko, nanašanje aluminija, oksidacija termična, AES Auger spektroskopija elektronska, C-V metoda kapacitivno napetostna, interferometrija Povzetek: Nanašanje tankih plasti aluminija na silicijeve rezine je pomemben del polprevodniške tehnologije. V članku so podani rezultati karakterizacije tankih plasti aluminija s spektroskopijo Augerjevih elektronov v kombinaciji s C-V metodo in interferometrijo. Prikazani rezultati so dobljeni s preiskavo šestih karakterističnih vzorcev. Tanka plast aluminija je bila nanešena na tri vzorce z elektronskim curkom, na preostale tri pa z indirektnim uporovnim ogrevanjem na volframski spirali. Na enem vzorcu iz obeh skupin je bila pred nanosom plasti aluminija, na silicijevih rezinah s termično oksidacijo izdelana samo tanka plast silicijevega dioksida. Na drugih dveh je pred nanašanjem Al plasti z difuzijo bora izdelan np spoj ter na preostalih dveh z difuzijo fosforja pn spoj. Debelina, kemična sestava in elektronske lastnosti tako naparjenih plasti aluminija se najbolj razlikujejo pri tistih plasteh, ki so nanesene na silicijev dioksid, zaradi redukcije tega z aluminijem. Prav tako smo ugotovili, da so Al plasti nanešene z elektronsim curkom veliko boljše v pogledu gibljivih in negibljivih nabitih delcev, katere vnašajo v silicijev dioksid. itic Characterization of Thin Al Films Deposited on Si Substrates Key words: microelectronics, semiconductor technology, thin films, silicon wafers, vacuum evaporation, aluminium deposition, thermally grown silicon oxide, AES, Auger electron spectroscopy, capacitance-voltage method, interferometry Abstract: For a long time vacuum evaporation of thin aluminium films has been a constitutive part of semiconductor technology. This article presents some results on characterization of these films by Auger electron spectroscopy, capacitance-voltage and interferometric methods. The results presented have been obtained by examining six characteristic samples. On three of them aluminium has been evaporated by electron beam technique; other tree were coated with aluminium by evaporation from tungsten spiral. In each group of samples one of samples has been previously covered with thermally grown silicon oxide; the second two samples have been doped by boron and the third two by phosphorus. The thickness, chemical composition and electronic properties of these films are different; films deposited on the silicon dioxide show the most prominent differences because of the reduction of silicon dioxide by aluminium. Also, it has been confirmed that electron beam evaporated samples show better characteristics concerning the contents of fixed and mobile charges in the underlining silicon dioxide. 1. UVOD Vakuumsko naparjene plasti aluminija so že dolgo nepogrešljiv sestavni del polprevodniške tehnologije. Dobro nanašanje in legiranje, dobra električna prevodnost, možnost fotolltografskega postopka in nizka cena so zelo zaželjene lastnosti v proizvodnji polprevodnikov. Aluminij se uporablja tako za vmesne plasti kot tudi za kontaktiranje. Uporabne lastnosti nanesenih plasti aluminija bodo odvisne od njihove končne kemične sestave in strukture. V članku podajamo rezultate karakterizacije tankih plasti aluminija, ki so nanesene v vakuumu z dvema različnima metodama: naparevanjem iz volfram-ske spirale in nanašanjem s pomočjo elektronskega curka. upornostjo 3-5 ohm cm. Plast aluminija je na vzorec št.1 naparjena iz volframske spirale na vzorec št.4 pa je nanesena z elektronskim curkom. Vzorca št.2 in št.5 sta izdelana na silicijevih rezinah p-tipa z upornostjo, ki je znašala 3-5 ohm cm, ki sta bili termično oksidirani do debeline silicijevega dioksida okoli 1 |a.m. Z fotolitograf-skim postopkom sta bili najprej pri obeh v oksidni plasti izdelani odprtini, sledil je postopek doplranja s fosforjem in nato nanašanje aluminija. Plast aluminija je na vzorec št.2 naparjena iz volframske spirale na vzorcec št.5 pa nanešena z elektronskim curkom. Podlaga za vzorca št.3 in št.6 sta bili silicijevi rezini n-tipa s površino pripravljeno na enak način kot za vzorca št.2 in št.5, le da je po izdelavi odprtin v plasti silicijevega dioksida sledilo dopiranje z borom pred nanašanjem aluminija. Na vzo- 2. EKSPERIMENTALNO DELO 2.1. Izdelava vzorcev Vsi vzorci so izdelani na podlagah Iz silicijevih rezin z orientacijo <111> in premera 2". Silicijevi podlagi sta bili za vzorca št. 1 in št.4 termično oksidirani do debeline silicijevega dioksida okoli 0.4 um in sta bila n tip z * Prispevek je bil objavljen že v prejšnji številki Informacij MIDEM, 2(94), vendar ga ponovno objavljamo in se opravičujemo avtorju zaradi napak, ki so se prikradle med tiskom prejšnje številke. ** This article has already been published in the last issue of Informacije MIDEM, 2(94). Due to some unfortunate mistakes which appeared in the text during printing, we are publishing it again with our apologies to the author. 187 Informacije Ml DEM 24(1994)3, sir. 187-192 B. Praček: Karakterizacija v vakuumu naparjenih tankih _plasti Al na Si rezine vz.st. © © © Na pare v a nje \X/ - spirala. n sstf jC/U i U^ijjr- vz.si © © Napore vonje elektron, top '¿s. 'JL LEGENDA'G23AI-CTSiOj CUSi - smer AES anal/ZC_ Slika 1: Shematski prikaz prereza vzorcev rec št.3 je plast aluminija naparjena iz volframske spirale, na vzorec št.6 pa je Al plast nanešena z elektronskim curkom. Shematski prikaz preseka na opisani način izdelanih vzorcev z označeno smerjo AES profilne analize kaže slika 1. čas ionskega jedkanjav minutah. V legendi diagramov je za vse detektirane elemente označeno pri kateri energiji se v spektru Augerjevih elektronov nahaja njihov vrh. 2. 2. Profilometrične meritve in optična karakterizacija Meritve s profilometrom so pokazale, da je na vseh šestih vzorcih debelina nanešenih plasti aluminija dokaj enaka in da znaša okoli 0.4 um. Prav tako so meritve pokazale, da sta debelini termično izdelanega silicijevega dioksida na podlagah vzorcev št. 1 in št.4 pred nanašanjem aluminija, znašali okoli 0.38 um. Preiskave z optičnim mikroskopom pri 500 kratni povečavi niso pokazale bistvenih razlik v izgledu in strukturi plasti. 2. 3. AES karakterizacija Vzorce smo pritrdili na nosilec vzorcev z nagibom 60 kotnih stopinj in jih ugradili v spektrometer Augerjevih elektronov (Phisical Electronics Ind. SAM 545 A). Za analizo smo uporabili statični curek primarnih elektronov energije 3 keV in tok elektronov 0.5 ¡aA. Vzorci so jedkani z dvema sovpadajočima curkoma ionov argona z energijo 1 keV, ki sta rastrirala na površini 5mm x 5mm pri vpadnem kotu 47 kotnih stopinj. Hitrost jedkanja Cr/Ni standarda je bila okoli 3 nm/min. Podatki dobljeni iz spektrov Augerjevih elektronov, posneti med profilno analizo, so uporabljeni za izdelavo profilnih diagramov prikazanih na slikah 2 in 3. Na ordinati diagramov je nanesena koncentracija v relativnih enotah in na abscisi 3. REZULTATI IN DISKUSIJA 3.1 Rezultati AES profilne analize Profilni diagram vzorca št. 1 (slika 2a), prikazuje koncentracijski profil 0.4 ^.m debele plasti aluminija, ki je bila naparjena iz volframske spirale na 0.38 jim debelo plast silicijevega dioksida. Na površini Al plasti se nahaja tanka oksidna plast debela okoli 9 nm (okoli 3 min jedkanja). Augerjev vrh pri energiji 54 eV, ki pripada aluminiju vezanemu v AI2O3 ne zaznamo več že po štirih minutah jedkanja. Na površini in deloma tudi v tanki oksidni plasti najdemo kot kontaminacijo manjšo koncentracijo ogljika. Vse do 130-te minute jedkanja se nahaja plast čistega aluminija (Augerjev vrh pri energiji 68 eV), ko se že pojavijo vrhovi: Si(78eV), ki pripada siliciju vezanemu v SiC>2, vrh Si(92eV) pripada elementarnemu siliciju in vrh kisika 0(51 OeV). Fazno mejo med Al in Si02 dosežemo po 150-tih minutah jedkanja (debelina okoli 0.45 (um). V profilnem diagramu vzorca št.2 (slika 2b), je prikazan koncentracijski profil 0.4 (j.m debele plasti aluminija, ki je bila naparjena iz volframske spirale na silicijevo rezino dopirano z fosforjem. Nastala oksidna plast na površini tega vzorca je približno enake debeline (okoli 9nm) kot na vzorcu št. 1, le da je meja med Al oksidom in kovino manj izrazita. Krivulja vrha AI(54eV), ki pripada oksidir- 188 B. Praček: Karakterizacija v vakuumu naparjenih tankih plasti Al na Si rezine _ Informacije Ml DEM 24(1994)3, str. 187-192 100 Vz.1 -X- AI(61oV) AKOBoV) 0 (610oV) — C (2 72eV) -0- 8l(78oV) -A- 8l(82eV) 140 100 100 170 180 JT 03 o C o; -E c > < rt aj > O rt c CU O C o k: 100 Vz.2 AliS-loV) -ra- Ai(OBoV) 0 (S10oV) --- 0 (272oV) -O- 8l(70oV) -A- 3i(gjoV) 110 150 100 170 180 100 V z.3 -X- AI(64oV) AI(68eV) 0 (510oV) -— C (272oV) -0- 8l(70oV) -A- 01(0 2oV) : !- ' 10 130 160 170 180 Cas ionskega jedkanja [rain] Slika 2: ProfUnidiagram vz. 1(a), vz.2(b) in vz.3(c) 189 Informacije MIDEM 24(1994)3, str. 187-192 B. Praček: Karakterizacija v vakuumu naparjenih tankih 1 ___plasti Al na Si rezine 100 o i-n— Vz.4 A1(61oV) -t-> AI(OBoV) 0 (B10BV1 — C (272SV) -0- 8 K 7 0 oV) SK920V) 190 200 210 xz rt -t-» o C Q> C '+Z rt 0> > rt o rt i— C. d) o c o ^ 100 80 - 60 40 20 - D HJ- t-*: o i j-tr'^-H Vz.5 -X- AI(55500 A/cm2 Najvišji energetski impulz 0.3 J do 200 J 2.2 J do 280 J > 400 J/cm3 Zaščita Epoksi Epoksi Epoksi Pakiranje Razsuti ali trakanl Razsuti ali trakani Razsuti ali trakani Atesti C-UL.VDE v testiranju MLV ZV Serija - Nizkonapetostni AV Serija - Avtomobilski Napetost praga 4 V do 33 V 18 V, 22 V, 27 V, 33V Najvišji tokovni impulz 25 A do 1000 A 250 A do 4000 A Najvišji energetski Impulz 0.05 J do 6.0 J 1 J do 45 J Izvedba Radialno ožičeni ali čipl Radialno ožičeni ali čipl Zaščita Epoksi Epoksi Pakiranje Razsuti ali trakani Razsuti ali trakani Močnostni ZO V Serija - Standardni ZOV Serija-po naročilu Napetost praga 200 V do 1000 V 200 V do 1000 V Najvišji tokovni impulz 15000 A do 40000 A > 5500 A/cm2 Najvišji energetski impulz 140 J do 1100 J > 400 J/cm3 Izvedba Metallzirana plošči ca ali zaščiten Metallzirana ploščica ali zaščiten Zašata Epoksi Epoksi Pakiranje Razsuti Razsuti VARICON MV Serija - Nizkonapetostni OV Serija - Avtomobilski Napetost praga 4 V do 33 V 18 V, 22 V, 27 V, 33 V Najvišji tokovni impulz 50 A do 250 A 1000 A Najvišji energetski impulz 0.05 J do 1.3 J 3.2 J do 6.0 J Kapacitivni obseg 10 do 100 nF 0.47 do 1.5 ¡iF Zaščita Epoksi Epoksi Pakiranje Razsuti ali trakani Razsuti ali trakani J POZISTORJI Grelci Visokonapetostni Nizkonapetostni Naziva temperatura 70°C do 220°C 40°C do 80 °C Nazivna upornost 200 n do 1700 a 4 a do 25 fl Največja dovoljena napetost 160 V, 240 V, 260 V 30 V,50 V Izvedba Metalizirane tablete Metalizirane tablete Pakiranje Razsuti Razsuti Pretokovna zaščita High volta ge Naziva temperatura 60°C Nazivna upornost 1200 n to 3500 n Največja dovoljena napetost 360 V Izvedba Radialno ožičeni Epoksi ali brez Pakiranje Razsuti KEKO d.d., Grajski trg 15, 68360 Žužemberk, SLO, tel. (+ 386 68) 86-230, fax (+ 386 68) 87-315 197 Informacije MIDEM 24(1994)3, Ljubljana konference, posvetovanja, seminarji, poročila NATO Advanced Workshop on "Advances in Ceramic MCM and High Performance Electronic materials" 21. - 23. 5.1994, Islamorada, Florida, USA Udeležil sem se konference oz. delavnice (workshop) o (predvsem) keramičnih multichip modulih (MCM) in materialih za elektroniko, ki sta jo sponzorirala NATO in ISHM (International Society for Hybrid Microelectronics). Konferenca je trajala tri dni, od 21. do 23. maja v hotelu Cheeca Lodge na otoku Islamorada, kakih 150 km južno od Miamija. Delo je potekalo v naslednjih sekcijah: — Keramični MCM — Uporaba keramičnih MCM — Debeloplastni senzorji — Načrtovanje in modeliranje — MCM - "mešane" tehnologije — "Napredni" (advanced) debeloplastni materiali Udeleženci: Združene države Amerike 31 Francija 4 Nemčija 4 Velika Britanija 3 Madžarska 2 Poljska 2 Švedska 2 Avstrija 1 Belgija 1 -Češka 1 Italija 1 Litva 1 Slovaška 1 Slovenija 1 Španija 1 V poročilu bom na kratko opisal vsebino nekaterih zanimivejših predavanj, na razpolago pa je zbornik razširjenih povzetkov. Zbornik referatov bo izšel predvidoma v prvi polovici naslednjega leta. Multi Chip Moduli (MCM) so komponente z zelo visokim številom funkcij, pri katerih se na večplastne substrate z veliko gostoto povezav pritrdi gole silicijeve tabletke. Multichip moduli imajo precej prednosti pred konvencio-nalno inkapsuliranimi silicijevimi tabletkami z velikim številom vhodov/izhodov (single chip modules), predv- sem v primerih, ko primanjkuje prostora v vezju in, če je takt ure "hiter". Nekateri predavatelji so povedali, da bodo za zahtevne aplikacije postali MCM nujno potrebni, ker zaradi naraščajočega števila transistorjev na silicijevih tabletkah in hitrosti "delovanja" konvencionalne tehnologije ne bodo več ustrezale zaradi predolgih povezav. Ena od prednosti MCM pred ASIC (Application Specific Integrated Circuits) je v hitrejšem designu MCM. Pri ASIC traja načrtovanje tudi do dve leti, v MCM pa se povežejo obstoječe tabletke. ASIC je v velikih količinah lahko precej cenejši in bolj funkcionalen, vendar je za izdelke pomembnejši kratek čas razvoja. Gostota komponent je lahko podobna na MCM in pri ASIC, pri tem pa se lahko v MCM kombinirajo tudi različne polprevod-ne tehnologije, na primer silicij in GaAs. Na konferenci so obravnavali predvsem keramične MCM. Za začetek bom na kratko definiral "osnovne tipe" Multi Chip Modulov, izdelanih v različnih tehnologijah: MCM-L so zahtevna večplastna tiskana vezja z linijami minimalne širine, to je navzdol do 25 |j.m. * Relativna cena: 1 MCM-D so moduli, ki imajo nanešene tankoplastne večplastne kovinske povezave (večinoma aluminij ali baker), ločene s polimernim ali napršenim tankoplastnim (Si02) dielektrikom. Kot substrat se največ uporablja AI2O3 ali silicij. Silicij dobro prevaja toploto, njegov temperaturni razteznostni koeficient pa je seveda isti kot razteznostni koeficient silicijevih tabletk. V tem primeru se del elektronike izdela lahko že na substratu. Ta tip MCM omogoča največje gostote komponent oz. funkcij. * Relativna cena - A^Oa : 3 * Relativna cena - silicij: 8 MCM-C so "keramični" hibridi visoke gostote, navadno večplastni keramični substrati, v katerih je tudi prek 50 nivojev prevodnika, ali pa kompleksna debeloplastna večplastna vezja. Večplastni keramični substrati so narejeni iz zelenih folij, potiskanih s prevodnimi linijami in so lahko na osnovi AI2O3 ali AIN z višjo toplotno prevodnostjo (HT- MCM-C - keramični MCM z visoko temperaturo žganja) ali pa na osnovi kristali-zirajočih stekel (LT- MCM-C - keramični MCM z nizko temperaturo žganja). V sam substrat 198 Informacije MIDEM 24(1994)3, Ljubljana so lahko vgrajeni, v glavnem v primeru keramike s temperaturo žganja pod 1000°C, tudi upori ali kondenzatorji. * Relativna cena: 2 Moja (povsem osebna!) ocena je, da bodo zaradi njihove visoke cene, kljub neizpodbitnim prednostim, MCM uporabljani še precej časa predvsem za vojaške in vesoljske aplikacije. Mimogrede, še anekdota iz uvoda članka o MCM; avtor je napisal, da, če isto vezje, izdelano v večplastni debeloplastni tehnologiji, imenuje večplastno vezje, bo zanj dobil 100$, če pa ga imenuje Multi Chip Modul, pa 1000$. Več avtorjev je predstavilo uporabo MCM za uporabo v satelitih, tako komunikacijskih kot "opazovalnih", ki morajo spraviti velike količine podatkov. Zahteve po spominu v nekaterih primerih presegajo nakaj 100 Gbit, predvsem za geostacionarne satelite. MCM začenjajo tako po karakteristikah (lahki, kompaktni in odporni na sevanje) kot po številu podatkov, ki jih lahko "spravijo", tekmovati z magnetnimi spomini (trakovi ali diski) ali optičnimi diski. Njihova prednost je predvsem v tem, da so brez gibljivih delov. Bodoči trendi so, kot so podali nekateri avtorji, med ostalim tudi tridimenzionalno zlaganje MCM drugega na drugega ali drugega poleg drugega tako, da dobimo tridimenzionalno "škatlico" - MCM cube - z visoko volumsko, ne samo ploskovno gostoto funkcij, ki še vedno zavzame majhen del površine plošče, na kateri se montira. N. Sinnadurai (Middlesex University, Anglija) je v svojem prispevku povedal, da bi morali predvsem za "vesoljske" aplikacije pretestirati in uporabljati organske polimerne zaščitne materiale, zaradi nizkih dielek-tričnosti in predvsem zaradi nižje teže tako enkapsulira-nih MCM, čeprav to nasprotuje sedanji filozofiji o uporabi hermetičnih, to je kovinskih ali keramičnih ohišij. Omenil je zahtevo za te vrste aplikacij, to je nobene odpovedi v 25 letih. A. M. Hirscherg (Coors Electronic Package Comp., ZDA) je zatrdil, da so keramični MCM trenutno najbolj razviti. Ta razvoj je bil financiran večinoma od komercialnih firm, medtem ko je vlada vlagala denar v glavnem v razvoj MCM-D in MCM-L. Prednosti MCM-C so predvsem v tem, da se lahko "zgradi" veliko število, tudi prek 100, prevodnih nivojev. Omenil je MCM na osnovi AIN z 93000 povezavami (vias) med nivoji in 800 m (skoraj kilometer!) pokopanih, to je zapečenih v keramičen substrat, prevodnih linij. H. Hentzell (IMC, Švedska) je govoril o MCM na tako imenovanih aktivnih ali pametnih (smart) substratih. Pri teh MCM je substrat silicijeva ploščica, na kateri so poleg povezav izdelani tudi logika in spominski elementi, zato je potrebno pritrditi manj silicijevih tabletk. Na ta način lahko zmanjšajo dimenzije MCM za več kot 50% v primerjavi s pasivnimi substrati, na katerih so samo povezave. Povedal je, da bi se teoretično lahko spravila vsa elektronika na silicijev substrat, vendar bi vezje postalo tako kompleksno, da bi bili izkoristki nesprejemljivo nizki. (Pripombe; pred nekaj leti je vojska oz. letalstvo Združenih držav pripravilo projekt za razvoj takih integriranih vezij, pri čemer bi bile posamezne tabletke velike tudi do 50 mm - wafer scale integration -, vendar ga zaradi problema izkoristka niso izpeljali. Še prej, v drugi polovici osemdesetih let, je imel isto idejo Sinclair, izumitelj in proizvajalec hišnih računalnikov, od katerih je bil verjetno najbolj znan in prodajan Spectrum). W. K. Jones (Florida Int. University, ZDA), D. Lambert (Bull SA, Francija) in E. Bihler (IBM, Nemčija) so govorili 0 "mešanih" MCM, kjer se na večplastnih keramičnih substratih izdela večplastne tenkoplastne strukture na osnovi polimerov kot izolatorjev in bakra oz TiW/Au kot prevodnika (kombinacija MCM-C in MCM-D tehnologije). Pri tem da keramična podloga trdnost in dobro odvajanje toplote, polimerni dielektrik pa omogoča višjo frekvenco signalov zaradi nizke dielektričnosti. Nekaj referatov je poročalo o karakteristikah debeloplastnih uporov ali kondenzatorskih dielektrikov, ki so pokopani in žgani v večplastnih keramičnih strukturah. Zanimiva (in nenavadna) je bila uporaba laserja za "risanje" prevodnih linij na AIN keramiki, o čemer je poročal Z. Illyefalvi-Vitez (Technical University of Budapest, Madžarska). AIN razpada na aluminij in dušik, ko je obsevan z laserjem. Po poti laserskega žarka se pod primerno nastavitvijo parametrov laserja Al izloči na površini keramike in tvori tenkoplastno prevodno sled s plastno upornostjo do 200 mohm/. Širina teh linij je, vsaj teoretično, omejena samo z ostrino fokusa laserskega žarka. (Pripomba: to je isti efekt, ki otežuje lasersko doravnavanje debeloplastnih uporov na AIN substratih. Kovinski Al, ki lahko ostane v rezu, do neke mere kratko sklene prerezan del upora, kar povzroči nestabilnost uporovne vrednosti). G. Harsanyi (Univerza v Budimpešti, Madžarska) je obravnaval probleme zaradi elek-tromigracije v večplastnih MCM. Migracijo kovinskih ionov skozi dielektrik povzroča vlaga, ki lahko ostane na vezjih ali pa je absorbirana v polimerih. Ta problem se bo verjetno še poslabšal, ko bodo namesto CFC topil za čiščnje ostankov organskih fluksov po spajkanju začeli uporabljati topila na osnovi vode za vodotopne flukse. V sekciji o debeloplastnih senzorjih je bil predstavljen tudi naš referat, ki je obravnaval preiskave komercialnih debeloplastnih materialov z namenom, da bi našli materiale z optimalno kombinacijo karakteristik za uporabo v senzorjih temperature (termoelementi, narejeni z de-beloplastnimi prevodniki) in upogiba (debeloplastni upori z visoko odvisnostjo spremembe upornosti od deformacije). R. Dell'Acqua (MiTeCo, Italija) in S. Mergui (Florida University, ZDA) sta prikazala pregled debeloplastnih senzorskih materialov tako na osnovi keramike kot organskih polimerov. Poudarjena je bila predvsem potreba po večji zanesljivosti, ponovljivosti in ceni, pristopni za splošno uporabo. L. J. Golonka (Technical University of Wroclaw, Poljska) je poročal o debelopla-stnem elektrolitskem sonzorju za detekcijo žveplovega dioksida. Trdni elektrolit je bil K2SQ4, referenčna elektroda pa Ag/Agi'SOV. M. So mora (Technical University of Kosice, Slovaška) je poročal o uporabi debeloplastnih uporovnih materialov na osnovi RUO2 za sekundarne temperaturne senzorje za zelo nizke temperature, pod 1 K. J. Minalgiene (Hibridas Enterprise, Litva) in S. Achmatowicz (Institute of Electronic Materials Techn., 199 Informacije M1DEM 24(1994)3, Ljubljana Poljska) sta predstavila razvoj fotoobčutljivih debelopla-stnih materialov, ki omogočajo s postopki foto litografije izdelavo zelo gostih večplastnih vezij z ločljivostjo prevodnih linij pod 50 iam in lukenj (vias) v dielektriki okrog ali pod 100 ¡im. Pri tem razvoju sodelujejo trije "vzhodni" inštituti iz Litve, Ukrajine in Poljske, poleg tega pa še firma MozaikTechnologyVentures iz Anglije. (Pripomba: take materiale je firma Du Pont ponudila prvič že v sedemdesetih letih pod imenom FODEL, nato pa ponovno pred okrog tremi leti. Ker pri omenjenem razvoju teh materialov sodeluje tudi S. Muckett - firma Mozaik iz Anglije -, ki je "povezana" z Electro Science Labs., znanim proizvajalcem debeloplastnih materialov, sklepam, da bo te materiale po končanem razvoju pričela prodajati ESL). Dr. Marko Hrovat, dipl. ing. Institut Jožef Štefan Jamova 39, 61000 Ljubljana VESTi, news korea's semicon industry will continue strong growth The Seoul based Korea Semiconductor Industry Association (KSIA) predicts the industry will show a healthy 37% growth over 1993, reaching US$7.24 billion this year. Last year, it registered $5.26 billion in sales, a 61% increase over the previous year. "Among the U.S. dealers, Korean DRAMs are recognized as No. 1 in terms of quality and price," said Kim Chi-Luck, KSIA's president. This reputation, he added, should enable Korean chip makers to enjoy a favorable business environment, for some time to come. Also, he said, the Korean makers' strong commitment to mass production could give them an edge over Japanese rivals, especially in the memory business, where the key selling point is low unit price. Kim dismissed the possibility that trade friction with foregin countries could result from a sharp rise in exports, "because Korean memory producers do not sell their products under production cost and do not have a monopoly in over-seas markets". To avoid other possible trade conflicts, Korea's government is preparing details of the Korea Chip Protection Law enacted last year and is studying ways to improve the tariff structure in the sector, Kim said. He also noted that KSIA and its counterparts in the U.S. and European Union have agreed to eliminate tariffs on semiconductor devices and equipment for five years after the Urugay Round Tariff accord. He said the pact should increase the industry's exports. Electronics, March 1994 Tl Europe attacks electronic money chip market with encryption protocol Texas Instruments Europe is challenging market leaders SGS Thomson Microelectronics SA of Paris and Motorola Inc. of Schaumburg, III., in an effort to capture half Europe's sales of electronic money microcontroller chips. The chips are used in financial transaction cards which enable banks and credit card firms to identify the legitimate user through a personal code that is scanned before any payment is authorized. The Villeneuve Loubet - based firm has been working with Paris' Schlumberger SA to develop the non-volatile EPROM memory chip family that is the basis of its pay card technology in which secure data encryption is a key element, said Sghaier Noury, Tl's microcontroller manager for Europe. He said that within 18 months, Tl will have a new, even more sophisticated encryption protocol ready that will provide a higher degree of security for the user. "Data encrypted transaction is going to be the driving force in tomorrow's payments cards," said Noury. "The business person is becoming increasingly nomadic. Just as he wants to use his mobile phono wherever he WORLD SMART CARD MARKET by end-user application in millions of U.S. dollars $1200 '93 '95 '97 '99 M Pay phone ■S Financial Ml Healthcare Frost and Su|Hvan The smart card markers for pay phone, financial and healthcare applications will grow at compound annual growth rates of 22%, 32.5% and 27.6%, respectively, according to Girish Rishi, a senior analyst at Frost and Sullivan Market Intelligence in Mountain View, Calif. 200 Informacije M1DEM 24(1994)3, Ljubljana happens to be, he needs to access confidential data -from an office database or his personal bank account -at any time or place. That's why encryption is so Important." He added, "The pay card market is developing much faster In Europe then elsewhere. (The U.S. market) has regarded a switch to the microprocessor-memory chip on a 'smart card' (from magnetic strip cards) as too costly. But now, losses due to forgery are so huge that the mood is changing." Electronics, March 1994 Semiconductors allow 25-GHz transit frequencies The semiconductor group of Munich-based Siemens AG has introduced a new process technology named B6HF, which allows transit frequencies of more than 25 GHz. Unltl now these extremely high frequencies were a domain of gallium arsenide (GaAs). B6HF offers gate delay times of 25 picoseconds at 1.2 microAmperes and 70 ps at 100 |aA. In this technology, structures of 0.8 - microns can be realized with noise factors of 1.1 dB at 1.8 GHz, making them suitable for fiber-optic transmission systems running at 10 Gbits/s. The effective emitter width is said to be 0.4 micron. "B6HF is the only silicon technology in the world that offers a transit frequency of more than 25 GHz," said Rolf-Juergen Bruess, head of marketing for communications ICs at Siemens. The company plans to develop ECL gate arrays with complexities of 3.000 and 6.000 gates this year. Siemens handles its bipolar B6HF process on its CMOS process lines. Except for the precipitation of the Epi layer, the B6HF process is fully compatible to the 0.8 -micron CMOS process. Electronics, March 1994 Siemens sees high demand for communications ICs Communication ICs for mobile communications, trunk switches, public branch exchanges and integrated services digital networks (ISDN) have become leading sellers in the Munich headquarters of Siemens AG's semiconductor group. While other divisions of the semiconductor group struggle to make a profit, the communications ICs division has been in the black since the last fiscal year (ending in September), said Rolf- Juergen Bruess, senior marketing manager of communication ICs at Siemens. He said that within the last two years, the company's communications ICs sales will have more than doubled to DM400 million (US$235 million) by the end of this fiscal year. "Our strong growth is based on our structural strength," Breuss asserted. 'There is no other manufacturer who offers such a broad spectrum of communications ICs." Siemens will sell more than 500.000 chip sets for global system for mobile communications (GSM) standard terminals and between 25 to 30 million high-frequency ICs this year. Due to the high demand for third-generation GSM ICs, there are shortages in this sector. Within the next four to five years Siemens plans to get a GSM market share of 17%. At the beginning of 1996, the next GSM chip set generation will be presented to the market. The whole GSM phone will then consist of only tree high-frequency ICs and two digital ICs, plus EEPROM and RAM. Another major growth market is in digital European cordless telephones (DECT), where Bruess expects a steep increase by mid-1994:"1995 will be the year of DECT. We are preparing to sell 250.000 DECT chip sets per month next year." The trunk switch, PBX and ISDN chip markets are also good business forthe German semiconductor manufacturer. It expects to sell "several houndreds of thousand" of its IEC-Q, a single-chip solution forthe ISDN-U interface with echo cancellation. The demand seems to be higher than Siemens' delivery capacity, and Bruess wants to expand the IEC-Q production volume to several million units per year in 1995. However, even though Bruess reports an "annual Increase of more than 500% in chips for ISDN PC cards," the IEC-Q is not used for ISDN but mainly for digitally added main line (DAML) applications, which enable the transmission of two phone calls via one twisted pair cable. SIEMENS COMMUNICATIONS IC SALES in millions of deutschemarks Electronics, March 1994 Sanyo solar cell sets efficiency standard Sanyo Electric Co. Ltd of Osaka is expanding its expertise in solar technology on two fronts - advanced technology and consumer marketing. At the cutting-edge of solar-energy conversion technology, Sanyo has announced what it claims to be the world's most efficient solar cell - a 1 -cm-square, thin-film device of polycrystalline silicon that has achieved an energy conversion rate 8.5%. When the device is used 201 Informacije M1DEM 24(1994)3, Ljubljana in conjunction with conventional amorphous silicon cells, the conversion ratio can be increased to 13%. Sanyo said the technology used is capable of a conversion ratio of as much as 20%, but further development is needed. Already developed and ready for shipment next month are Sanyo solar power generation panels for the Japanese residential market. The shipping date is timed to coincide with a 1994 Japanese government subsidy program for homeowners upgrading their homes to solar power. Up to half the upgrade costs will be shouldered by the Japanese taxpayer. A typical system costs approximately Y6 million (US$57.000). That includes solar cell module, solar inverter, electric power distribution panel, switches, installation hardware and dual kilowatt-hour meters: one to record power consumption, the other to track surplus power generation. Since passage of a 1992 law, surplus power can be sold by the homeowner to the local power company. Similar laws have been in effect in the U.S. for a number of years. Electronics, March 1994 AMS joins ESPRIT Project "FAB 2000" Austria Mikro Systeme International, together with ES2 in France, GEC-Plessey in the UK, Gressi of France and Siemens Germany will participate in the joint European ESPRIT project "FAB 2000", the aim of which is to develop new and refined fabrication methodologies for next generation of application specific integrated circuits to be implemented by the year 2000. The ultimate goal is to guarantee the competitiveness of the European semiconductor industry into the next century. Although all the participants of the ESPRIT project come from full member states of the European Union (Austria will be full member as of January 1, 1995 after a resounding yes to join the EU), AMS has also been invited because of its profound IC manufacturing experience since the company is one of the few European semiconductor manufacturers that houses all necessary fabrication facilites "under one roof": Research and development, design, mask lithography, wafer fabrication, assembly and test. Dr. Humbert Noll, head of the AMS research and development department:"As a result of the participation in the ESPRIT project AMS will provide highly specialized and valuable know-how and thus further strengthen its leading position in the field of mixed analogue/digital integrated circuits." For more information, call: Schloss Premstatten A-8141 Unterpremstâtten, Austria Telex 312547 ams a FAX (03136) 52 501, 53 650 (03136) 500-0* Dr. Conrad Heberling, ext. 277 Microtip technology: the LCD market's next leader? Microtip technology proponents hail the field-emission display (FED) technology as a high-performance, lightweight, low-power consumption FPD. Pixel International of Rousset, France, is an active advancerof microtip technology, originally developed by Laboratoire d'Electronique de Technologies et d'Instrumentation (LETI) of France. "Based on the preliminary work of Pixel and LETI, (microtip) is outstanding," said David Mentey, director of display industry research with Stanford Resources Inc. in San Jose, Calif. "It's sort of the dark horse (FDP technology) right now." Pixel has lincensed its technology to Futaba Corp. of Mobara, Japan and Texas Instruments Inc. of Dallas. Mentley also cited microtip work done by Boise-based Micron Display Technology Inc. It has three patents for cold-cathode FEDs, with 15 patents pending for its COLD CATHODE MICROTIP FED TECHNOLOGY ' , _Transparent Conductor (-500 V) Faceplate a ^ „ A, af^.vy,». Micron's FEDs consist of a series of arrays composed of sets of cold-cathode FE devices (spindt emitters) opposing a phosphor- coated transparent plate-the space between the arrays and the plate has been evacuated. The spindt emitters are activated, and electrons are accelerated from the cold-cathode devices toward the phosphor-coated plate, which serves as an anode and has a positive voltage relative to the spindt emitter arrays. The phosphor is then induced into luminescence by electrons bombarding the phosphor surface, just as with conventional cathode ray tubes. 202 Informacije M1DEM 24(1994)3, Ljubljana technology (see illustration). Micron estimates that a 10-inch, 50 fL, full-color FED would consume less than 5 watts of power. Electronics, April 1994 MOTIF BRIDGES AM/PM LCD GAP ACTIVE ADDRESSING LCD PERFORMANCE VS. COST stn) Cost Motif Inc. Motif Inc. of Wilsonville, Ore., is producing prototypes of its "active addressing" (AA) LCD technology and may begin production for OEMs by 1995, said Thomas Mills, marketing manager for Motif, a joint venture of Motorola Inc. in Schaumburg, III., and In Focus Systems Inc. of Tualatin, Ore. He said units will be evaluted in late Q2 or early 03. AA applies electrical signals to LCDs in a way that, Motif says, improves response time and contrast without limiting resolution or display size: AA-LCDs enable STN-LCDs to nearly achieve the performance of TFT-LCDs at a reduced cost (see chart). AA-LCD signals all pixels constantly and simultaneously using AA-ICs located off screen - cicuit complexity is in silicon to simplify manufacture. The initial development phase of AA-LCD targeted high-end use, such as notebook computers. In March, In Focus announced it will inject new capital into the venture - US$ 1.5 million to $3.5 million - to cover ongoing costs, increase plant capacity and begin development of a second-phase AA-LCD for handheld game, entertainment and wireless applications. Electronics, April 1994 EU alliance hopes to crack LCD market Aconsortium of European companies, led by Flat Panel Display, a subsidiary of Philips NV of Eindhoven, have allied in a European Union Esprit program to develop ferroelectric LCD technology. The companies - Thomson-LCD, Thomson Consumer Electronics, Sagem, IBM France, DRA, Merck and Barco - hope to improve the EU's dismal position in the the market for liquid crystal devices, components and sub-assemblies for panels. The project aims to develop a customized integrated circuit, a touch input system and a ferroelectric LCD which, when combined, will provide a low-cost, low-power module for use in a series of information technology products. The project is using two key advantages of ferroelectric technology: memory, the ability to retain an image with no power, and extremely low voltage. Use of the memory capability will reduce the power consumption of the display and greatly prolong battery life. The use of low voltages will reduce both the size and cost of the ICs used in the drive electronics. These two key advantages make the proposed display modules ideally suited for a wide range of new and emerging portable IT products. The project will also try to provide analog gray levels on ferroelectric LCDs, so the display can be used in video applications. Analog gray scale has not yet been suc-essfully demonstrated in a passive ferroelectric LCD. The project was launched in January 1994 and is expected to take two years to complete. Electronics, April 1994 Hyundai begins construction of 64M DRAM plant In mid-July, Hyundai Electronics Industries Co. of Seoul began construction of an 8-inch wafer fabrication plant for 64-Mbit dynamic random-access memory, in Ichon, Korea. A US$ 1.24 billion investment, the plant is projected to be completed in June 1995. Featuring 0.35 micron process rules and a Class 1 cleanroom with less than 0.05 micron particles, the plant will be optimized for the production of 64-Mbit DRAMs. However, it will produce 16-Mbit DRAMs until late 1996 or 1997, when the market for 64-Mbit DRAMs is expected to mature. When the plant is completed, Hyundai's combined monthly production capacity of 16- Mbit DRAMs will reach 9.9 million units. Hyundai expects to ship $930 million worth of 16-Mbit DRAMs to take 11% of the world's market share next year. Electronics, July 1994 203 Informacije M1DEM 24(1994)3, Ljubljana koledar prireditev 1994 SEPTEMBER 28.09.-30.09.1994 22nd INTERNATIONAL CONFERENCE ON MICROELECTRONICS, MIEL'94 30th SYMPOSIUM ON DEVICES AND MATERIALS, SD '94 TERME ZRECE, Rogla, Slovenija (Info.: Meta Limpel, Tel.: 386 61 312 898) OCTOBER 04.10.-06.04.1994 FIRST EUROPEAN DEPENDABLE COMPUTING CONFERENCE Berlin, Germany (Info.: Dr.David Powell, Tel.:(33) 61 33 62 87) 04.10.-07.10.1994 ESREF '94 5th EUROPEAN SYMPOSIUM ON RELIABILITY OF ELECTRON DEVICES, FAILURE PHYSICS AND ANALYSIS Glasgow, Scotland (Info.: G.M.Brydon, Tel.: 44 604 408647) 10.10.-11.10.1994 BIPOLAR/BICMOS CIRCUITS & TECHNOLOGY MEETING Minneapolis, MN, USA (Info.: John S.Shier, VTC Inc., Tel.:(612)853-3292) 10.10.-13.10.1994 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN:VLSI IN COMPUTERS & PROCESSORS Cambridge, MA, USA (Info.: IEEE Computer Society, Tel.:(202) 371-0101) 11.10.-13.10.1994 INTERNATIONAL DISPLAY RESEARCH CONFERENCE Monterey, CA, USA (info.: Ralph Nadel, Pallisades Institute (212) 620-3379) 16.10.1994 GALLIUM ARSENIDE RELIABILITY WORKSHOP Philadelphia, PA, USA (info.: Antony Immorlica, GE Co., (315) 456-3514) 16.10.-19.10.1994 GALLIUM ARSENIDE INTEGRATED CIRCUITS SYM-PHOSIUM Philadelphia, PA, USA (Info.: Donald D'Avanzo, Hewlett-Packard, CA, Tel.: (707) 577-2644) 31.10.-04.11.1994 INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN Santa Clara, CA, USA (Info.: IEEE Computer Society, Tel.: (202) 371-0101) NOVEMBER 14.11.-16.11.1994 TOPICAL CONFERENCE ON THE SYNTHESIS & PROCESSING OF ELECTRONIC MATERIALS San Francisco, CA, USA (Info.: Tim Anderson, Tel.: (904) 392-0881) 15.11.-16.11.1994 SEMICONDUCTOR MANUFACTURING CONFERENCE & WORKSHOP Cambridge, MA, USA (info.: Margaret Bachmeyer, Tel.: (202) 457-9584) DECEMBER 05.12.-09.12.1994 INTERNATIONAL CONFERENCE ON PHOTOVOLTAIC ENERGY CONVERSION Waikoloa, HI (Info.: Dennis J.Flood, Cleveland, Ohio, Tel.: (216) 433-2303) 204 Informacije M1DEM 24(1994)3, Ljubljana NAVODILA AVTORJEM Informacije MIDEM je znanstveno-strokovno-dru-štvena publikacija Strokovnega društva za mik-roelektroniko, elektronske sestavne dele in ma-teriale-MIDEM. Časopis objavlja prispevke domačih in tujih avtorjev, še posebej članov MIDEM, s področja mikroelektronike, elektronskih sestavnih delov in materialov, ki so lahko: izvirni znanstveni članki, predhodna sporočila, pregledni članki, razprave z znanstvenih in strokovnih posvetovanj in strokovni članki. Članki bodo recenzirani. Časopis objavlja tudi novice iz stroke, vesti iz delovnih organizacij, inštitutov in fakultet, obvestila o akcijah društva MIDEM in njegovih članov ter druge relevantne prispevke. Strokovni prispevki morajo biti pripravljeni na naslednji način 1. Naslov dela, imena in priimki avtorjev brez titul. 2. Ključne besede in povzetek (največ 250 besed), 3. Naslov dela v angleščini. 4. Ključne besede v angleščini (Key words) in podaljšani povzetek (Extended Abstract) v angleščini. 5. Uvod, glavni del, zaključek, zahvale, dodatki in literatura. 6. Imena in priimki avtorjev, titule in naslovi delovnih organizacij, v katerih so zaposleni. Ostala splošna navodila 1. V članku je potrebno uporabljati SI sistem enot oz. v oklepaju navesti alternativne enote. 2. Risbe je potrebno izdelati s tušem na pavs ali belem papirju. Širina risb naj bo do 7.5 oz. 15 cm. Vsaka risba, tabela ali fotografija naj ima številko in podnapis, ki označuje njeno vsebino. Risb, tabel in fotografij ni potrebno lepiti med tekst, ampak jih je potrebno ločeno priložiti članku. V tetetu je potrebno označiti mesto, kjer jih je potrebno vstaviti. 3. Delo je lahko napisano in bo objavljeno v kateremkoli jugoslovanskem jeziku v latinici in v angleščini. Uredniški odbor ne bo sprejel strokovnih člankov, ki ne bodo poslani v dveh izvodih. Avtorji, ki pripravljajo besedilo v urejevalnikih besedil, lahko pošljejo zapis datoteke na disketi (1.2 ali 1.44) v formatih ASCII, Wordstar (3.4, 4.0), wordperfect, word, ker bo besedilo oblikovano v programu Ventura 2.0. Grafične datoteke so lahko v formatu HPL, SLD (AutoCAD), PCX ali IMG/GEM. Avtorji so v celoti odgovorni za vsebino objavljenega sestavka. Rokopisov ne vračamo. Rokopise pošljite na naslov Uredništvo Informacije MIDEM Elektrotehniška zveza Slovenije Dunajska 10, 61000 Ljubljana UPUTE AUTORIMA Informacije MIDEM je znanstveno-stručno-druš-tvena publikacija Stručnog društva za mikroelek-troniku, elektronske sestavne dijelove i materijale - MIDEM. časopis objavljuje priloge domačih i stranih autora, naročita članova MIDEM, s podru-čja mikroelektronike, elektronskih sastavnih dije-lova in materijala koji mogu biti: izvorni znanstveni članci, predhodna priopčenja, pregledni članci, izlaganja sa znanstvenih i stručnih skupova i stručni članci. Člana če biti recenzirani. Časopis takoder objavljuje novosti iz struke, oba-vijesti iz radnih organizacija, instituta i fakulteta, obavijesti o akcijama društva MIDEM i njegovih članova i druge relevantne obavijesti. Stručni članci moraju biti pripremljeni kako slijedi 1. Naslov članka, imena i prezimena autora bez titula. 2. Ključne riječi i sažetak (najviše 250 riječi). 3. Naslov članka na engleskom jeziku. 4. Ključne riječi na engleskom jeziku (3Key Words) i produženi sažetak (Extended Abstract) na engleskom jeziku. 5. Uvod, glavni dio, zaključni dio, zahvale, dodaci i literatura. 6. Imena i prezimena autora, titule i naslovi institucija u kojima su zaposleni. Ostale opšte upute 1. U prilogu treba upotrebljavati SI sistem jedinica od. u zagradi navesti alternativne jedinice. 2. Crteže treba izraditi tušem na pausu ili bijelom papiru. Širina crteža neka bude do 7.5 odnosno 15 cm. Svaki crtež, tablica ili fotografija treba imati broj i naziv koji označuje njen sadržaj. Crteže, tabele i fotografije nije potrebno lijepiti u tekst, več ih priložiti odvojeno, a u tekstu samo naznačiti mjesto gdje doiaze. 3. Rad može biti pisan i biti če objavljen na bilo kojem od jugosiavenskih jezika u latinici i na engleskom jeziku. Autori mogu poslati radove na disketama (1.2 iii 1.44) u formatima tekst procesora ASCII, Wordstar (3.4. i 4.0), word, Wordperfect pošto če biti tekst dalje obraden u Venturi 2.0. Grafičke datoteke mogu biti u formatu HPL, SLD (AutoCAD), PCX ili IMG/GEM. Urednički odbor če odbiti sve radove koji neče biti poslani u dva primjerka. Za sadržaj članaka autori odgovaraju u potpu-nosti. Rukopisi se na vračaju. Rukopise šaljite na adresu: Uredništvo Informacije MIDEM Elektrotehnična zveza Slovenije Dunajska 10, 61000 Ljubljana Slovenija INFORMATION FOR CONTRIBUTORS Informacije MIDEM is professional-scientific-social publication of Professional Society for Microelectronics, Electronic Components and Materials. In the Journal contributions of domestic and foreign authors, especially members of MIDEM, are published covering field of microelectronics, electronic components and materials. These contributions may be: original scientific papers, preliminary communications, reviews, conference papers and professional papers. All manuscripts are subject to reviews. Scientific news, news from the companies, institutes and universities, reports on actions of MIDEM Society and its members as well as other relevant contributions are also welcome. Each contribution should include the following specific components: 1. Title of the paper and authors' names. 2. Key Words and Abstract (not more than 250 words). 3. Introduction, main text, conclusion, acknowledgements, appendix and references. 4. Authors' names, titles and complete company or institution adress. General information 1. Authors should use SI units and provide alternative units in parentheses wherever necessary. 2. Illustrations should be in black on white or tracing paper. Their width should be up to 7.5 or 15 cm. Each illustration, table or photograph should be numbered and with legend added. Illustrations, tables and photografphs are not to be placed into the text but added separately. Hower, their position in the text should be clearly marked. 3. Contributions may be written and will be published in any Yugoslav language and in english. Authors may send their files on formatted cfiskettes (1.2 or 1.44) in ASCII, Wordstar (3.4 or 4.0), word, wordperfect as text will be formated in Ventura 2.0. Graphics may be in HPL, SLD (AutoCAD), PCX or IMG/GEM formats. Papers will not be accepted unless two copies are received. Authors are fully responsible for the content of the paper. Manuscripts are not returned. Contributions are to be sent to the address: Uredništvo Informacije MIDEM Elektrotehniška zveza Slovenije Dunajska 10, 61000 Ljubljana, Slovenia 205 TERMINOLOŠKI STANDARDI 2.2 Usnerjnlne diode 1 2 3 4 2.2.1 Splošni izrazi 2.2.1.1 • Direktni (propusni) smer • Propusni (direktni) smjer • HitpcKTiia nacoKa • Prepustna smer 147—0/IC—1.1 • Forward direction • Sens direct Smer trajnega enosmernega toka, v kateri ima polprevodniška dioda manjšo upornost. 2.2.1,2 • Inverzni (nepropusni) smer • Zaporni (inverzni) smjer • HiiBep3ita nacoKa • Zaporna smer, inverzna smer 147—0/IC—1.2 • Reverse direction • Sens invers Smer trajnega enosmernega toka, v katerem ima polprevodniška dioda večjo upornost. 2.2,1.3 • Grana ispravljačkog bloka (sloga) • Grana ispravljačkog slosa • FpaiiKa na naco>iynaHKi! 5hok • Veja usmetjalncga stavka 147—0/IC-1.3 • Rectifier stack arm • Bras d'un bloc de redressement Del usmerjalnega stavka, ki je priključen med dva priključka in : ima lastnost, da prevaja tok pretežno samo v eni smeri. Opomba: Veja usmerjalnega stavka, sestavljena iz ene ali več diod, vezanih zaporedno, vzporedno ali zaporedno-vzporedno, da delujejo kot enota. To pomeni,da je veja usmerjalnega stavka lahko celotni usmerjalni stavek ali samo njegov del. 2.2,1.4 • Anodni priključak, anoda (poluprovodnič-ke ispravljačke diode ili ispravljačkog bloka) • Anodni priključak, anoda poluvodičke ispravljačke diode ili ispravljačkog sloga 147—0/IC— 1.4 • Anode terminal (of a semiconductor rectifier diode or rectifier stack) • Borne d'anode (d'une diode de redressement a semicondicteurs ou d'un bloc de redressement) Priključek, v katerega teče prepustni tok iz zunanjega tokokroga- TERMINOLOŠKI STANDARDI m o -si 1 2 3 4 • Anoflcir npuK/ry'iOK (»a nojiynpoBoaumKa naco'iyBa'iKa Aiio/ia hjtii na iiacoMyoatiKH 5hok) « Anodni priključek (polprevodniske usmer-jalne diode aJi usmerjalnega stavka) 2.2.1.5 • Katodni priključak, katoda (poluprovod-ničke ispravljačke diode ili ispravljačkog bloka) • Katodni priključak, katoda poluvodičke ispravljačke diode ili ispravljačkog sloga • KaTOflen npiiKJiyqoK (na no/iynpoBoanHM-K3 nacoiiyBaiiKa unoxta ¡trni na naco'iyBaii- ■ KM GJIOK) ® Katodni priključek (polprevodnike usmer-jalne diode ali usmerjalnega stavka) 147-0/IC—1.5 ® Cathode terminal (of a semiconductor rectifier diode or rectifier stack) • Borne de cathode (d'une diode de redressement à semiconducteurs ou d'un bloc de redressement) Priključek, iz katerega teče prepustni tok v zunanji tokokrog. 2,2.2 Izrazi, ki se nan.ašajo na mejne vrednosti in karakteristike 2,2.2.1 • Direktni (propusni) napon • Propusni (direktni) napon • U,npeKrreH nanon • Propustna napetost i 147—0/IC—-2. A • Forward "oltage » Tension directe Napetost, ki nastane na priključkih zaradi prehoda toka v prepustni smeri. 3 O 3 ® S a m l\5 tO (O £ CO C çr m" 3 B> TERMINOLOŠKI STANDARDI 1 2 3 1 2 "i o 2 • Vršni radni inverzni (nepropusni) napon • Vrini radni zaporni (inverzni) napon • Bpncu paCoicii HHBcpxii nanoii . • Temenska delovna zaporna napetost, temenska delovna inverzna napetost 147-0/IC-2.2 « Crest (peak) working reverse voltage • Tension inverse de crCte Največja trenutna vrednost zaporne napetosti, ki nastane na polprevodniki usmerjalni diodi ali veji usmerjalnega stavka, izključojoč vse ponovitvenc in neponovitvene prehodne napetosti. 2.2.2.3 • Periodični'\aSni inverzni (nepropusni) napon • Periodični vršni zaporni (inverzni) napon • nepHOflHMCIl D pBCH HHBep3CH ItanOII » Ponovitvena temenska zaporna napetost, po-novitvena temenska inverzna napetost 147—0/IC—2.3 ® Repetitive peak reverse voltage, maximum recurrent reverse voltage • Tension inverse de pointe repetitive Največja trenutna vrednost zaporne napetosti, ki nastane na polprevodniki usmeijalni diodi ali veji usmerjalnega stavka, vključojoč vse ponovitvene in izključojoč vse neponovitvene napetosti. 2.2.2.4 • Neperiodični vršni inverzni (nepropusni) napon « Neperiodični vršni zaporni (inverzni) napon • Hcncpsio/uricH apnen HHBcp3cit nanoii ® Neponovitvena temenska zaporna napetost, neponovitvena temenska inverzna napetost 147—0/IC—2.4 • Non-repetitive peak reverse voltage, peak transient reverse voltage • Tension inverse de pointe non repetitive Največja trenutna vrednost neponovitvene prehodne zaporne napetosti, ki nastane na polprevodniški usmerjalni diodi ali na veji usmerjalnega stavka. Opomba: Ponovitvena napetost je navadno funkcija vezja in povečuje izgubno moč elementa. Neponovitvena prehodna napetost se navadno pojavi zaradi zunanjega vzroka in lahko predpostavimo, da njen učinek popolnoma izgine, preden pride do naslednje prehodne napetosti. 2,2.2.5 • Konstantni (jed nosmerni) inverzni (nepropusni) napon • Konstantni (istosmjerni) zaporni (inverzni) napon • Flociojan HHBep3cit nanoii • Trajna (enosmerna) zaporna napetost, trajna (enosmerna) inverzna napetost 147—0/IC—2.5 • Continuous (direct) reverse voltage • Tension inverse continue permanente Vrednost trajne napetosti, priključena na diodo v zaporni smeri. TERMINOLOŠKI STANDARDI 1 2 3 4 2.2.2.6 • Direktna (propusna) struja • Propusna (direktna) struja • 11 upe Krita crpyja • Prepustni tok 147—0/IC—2.6 • Farward current • Courant direct Tok, ki teče skozi diodo v smeri manjše upornosti. 2.2.2.7 ® Srednja direktna (propusna) struja • Srednja propusna (direktna) struja • Cpcfliia flupcKTiia crpyja ® Povprečni prepustni tok 147—0/IC—2.7 ® Mean forward current • Courant direct moyen Povprečna vrednost prepustnega toka v celotni periodi. 2.2.2.8 • Periodična vršna direktna (propusna) struja ® Periodična vršna propusna (direktna) struja • nepHOAiNiia Bpnua AHpeKnia npyja ® Ponovitveni temenski prepustni tok 147—0/IC—2.9 • Repetitive peak forward current • Courant direct de pointe répétitif Temenska vrednost toka v .prepustni smeri, vključojoč vse ponovitvene prehodne toke. Opomba: Razmerje tega toka in povprečne vrednosti toka v prepustni smeri dobimo s faktorjem, kije odvisen od vezja in od oblike vala napajalne napetosti. 2.2.2.9 • Udarna neperiodična direktna (propusna) sLruja ® Udarna neperiodična propusna (direktna) struja • Vnapiia (iienepnoAH'n!a) AHpeKBia rrpyja • Udarni (ne po no vi t ve ni) prepustni tok 147—0/IC—2.10 • Surge (non-repetitive) forward current • Courant direct non répétitif de surcharge accidentelle Kratkotrajen impulz tokav prepustni smeri z določeno valovno obliko. 2.2.2.10 • Inverzna (nepropusna) struja • Zaporna (inverzna) struja • Mimepma crpyja • Zaporni tok, inverzni tok 147—0/IC—2.11 • Reverse current • Courant inverse Celotni tok, ki teče skozi diodo, ko se nanjo pritisne označena zaporna napetost. TERMINOLOŠKI STANDARDI 1 2 3 4 2.2.2.11 • Ukupni gubici snage • Ukupni gubici • Bi